Method for processing photomask layout data

Abstract

The present disclosure provides a method for processing photomask layout data, including: providing initial framework layer data and chip layer data, the chip layer data being used to define a chip layer, the chip layer including a chip target area having a pattern; the initial framework layer data being used to define an initial framework layer, the initial framework layer including a framework target area and a framework dummy area, the framework dummy area including a first area surrounded by the framework target area, the first area being directly opposite the chip target area, and the pattern of the initial framework layer being located in the framework target area and the framework dummy area, or only in the framework target area; obtaining framework layer data based on the initial framework layer data, the framework layer data being used to define a framework layer, the framework layer being an initial framework layer that retains only the pattern located in the framework target area; and obtaining layout layer data based on the framework layer data and the chip layer data. The present disclosure at least helps improve the accuracy of layout layer data.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a method for processing photomask layout data. Background Art

[0002] The semiconductor manufacturing process involves processing customer-provided layout data to create a photomask layout, which is then used to create a photomask. After the photomask is manufactured, the pattern on the photomask is transferred to a wafer to form a semiconductor product.

[0003] The photomask, also known as a mask or a reticle, has at least one geometric figure on it that has a light-shielding property for exposure light, which can selectively block the light irradiated on the photoresist on the wafer surface and ultimately form a corresponding pattern on the photoresist on the wafer surface.

[0004] Since the photomask is produced based on the photomask layout data, if the accuracy of the photomask layout data is poor, that is, the layout layer defined by the photomask layout data is different from the pattern of the preset photomask, it will result in the formation of a defective photomask, which will in turn affect the subsequently formed semiconductor products. Summary of the Invention

[0005] The method for processing photomask layout data provided by the embodiment of the present disclosure is at least beneficial to improving the accuracy of layout layer data.

[0006] An embodiment of the present disclosure provides a method for processing photomask layout data, comprising: providing initial frame layer data and chip layer data, the chip layer data being used to define a chip layer, the chip layer including a chip target area having a pattern, the initial frame layer data being used to define an initial frame layer, the initial frame layer including a frame target area and a frame dummy area, the frame dummy area including a first area surrounded by the frame target area, the first area being opposite to the chip target area, and the pattern of the initial frame layer being located in the frame target area and the frame dummy area, or only in the frame target area; obtaining frame layer data based on the initial frame layer data, the frame layer data being used to define a frame layer, the frame layer being an initial frame layer that only retains the pattern located in the frame target area; obtaining layout layer data based on the frame layer data and the chip layer data, the layout layer data being used to define a layout layer, the layout layer including a layout target area, the layout target area being opposite to the frame target area and the chip target area, and the layout target area having the pattern of the frame target area and the pattern of the chip target area.

[0007] In some embodiments, the step of obtaining framework layer data based on the initial framework layer data includes: providing first occlusion layer data, the first occlusion layer data is used to define a first occlusion layer, the first occlusion layer at least includes a first sub-occlusion area opposite to the first area; obtaining framework layer data based on the first occlusion layer data and the initial framework layer data.

[0008] In some embodiments, the pattern of the initial frame layer is located in the frame target area and the frame dummy area, and the pattern of the frame dummy area is located in the first area. Obtaining the frame layer data based on the first occlusion layer data and the initial frame layer data includes: using the first sub-occlusion area to remove the pattern located in the first area to obtain the frame layer data.

[0009] In some embodiments, the frame dummy area further includes a second area located outside the frame target area, and the first shielding layer further includes a second sub-shielding area directly opposite to the second area.

[0010] In some embodiments, the pattern of the initial frame layer is located in the frame target area and the frame dummy area, and the pattern of the frame dummy area is located in the first area and the second area. Obtaining the frame layer data based on the first occlusion layer data and the initial frame layer data includes: using the first sub-occlusion area to remove the pattern located in the first area, and using the second sub-occlusion area to remove the pattern located in the second area to obtain the frame layer data.

[0011] In some embodiments, providing chip layer data includes: providing initial chip layer data, the initial chip layer data is used to define the initial chip layer, the initial chip layer includes an initial chip target area and an initial chip dummy area opposite to the first area, and the pattern of the initial chip layer is located in the initial chip target area and the initial chip dummy area, or only in the initial chip target area; providing second occlusion layer data, the second occlusion layer data is used to define a second occlusion layer, the second occlusion layer has a second occlusion area opposite to the initial chip dummy area; obtaining chip layer data based on the second occlusion layer data and the initial chip layer data, the chip layer is an initial chip layer that only retains the pattern located in the initial chip target area.

[0012] In some embodiments, the pattern of the initial chip layer is located in the initial chip target area and the initial chip dummy area. The step of obtaining chip layer data based on the second occluding layer data and the initial chip layer data includes: using the second occluding area to remove the pattern located in the initial chip dummy area to obtain chip layer data.

[0013] In some embodiments, the first area includes at least two independent first partitions and a second partition; providing chip layer data includes at least: providing first chip layer data and second chip layer data, the first chip layer data is used to define the first chip layer, the first chip layer includes a first chip dummy area and a first chip target area opposite to the first partition, the second chip layer data is used to define the second chip layer, the second chip layer includes a second chip dummy area and a second chip target area opposite to the second partition; obtaining layout layer data based on the framework layer data and the chip layer data includes: obtaining layout layer data based on the first chip layer data, the second chip layer data and the framework layer data.

[0014] In some embodiments, providing first chip layer data includes: providing initial first chip layer data, the initial first chip layer data is used to define the initial first chip layer, the initial first chip layer includes an initial first chip dummy area and an initial first chip target area opposite to the first partition, the pattern of the initial first chip layer is located in the initial first chip target area and the initial first chip dummy area, or only in the initial first chip target area; providing third occlusion layer data, the third occlusion layer data is used to define a third occlusion layer, the third occlusion layer has a third occlusion area opposite to the initial first chip dummy area; obtaining first chip layer data based on the third occlusion layer data and the initial first chip layer data, the first chip layer is the initial first chip layer that only retains the pattern located in the initial first chip target area.

[0015] In some embodiments, the pattern of the initial first chip layer is located in the initial first chip target area and the initial first chip dummy area. The step of obtaining the first chip layer data based on the third occluding layer data and the initial first chip layer data includes: using the third occluding area to remove the pattern located in the initial first chip dummy area to obtain the first chip layer data.

[0016] In some embodiments, providing second chip layer data includes: providing initial second chip layer data, the initial second chip layer data is used to define the initial second chip layer, the initial second chip layer includes an initial second chip dummy area and an initial second chip target area opposite to the second partition, the pattern of the initial second chip layer is located in the initial second chip target area and the initial second chip dummy area, or only in the initial second chip target area; providing fourth occluding layer data, the fourth occluding layer data is used to define a fourth occluding layer, the fourth occluding layer has a fourth occluding area opposite to the initial second chip dummy area; obtaining second chip layer data based on the fourth occluding layer data and the initial second chip layer data, the second chip layer is the initial second chip layer that only retains the pattern located in the initial second chip target area.

[0017] In some embodiments, the pattern of the initial second chip layer is located in the initial second chip target area and the initial second chip dummy area. The step of obtaining the second chip layer data based on the fourth occluding layer data and the initial second chip layer data includes: using the fourth occluding area to remove the pattern located in the initial second chip dummy area to obtain the second chip layer data.

[0018] In some embodiments, the step of obtaining layout layer data based on the framework layer data and the chip layer data includes: merging the framework layer data with the chip layer data to obtain the layout layer data.

[0019] In some embodiments, the frame dummy area also includes a second area located outside the frame target area, and the step of obtaining layout layer data based on the frame layer data and the chip layer data includes: providing fifth occlusion layer data, the fifth occlusion layer data is used to define the fifth occlusion layer, and the fifth occlusion layer has a fifth occlusion area opposite to the second area; obtaining layout layer data based on the fifth occlusion layer data, the frame layer data and the chip layer data.

[0020] In some embodiments, obtaining layout layer data based on the fifth occlusion layer data, the framework layer data, and the chip layer data includes: merging the framework layer data with the chip layer data and performing inversion processing to obtain initial layout layer data, the initial layout layer data is used to define the initial layout layer, the initial layout layer includes an initial layout target area and an initial layout dummy area opposite to the second area, the pattern of the initial layout layer is located in the initial layout target area and the initial layout dummy area, or only in the initial layout target area; obtaining layout layer data based on the fifth occlusion layer data and the initial layout layer data, the layout layer is an initial layout layer that only retains the pattern located in the initial layout target area.

[0021] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: in the above technical solution, the initial framework layer data and the chip layer data can both be the layer data initially provided by the design department, the chip layer data is used to define the chip layer, the chip layer includes a chip target area with a pattern, the pattern of the chip target area is the same as the pattern of the chip area of the photomask manufactured subsequently, the initial framework layer data is used to define the initial framework layer, the initial framework layer includes a framework dummy area and a framework target area with a pattern, the pattern of the framework target area is the same as the pattern of the frame area of the photomask manufactured subsequently, the pattern of the frame area is the pattern of the scribing road or the cutting road, the framework dummy area includes a first area that is directly opposite to the chip target area, and when the layout layer is subsequently formed, the pattern of the chip target area falls within the first area to obtain a layout layer that merges the chip target area and the framework target area. In the technical solution provided by the embodiment of the present disclosure, the initial framework layer data initially provided by the design department is processed to obtain a framework layer with the pattern located in the dummy area of the framework removed, that is, to obtain the framework layer data, to ensure that the dummy area of the framework layer merged with the chip layer is free of patterns, to prevent the pattern in the dummy area from being merged into the layout layer during the subsequent formation of the layout layer and affecting the formed layout layer, which is beneficial to improving the accuracy of the layout layer data. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 A schematic structural diagram of a chip layer provided in an embodiment of the present disclosure;

[0024] Figure 2 A schematic structural diagram of another chip layer provided in an embodiment of the present disclosure;

[0025] Figure 3 A schematic diagram of the structure of an initial framework layer provided in an embodiment of the present disclosure;

[0026] Figure 4 A schematic diagram of the structure of another initial framework layer provided in an embodiment of the present disclosure;

[0027] Figure 5A schematic diagram of the structure of another initial framework layer provided in an embodiment of the present disclosure;

[0028] Figure 6 A schematic diagram of the structure of another initial framework layer provided in an embodiment of the present disclosure;

[0029] Figure 7 A schematic diagram of the structure of a framework layer provided in an embodiment of the present disclosure;

[0030] Figures 8 to 18 A schematic diagram of each step of the method for processing photomask layout data provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] As known from the background art, if the layout layer defined by the photomask layout data is different from the pattern on the preset photomask, it will result in the formation of a defective photomask, thereby affecting the subsequently formed semiconductor products.

[0032] After analysis, it was found that the layout layer is usually drawn using design software, and the drawn layout layer is provided to the photomask manufacturer in the form of a file. The photomask manufacturer manufactures the photomask according to the layout layer file (layout layer data). The pattern of the chip area of the photomask is determined by the pattern of the chip area of the layout layer, and the pattern of the frame area of the photomask is determined by the pattern of the frame area of the layout layer. The pattern of the chip area of the layout layer is the pattern formed on the chip wafer or substrate in the process of forming the chip, and the pattern of the frame area of the layout layer is the pattern formed on the wafer or substrate around the chip in the process of forming the chip. That is to say, the pattern of the frame area corresponds to the scribing road or cutting road. In the related technology, the layout The pattern of the chip area of the diagram layer and the pattern of the frame area of the layout layer are provided by different design departments, that is, at least two sets of layer data are provided, namely, the two sets of layer data are layer data corresponding to the frame area and the layer data corresponding to the chip area, and the two sets of layer data are merged to obtain the layout layer data. Among them, if the layer data corresponding to the frame area provided by the design department originally has an area without any pattern but has an unexpected pattern due to design errors or other reasons, these unexpected patterns, if located in the area corresponding to the chip area, will overlap with the pattern of the chip area, resulting in the formation of an abnormal pattern in the chip area, and then resulting in the formation of an abnormal photomask, which will affect the semiconductor product formed using the photomask.

[0033] To solve the above problems, an embodiment of the present disclosure provides a method for processing photomask layout data, wherein the initial framework layer data and the chip layer data can both be layer data initially provided by the design department, the chip layer data is used to define the chip layer, the chip layer includes a chip target area with a pattern, the pattern of the chip target area is the same as the pattern of the chip area of the photomask manufactured subsequently, the initial framework layer data is used to define the initial framework layer, the initial framework layer includes a framework dummy area and a framework target area with a pattern, the pattern of the framework target area is the same as the pattern of the frame area of the photomask manufactured subsequently, the pattern of the frame area is the pattern of the scribing street or the cutting street, the framework dummy area includes a first area directly opposite to the chip target area, when the layout layer is subsequently formed, the pattern of the chip target area falls within the first area to obtain a layout layer that merges the chip target area and the framework target area. In the technical solution provided by the embodiment of the present disclosure, the initial framework layer data initially provided by the design department is processed to obtain a framework layer with the pattern located in the framework dummy area in the initial framework layer removed, that is, to obtain the framework layer data, so as to ensure that the dummy area of the framework layer merged with the chip layer is free of patterns, which is beneficial to prevent the pattern in the dummy area from being merged into the layout layer in the subsequent process of forming the layout layer, thereby affecting the formed layout layer, that is, it is beneficial to improve the accuracy of the merged layout layer data.

[0034] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0035] Figure 1 A schematic structural diagram of a chip layer provided in an embodiment of the present disclosure; Figure 2 A schematic structural diagram of another chip layer provided in an embodiment of the present disclosure; Figure 3 A schematic diagram of the structure of an initial framework layer provided in an embodiment of the present disclosure;

[0036] Figure 4 A schematic diagram of the structure of another initial framework layer provided in an embodiment of the present disclosure; Figure 5 A schematic diagram of the structure of another initial framework layer provided in an embodiment of the present disclosure; Figure 6 A schematic diagram of the structure of another initial framework layer provided in an embodiment of the present disclosure; Figure 7 A schematic diagram of the structure of a framework layer provided in an embodiment of the present disclosure.

[0037] It should be noted that the layer data involved in the embodiments of the present disclosure, such as the initial framework layer data, chip layer data, and layout layer data, are all data files designed and drawn by layout design software. The layout design software can be common design software in the field that has functions such as integrated circuit design, simulation verification, layout editing, and automatic layout and routing. The layer data involved in the embodiments of the present disclosure can be in the format of a common GDS file, with a layer being the specific representation of the layer data, and each layer data has a corresponding layer.

[0038] The processing method of photomask layout data includes: Figures 1 to 7 , providing initial frame layer data and chip layer data, the chip layer data is used to define the chip layer 100, the chip layer 100 includes a chip target area 110 with a pattern and a chip dummy area 120 outside the chip target area, the initial frame layer data is used to define the initial frame layer 200, the initial frame layer 200 includes a frame target area 210 and a frame dummy area 220, the frame dummy area 220 includes a first area 221 surrounded by the frame target area 210, the first area 221 is opposite to the chip target area 110, reference Figure 5 and Figure 6 , and the pattern of the initial frame layer 200 is located in the frame target area 210 and the frame dummy area 220, or reference 3 and Figure 4 , the pattern of the initial frame layer 200 is only located in the frame target area 210 .

[0039] Among them, the initial framework layer data and the chip layer data can both be the layer data initially provided by the design department. The chip layer data is used to define the chip layer 100. The chip layer 100 includes a chip target area 110 with a pattern. The pattern of the chip target area 110 is the same as the pattern of the chip area of the photomask manufactured subsequently. The initial framework layer data is used to define the initial framework layer 200. The initial framework layer 200 includes a framework dummy area 220 and a framework target area 210 with a pattern. The pattern of the framework target area 210 is the same as the pattern of the frame area of the photomask manufactured subsequently. The pattern of the frame area is the pattern of the scribing street or the cutting street. The framework dummy area 220 includes a first area 221 that is opposite to the chip target area 110. When the layout layer is subsequently formed, the pattern of the chip target area 110 falls within the first area 221 to obtain a layout layer that merges the chip target area 110 and the framework target area 210.

[0040] For target areas such as the chip target area 110, the frame target area 210 and the subsequent layout target area with patterns, the patterns of the target areas are usually composed of transparent parts and non-transparent parts. For example, Figure 1 The light-transmitting portion 111 of the chip target area 110 of the chip layer 100 is Figure 2The non-light-transmissive portion 112 of the chip target area 110 of the chip layer 100 is facing the Figure 1 The non-transparent portion 112 of the chip target area 110 of the chip layer 100 is Figure 2 The light-transmitting portion 111 of the chip target area 110 of the chip layer 100 is facing the Figure 1 and Figure 2 The chip layer 100 is an inverse of the other. Similarly, the frame target area 210 of the initial frame layer 200 is also composed of a transparent portion 211 and a non-transparent portion 212. The patterns of the transparent portion 211 and non-transparent portion 212 of the frame target area 210, as well as the transparent portion 111 and non-transparent portion 112 of the chip target area 110, are determined based on the design of a specific layer of the semiconductor product.

[0041] Taking the initial frame layer 200 as an example, theoretically, it is hoped that the pattern of the initial frame layer 200 is only located in the frame target area 210, such as Figure 3 and Figure 4 However, in actual application, due to design errors or other reasons, the pattern of the initial frame layer 200 is located not only in the frame target area 210, but also in the frame dummy area 220, such as Figure 5 and Figure 6 Reference Figure 3 、 Figures 5 to 7 The disclosed embodiment does not distinguish between these two situations during data processing. Instead, it directly processes the initial framework layer data obtained from the design department. Specifically, it obtains framework layer data for defining framework layer 300 based on the initial framework layer data, so that framework layer 300 is the initial framework layer 200 that retains only the pattern located in the framework target area 210. This ensures, on the one hand, that the dummy areas of the framework layer 300 merged with the chip layer 100 are all free of patterns, preventing the patterns in the dummy areas from being merged into the layout layer during the subsequent formation of the layout layer, thereby affecting the formed layout layer 400. This helps improve the accuracy of the merged layout layer data. On the other hand, it avoids additional differentiation or identification of the obtained initial framework layer data, which helps reduce the complexity of photomask layout data processing and avoids subsequent problems caused by identification errors. This improves the accuracy of the layout layer data while also reducing labor costs.

[0042] The following will Figure 1 The chip layer 100 and Figure 3 、 Figures 5 and 6 Taking the initial framework layer 200 as an example, the method for processing the photomask layout data is described in detail. Figures 8 to 18 A schematic diagram of each step of the method for processing photomask layout data provided in an embodiment of the present disclosure.

[0043] refer to Figures 8 to 10 In some embodiments, the step of obtaining the framework layer data based on the initial framework layer data includes: providing first occlusion layer data, the first occlusion layer data is used to define the first occlusion layer 500, the first occlusion layer 500 at least includes a first sub-occlusion area 501 that is opposite to the first area 221, so that the initial framework layer data is processed using the first occlusion layer data, and the pattern located in the first area 221 can be filtered out using the first sub-occlusion area 501 to obtain the framework layer data based on the first occlusion layer data and the initial framework layer data.

[0044] There are two cases for filtering out the pattern in the first area 221. In some embodiments, referring to Figure 8 , the first area 221 of the initial frame layer 200 is an area without a pattern. At this time, after the first area 221 is filtered out using the first sub-blocking area, the first area 221 is still an area without a pattern. Figure 9 In other embodiments, the pattern of the initial frame layer 200 is located in the frame target area 210 and the frame dummy area 220, and the pattern of the frame dummy area 220 is located in the first area 221. Pattern 10 is the pattern located in the first area 221. Obtaining the frame layer data based on the first occlusion layer data and the initial frame layer data includes: using the first sub-occlusion area 501 to remove the pattern located in the first area 221 to obtain the frame layer data. In this way, the undesired pattern located in the frame dummy area 220 is removed, and the frame layer 300 is obtained in which the dummy area does not have a pattern state, that is, the frame layer data is obtained, which helps to improve the accuracy of the merged layout layer data.

[0045] It should be noted that processing the initial frame layer data using the first occlusion layer data includes performing a Boolean operation on the first occlusion layer data and the initial frame layer data using software. Specifically, the initial frame layer data and the first occlusion layer data can be subtracted to obtain the frame layer data. Subsequent processing of the layer using the occlusion layer can all be performed by subtracting the data using Boolean operations.

[0046] In some embodiments, the frame dummy area 220 further includes a second area 222 located outside the frame target area 210, and the first shielding layer 500 further includes a second sub-shielding area 502 directly opposite the second area 222. The second sub-shielding area 502 is used to filter out patterns located in the second area 222, thereby ensuring that the second area 222, serving as a dummy area, is free of patterns. This results in a frame layer 300 in which all dummy areas are free of patterns, thereby improving the accuracy of the merged layout layer data.

[0047] Filtering the pattern located in the second area 222 includes two situations. In some embodiments, the second area 222 is an area without a pattern. In this case, after filtering the second area 222 using the second sub-blocking area, the second area 222 is still an area without a pattern. In other embodiments, the pattern of the initial frame layer 200 is located in the frame target area 210 and the frame dummy area 220, and the pattern of the frame dummy area 220 is located in the second area 222. Obtaining the frame layer data based on the first blocking layer data and the initial frame layer data includes: using the second blocking area 511 to remove the pattern located in the second area 222 to obtain the frame layer data.

[0048] In some embodiments, reference Figure 10 The pattern of the initial frame layer 200 is located in the frame target area 210 and the frame dummy area 220. The pattern 10 is the pattern located in the frame dummy area 220, and the pattern of the frame dummy area 220 is located in the first area 221 and the second area 222. Based on the first occlusion layer data and the initial frame layer data, the frame layer data is obtained by using the first sub-occlusion area 501 to remove the pattern located in the first area 221, and using the second sub-occlusion area 502 to remove the pattern located in the second area 222, so as to obtain the frame layer data. In this way, after processing the initial frame layer 200 using the first occlusion layer 500, a frame layer 300 is obtained in which all dummy areas have no patterns, which is conducive to improving the accuracy of the merged layout layer data.

[0049] It should be noted that the area outside the first sub-shielding area 501 and the second sub-shielding area 502 of the first shielding layer 500 is a first shielding dummy area 503 without any pattern. The first shielding layer 500 can be a layer drawn based on the initial framework layer 200 using design software.

[0050] refer to Figures 11 to 12In some embodiments, providing chip layer data includes: providing initial chip layer data, the initial chip layer data is used to define an initial chip layer 130, the initial chip layer 130 includes an initial chip target area 131 opposite to the first area and an initial chip dummy area 132 outside the initial chip target area 131, and the pattern of the initial chip layer 130 is located in the initial chip target area 131 and the initial chip dummy area 132, or only in the initial chip target area 131; providing second occlusion layer data, the second occlusion layer data is used to define a second occlusion layer 510, the second occlusion layer 510 has a second occlusion area 511 opposite to the initial chip dummy area 132; obtaining chip layer data based on the second occlusion layer data and the initial chip layer data, the chip layer 100 is the initial chip layer 130 that only retains the pattern located in the initial chip target area 131. Among them, the initial chip layer data can be the layer data initially provided by the design department. By using the second masking layer data to process the initial chip layer data, a chip layer 100 with no pattern state in the virtual area can be obtained, thereby obtaining chip layer data, which is beneficial to improving the accuracy of the subsequent layout layer data obtained based on the chip layer data.

[0051] Obtaining chip layer data based on the second occlusion layer data and the initial chip layer data includes the following two cases. In some embodiments, reference Figure 11 , the pattern of the initial chip layer 130 is only located in the initial chip target area 131, and the step of obtaining the chip layer data based on the second shielding layer data and the initial chip layer data includes: using the second shielding area 511 to filter out the initial chip dummy area 132 to obtain the chip layer data. In other embodiments, referring to Figure 12 The pattern of the initial chip layer 130 is located in the initial chip target area 131 and the initial chip dummy area 132. The pattern 10 is the pattern located in the initial chip dummy area 132. The step of obtaining chip layer data based on the second shielding layer data and the initial chip layer data includes: using the second shielding layer 511 to remove the pattern located in the initial chip dummy area 132 to obtain chip layer data. That is, regardless of whether the pattern of the initial chip layer 130 is located in the initial chip dummy area 132, the second shielding layer data is used to process the initial chip layer data to obtain a chip layer 100 in which the dummy area has no pattern. This method, on the one hand, helps prevent the pattern in the dummy area from being merged into the layout layer during the subsequent formation of the layout layer, thereby affecting the formed layout layer 400, thereby improving the accuracy of the merged layout layer data. On the other hand, it avoids additional differentiation or screening of the initial chip layer data, thereby reducing the complexity of photomask layout data processing.

[0052] It should be noted that the area outside the second shielding area 511 of the second shielding layer 510 is a second shielding dummy area 512 without any pattern. The second shielding layer 510 can be a layer drawn based on the initial chip layer 130 using design software.

[0053] In some embodiments, reference Figure 13 , the first area 221 includes at least two independent first partitions 2211 and a second partition 2212; providing chip layer data includes at least: providing first chip layer data and second chip layer data, the first chip layer data is used to define the first chip layer 140, the first chip layer 140 includes a first chip dummy area 142 and a first chip target area 141 opposite to the first partition 2211, the second chip layer data is used to define the second chip layer 150, the second chip layer 150 includes a second chip dummy area 152 and a second chip target area 151 opposite to the second partition 2212; obtaining layout layer data based on the framework layer data and the chip layer data includes: obtaining layout layer data based on the first chip layer data, the second chip layer data and the framework layer data. That is, the chip layer data initially provided by the design department can be multiple independent layers. This is because the chip pattern formed using a photomask may include multiple different modules. Different modules occupy different areas on the wafer and have different functions. Therefore, the layer data used to form different modules can be drawn separately to reduce the difficulty of obtaining chip layer data. Furthermore, in the subsequent process of forming layout layer data, the multiple layer data of different modules are merged with the framework layer data to obtain the layout layer data.

[0054] In some embodiments, reference Figure 14Providing first chip layer data includes: providing initial first chip layer data, the initial first chip layer data is used to define an initial first chip layer 160, the initial first chip layer 160 includes an initial first chip dummy area 162 and an initial first chip target area 161 opposite to the first partition 2211, and the pattern of the initial first chip layer 160 is located in the initial first chip target area 161 and the initial first chip dummy area 162, or only in the initial first chip target area 161; providing third shading layer data, the third shading layer data is used to define a third shading layer 520, the third shading layer 520 has a third shading area 521 opposite to the initial first chip dummy area 162; obtaining first chip layer data based on the third shading layer data and the initial first chip layer data, the first chip layer 140 is the initial first chip layer 160 that only retains the pattern located in the initial first chip target area 161. By processing the initial first chip layer data using the third blocking layer data, the first chip layer data corresponding to the first chip layer 140 in which all dummy areas have no pattern state can be obtained, which is beneficial to improving the accuracy of the layout layer data subsequently obtained based on the first chip layer data.

[0055] Obtaining chip layer data based on the third occlusion layer data and the initial first chip layer data includes the following two situations: In some embodiments, the pattern of the initial first chip layer 160 is only located in the initial first chip target area 161, and the step of obtaining the first chip layer data based on the third occlusion layer data and the initial first chip layer data includes: using the third occlusion area 521 to filter out the initial first chip dummy area 162 to obtain chip layer data. In other embodiments, referring to Figure 14 The pattern of the initial first chip layer 160 is located in the initial first chip target area 161 and the initial first chip dummy area 162. Pattern 10 is the pattern located in the initial first chip dummy area 162. The step of obtaining the first chip layer data based on the third shielding layer data and the initial first chip layer data includes: using the third shielding layer 521 to remove the pattern located in the initial first chip dummy area 162 to obtain the first chip layer data. That is, regardless of whether the pattern of the initial first chip layer 160 is located in the initial first chip dummy area 162, the initial first chip layer data is processed using the third shielding layer data to obtain the first chip layer data corresponding to the first chip layer 140 in which the dummy area has no pattern. This method, on the one hand, helps prevent the pattern in the dummy area from being merged into the layout layer 400 during the subsequent formation of the layout layer 400, thereby improving the accuracy of the merged layout layer data. On the other hand, it avoids additional differentiation or screening of the initial first chip layer data, thereby reducing the complexity of photomask layout data processing.

[0056] It should be noted that the area outside the third shielding area 521 of the third shielding layer 520 is a third shielding dummy area 522 without any pattern. The third shielding layer 520 can be a layer drawn based on the initial first chip layer 160 using design software.

[0057] In some embodiments, reference Figure 15 Providing second chip layer data includes: providing initial second chip layer data, the initial second chip layer data is used to define an initial second chip layer 170, the initial second chip layer 170 includes an initial second chip dummy area 172 and an initial second chip target area 171 opposite to the second partition 2212, and the pattern of the initial second chip layer 170 is located in the initial second chip target area 171 and the initial second chip dummy area 172, or only in the initial second chip target area 171; providing fourth shading layer data, the fourth shading layer data is used to define a fourth shading layer 530, the fourth shading layer 530 has a fourth shading area 531 opposite to the initial second chip dummy area 172; obtaining second chip layer data based on the fourth shading layer data and the initial second chip layer data, the second chip layer 150 is the initial second chip layer 170 that only retains the pattern located in the initial second chip target area 171. By processing the initial second chip layer data using the fourth blocking layer data, a second chip layer 150 in which all dummy areas have no pattern can be obtained, thereby obtaining second chip layer data, which is beneficial to improving the accuracy of subsequent layout layer data obtained based on the second chip layer data.

[0058] Obtaining chip layer data based on the fourth shading layer data and the initial second chip layer data includes the following two situations: In some embodiments, the pattern of the initial second chip layer 170 is only located in the initial second chip target area 171, and the step of obtaining the second chip layer data based on the fourth shading layer data and the initial second chip layer data includes: using the fourth shading area 531 to filter out the initial second chip dummy area 172 to obtain chip layer data. In other embodiments, referring to Figure 15The pattern of initial second chip layer 170 is located in initial second chip target area 171 and initial second chip dummy area 172. Pattern 10 is the pattern located in initial second chip dummy area 172. The step of obtaining second chip layer data based on the fourth shielding layer data and the initial second chip layer data includes: using the fourth shielding layer 531 to remove the pattern located in initial second chip dummy area 172 to obtain second chip layer data. That is, regardless of whether the pattern of initial second chip layer 170 is located in initial second chip dummy area 172, the fourth shielding layer data is used to process the initial second chip layer data to obtain second chip layer 150 in which the dummy areas are all patternless. This method, on the one hand, helps prevent the pattern in the dummy area from being merged into the layout layer during the subsequent formation of the layout layer, thereby affecting the formed layout layer, thereby improving the accuracy of the merged layout layer data. On the other hand, it avoids additional differentiation or screening of the initial second chip layer data, thereby reducing the complexity of photomask layout data processing.

[0059] It should be noted that the area outside the fourth shielding region 531 of the fourth shielding layer 530 is a fourth shielding dummy region 532 without any pattern. The fourth shielding layer 530 can be a layer drawn based on the initial second chip layer 170 using design software.

[0060] refer to Figures 16 to 18 , layout layer data is obtained based on the frame layer data and the chip layer data. The layout layer data is used to define the layout layer 400. The layout layer 400 includes a layout target area 410. The layout target area 410 is opposite to the frame target area 210 and the chip target area 110, and the layout target area 410 has the pattern of the frame target area 210 and the pattern of the chip target area 110. The layout layer data is the photomask layout data. The pattern of the photomask formed according to the layout layer data is consistent with the pattern of the layout target area 410 of the layout layer 400. The layout layer 400 can be Figure 16 The layout layer 400 shown in FIG can also be Figure 18 The layout layer 400 shown in FIG. Figure 16 The layout layer 400 is shown with Figure 18 The layout layers 400 shown are mutually inverted layers. Figure 16 The photomask formed by the layout layer 400 shown is a positive mask, so based on Figure 18The photomask formed by the layout layer 400 shown is a negative mask. By processing the initial framework layer data and initial chip layer data in the aforementioned method, framework layer data and chip layer data are obtained, in which the dummy regions all have no pattern. The layout layer data obtained based on the framework layer data and chip layer data is highly accurate, facilitating the formation of a photomask with minimal error.

[0061] refer to Figure 16 In some embodiments, the step of obtaining layout layer data based on the framework layer data and the chip layer data may include merging the framework layer data with the chip layer data to obtain the layout layer data. Merging the framework layer data with the chip layer data may include performing a Boolean operation on the first occlusion layer data and the initial framework layer data using software. Specifically, the framework layer 300 may be directly combined with the chip layer 100 to obtain the layout layer 400.

[0062] refer to Figures 17 and 18 In some embodiments, the frame dummy area 220 further includes a second area 222 located outside the frame target area 210, and the frame dummy area 220 is obtained based on the frame layer data and the chip layer data. Figure 16 The steps for forming the layout layer with the inverted layout layer shown may include: providing fifth occlusion layer data, the fifth occlusion layer data being used to define a fifth occlusion layer 540, the fifth occlusion layer 540 having a fifth occlusion area 541 directly opposite the second area 222; and obtaining layout layer data based on the fifth occlusion layer data, the framework layer data, and the chip layer data. The fifth occlusion area 541 directly opposite the second area 222 also directly opposite the layout dummy area 420. Forming the layout layer data using the fifth occlusion layer data, the framework layer data, and the chip layer data ensures that the layout dummy area 420 is patternless, thereby generating layout layer data with higher accuracy.

[0063] Continue to refer Figures 17 and 18In some embodiments, obtaining layout layer data based on the fifth occlusion layer data, the framework layer data, and the chip layer data includes: merging the framework layer data with the chip layer data and performing inversion processing to obtain initial layout layer data, the initial layout layer data is used to define an initial layout layer 430, the initial layout layer 430 includes an initial layout target area 431 and an initial layout dummy area 432 directly opposite the second area 222, the pattern of the initial layout layer 430 is located in the initial layout target area 431 and the initial layout dummy area 432, or only in the initial layout target area 431; obtaining layout layer data based on the fifth occlusion layer data and the initial layout layer data, the layout layer 400 is the initial layout layer 430 that only retains the pattern located in the initial layout target area 431. That is, regardless of whether the pattern of the initial layout layer 430 is located in the initial layout dummy area 432, the fifth blocking layer data is used to process the initial layout layer data to obtain a layout layer 400 in which the dummy area has no pattern, and then obtain the layout layer data. In this way, on the one hand, it is helpful to prevent the layout dummy area 420 from having a pattern; on the other hand, it avoids additional differentiation or identification of the initial layout layer data, which is helpful to reduce the complexity of processing the photomask layout data.

[0064] It should be noted that the area outside the fifth shielding region 541 of the fifth shielding layer 540 is a fifth shielding dummy region 542 without any pattern. The fifth shielding layer 540 may be a layer drawn using design software based on the initial layout layer 430. Merging the framework layer data with the chip layer data and then performing inversion processing may be a Boolean operation using software to invert the merged framework layer data and the chip layer data.

[0065] In the method for processing photomask layout data provided in the above embodiment, the layer data initially provided by the design department is processed to obtain a framework layer 300 with the pattern located in the framework dummy area 220 in the initial framework layer 200 removed, that is, to obtain framework layer data, to ensure that the dummy area of the framework layer 300 merged with the chip layer 100 does not have a pattern, to prevent the pattern in the dummy area from being merged into the layout layer 400 during the subsequent formation of the layout layer 400 and affecting the formed layout layer 400, which is beneficial to improving the accuracy of the merged layout layer data.

[0066] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present disclosure. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope defined in the claims.

Claims

1. A method for processing photomask layout data, characterized in that: include: Providing initial frame layer data and chip layer data, wherein the chip layer data is used to define a chip layer, wherein the chip layer includes a chip target area having a pattern, and the initial frame layer data is used to define an initial frame layer, wherein the initial frame layer includes a frame target area and a frame dummy area, wherein the frame dummy area includes a first area surrounded by the frame target area, the first area being opposite to the chip target area, and the pattern of the initial frame layer is located in the frame target area and the frame dummy area, or only in the frame target area; Obtaining framework layer data based on the initial framework layer data, wherein the framework layer data is used to define a framework layer, wherein the framework layer is the initial framework layer that only retains the pattern located in the framework target area; Layout layer data is obtained based on the frame layer data and the chip layer data. The layout layer data is used to define a layout layer. The layout layer includes a layout target area. The layout target area is opposite to the frame target area and the chip target area. The layout target area has a pattern of the frame target area and a pattern of the chip target area.

2. The method for processing photomask layout data according to claim 1, wherein: The step of obtaining the framework layer data based on the initial framework layer data comprises: Providing first occlusion layer data, wherein the first occlusion layer data is used to define a first occlusion layer, wherein the first occlusion layer at least includes a first sub-occlusion area directly opposite to the first area; The framework layer data is obtained based on the first occlusion layer data and the initial framework layer data.

3. The method for processing photomask layout data according to claim 2, wherein: The pattern of the initial frame layer is located in the frame target area and the frame dummy area, and the pattern of the frame dummy area is located in the first area. The frame layer data is obtained based on the first occlusion layer data and the initial frame layer data, including: The first sub-blocking area is used to remove the pattern located in the first area to obtain the framework layer data.

4. The method for processing photomask layout data according to claim 2, wherein: The frame dummy area further includes a second area located at the periphery of the frame target area, and the first shielding layer further includes a second sub-shielding area directly opposite to the second area.

5. The method for processing photomask layout data according to claim 4, wherein: The pattern of the initial frame layer is located in the frame target area and the frame dummy area, and the pattern of the frame dummy area is located in the first area and the second area. The frame layer data is obtained based on the first occlusion layer data and the initial frame layer data, including: The first sub-blocking area is used to remove the pattern located in the first area, and the second sub-blocking area is used to remove the pattern located in the second area, so as to obtain the framework layer data.

6. The method for processing photomask layout data according to claim 1, wherein: Providing the chip layer data includes: Providing initial chip layer data, the initial chip layer data being used to define an initial chip layer, the initial chip layer including an initial chip target area and an initial chip dummy area directly opposite the first area, wherein a pattern of the initial chip layer is located in the initial chip target area and the initial chip dummy area, or only in the initial chip target area; Providing second shielding layer data, wherein the second shielding layer data is used to define a second shielding layer, wherein the second shielding layer has a second shielding area directly opposite to the initial chip dummy area; The chip layer data is obtained based on the second shielding layer data and the initial chip layer data, and the chip layer is the initial chip layer that only retains the pattern located in the initial chip target area.

7. The method for processing photomask layout data according to claim 6, wherein: The pattern of the initial chip layer is located in the initial chip target area and the initial chip dummy area, and the step of obtaining the chip layer data based on the second shielding layer data and the initial chip layer data includes: The second shielding area is used to remove the pattern located in the initial chip dummy area to obtain the chip layer data.

8. The method for processing photomask layout data according to claim 1, wherein: The first area includes at least two mutually independent first subareas and a second subarea; Providing the chip layer data at least includes: Providing first chip layer data and second chip layer data, wherein the first chip layer data is used to define a first chip layer, the first chip layer including a first chip dummy area and a first chip target area directly opposite the first subarea; and the second chip layer data is used to define a second chip layer, the second chip layer including a second chip dummy area and a second chip target area directly opposite the second subarea; Obtaining the layout layer data based on the framework layer data and the chip layer data includes: obtaining the layout layer data based on the first chip layer data, the second chip layer data, and the framework layer data.

9. The method for processing photomask layout data according to claim 8, wherein: Providing the first chip layer data includes: Providing initial first chip layer data, the initial first chip layer data being used to define an initial first chip layer, the initial first chip layer including an initial first chip dummy area and an initial first chip target area directly opposite the first subarea, and a pattern of the initial first chip layer being located in the initial first chip target area and the initial first chip dummy area, or only in the initial first chip target area; Providing third shielding layer data, wherein the third shielding layer data is used to define a third shielding layer, wherein the third shielding layer has a third shielding area directly opposite to the initial first chip dummy area; The first chip layer data is obtained based on the third shielding layer data and the initial first chip layer data. The first chip layer is the initial first chip layer that only retains the pattern located in the initial first chip target area.

10. The method for processing photomask layout data according to claim 9, wherein: The pattern of the initial first chip layer is located in the initial first chip target area and the initial first chip dummy area, and the step of obtaining the first chip layer data based on the third shielding layer data and the initial first chip layer data includes: The third shielding area is used to remove the pattern located in the initial first chip dummy area to obtain the first chip layer data.

11. The method for processing photomask layout data according to claim 8, wherein: Providing the second chip layer data includes: Providing initial second chip layer data, the initial second chip layer data being used to define an initial second chip layer, the initial second chip layer including an initial second chip dummy area and an initial second chip target area directly opposite the second subarea, a pattern of the initial second chip layer being located in the initial second chip target area and the initial second chip dummy area, or only in the initial second chip target area; Providing fourth shielding layer data, wherein the fourth shielding layer data is used to define a fourth shielding layer, wherein the fourth shielding layer has a fourth shielding area directly opposite to the initial second chip dummy area; The second chip layer data is obtained based on the fourth shielding layer data and the initial second chip layer data. The second chip layer is the initial second chip layer that only retains the pattern located in the initial second chip target area.

12. The method for processing photomask layout data according to claim 11, wherein: The pattern of the initial second chip layer is located in the initial second chip target area and the initial second chip dummy area, and the step of obtaining the second chip layer data based on the fourth shielding layer data and the initial second chip layer data includes: The fourth shielding area is used to remove the pattern located in the initial second chip dummy area to obtain the second chip layer data.

13. The method for processing photomask layout data according to any one of claims 1 to 12, wherein: The step of obtaining the layout layer data based on the framework layer data and the chip layer data includes: The framework layer data and the chip layer data are merged to obtain the layout layer data.

14. The method for processing photomask layout data according to any one of claims 1 to 3 and 6 to 12, wherein: The frame dummy area also includes a second area located outside the frame target area. The step of obtaining the layout layer data based on the frame layer data and the chip layer data includes: Providing fifth occlusion layer data, wherein the fifth occlusion layer data is used to define a fifth occlusion layer, wherein the fifth occlusion layer has a fifth occlusion area directly opposite to the second area; The layout layer data is obtained based on the fifth shielding layer data, the framework layer data and the chip layer data.

15. The method for processing photomask layout data according to any one of claims 4 to 5, characterized in that: The step of obtaining the layout layer data based on the framework layer data and the chip layer data includes: Providing fifth occlusion layer data, wherein the fifth occlusion layer data is used to define a fifth occlusion layer, wherein the fifth occlusion layer has a fifth occlusion area directly opposite to the second area; The layout layer data is obtained based on the fifth shielding layer data, the framework layer data and the chip layer data.

16. The method for processing photomask layout data according to claim 14 or 15, characterized in that: Obtaining the layout layer data based on the fifth shielding layer data, the framework layer data, and the chip layer data includes: The framework layer data and the chip layer data are merged and then inverted to obtain initial layout layer data, wherein the initial layout layer data is used to define an initial layout layer, the initial layout layer including an initial layout target area and an initial layout dummy area directly opposite to the second area, and a pattern of the initial layout layer is located in the initial layout target area and the initial layout dummy area, or only in the initial layout target area; The layout layer data is obtained based on the fifth shielding layer data and the initial layout layer data, and the layout layer is the initial layout layer that only retains the pattern located in the initial layout target area.

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