Chip clock system and method of operation thereof

Abstract

The application discloses a chip clock system and a running method thereof, and provides a more comprehensive clock safety system, which can identify whether HSE clock, LSE clock, HSI clock, LSI clock and PLL clock are faulty in real time, and adopts a standby high-speed clock to generate a corresponding standby clock through frequency division to replace the faulty clock when the clock is faulty; the clock system only needs one standby high-speed clock to generate a PLL standby clock, a HSI standby clock and a LSI standby clock, and the clock system, together with original HSECSS function and LSECSS function, can provide a more stable clock signal for a chip, and ensures completion of chip function test and verification.

Description

Technical Field

[0001] This invention belongs to the field of chip technology, specifically relating to a chip clock system and its operation method. Background Technology

[0002] The clock is the heart of a chip. The stability and reliability of the clock are the foundation for the stable operation of the chip. In particular, current digital chips are based on register-level circuit design (RTL). Almost all the functional signals of digital modules are transmitted from the registers one clock cycle at a time. Whether the final function of the circuit can be realized and whether the performance meets the design requirements depends to a large extent on the clock system.

[0003] Current MCU chips or large-scale SOC designs integrate more and more on-chip peripherals, such as storage interfaces like QSPI / SDIO, serial transmission interfaces like UART / I2C, and personalized communication interfaces like CAN / CAN FD / I2S for control or voice. The communication speeds of these interfaces are not the same; therefore, different clock sources are needed on the chip to provide a complete and reasonable clock network.

[0004] Commonly used MCU / SOC chips have the following clock sources: (1) LSI clock (i.e., low-speed internal clock), which uses an RC oscillator with a frequency of about 20KHz~60KHz, for use by independent watchdog and automatic wake-up units. (2) LSE clock (i.e., low-speed external clock), which uses a quartz crystal with an internal oscillator with a frequency of 32.768KHz, mainly used as the clock source for RTC. (3) HSE clock (i.e., high-speed external clock), which uses a quartz / ceramic resonator with an internal oscillator with a frequency range of 4MHz~16MHz, can be directly used as the system clock or PLL input. (4) HSI clock (i.e., high-speed internal clock), which uses an RC oscillator with a frequency of 8M / 16M / 32MHz, can be directly used as the system clock or as a PLL input. (5) PLL clock (i.e., phase-locked loop frequency multiplier clock), there are generally two PLLs: a main PLL and a dedicated PLL. The main PLL is provided with a clock signal by HSE or HSI and has two different output clocks: one for generating a high-speed system clock and the other for generating the clock for USB OTG FS, the clock for the random number generator, and the clock for SDIO. The dedicated PLL (i.e., PLLI2S) is used to generate a precise clock, thereby achieving high-quality audio performance in the I2S interface.

[0005] In actual chip return testing or during use, many functional failures are found to be due to clock loss or abnormalities, which in turn cause significant damage to the circuit.

[0006] like Figure 1As shown, the existing chip clock system includes LSE clock 1, HSE clock 2, LSI clock 3, HSI clock 4, first selector 5, second selector 6, third selector 7, fourth selector 8, PLL clock 9, and a clock module register. The output of LSI clock 3 directly outputs the low-speed clock signal lsi_clk; the output of LSE clock 1 is connected to the first input of first selector 5, the second input of first selector 5 is connected to the output of LSI clock 3, the selection terminal of first selector 5 inputs the low-speed clock switching enable signal LSECSSON, and the output of first selector 5 outputs the low-speed clock signal lse_clk; the output of HSI clock 4 directly outputs the high-speed clock signal hsi_clk; the output of HSE clock 2 is connected to the first input of second selector 6, the second input of second selector 6 is connected to the output of HSI clock 4, and the selection terminal of second selector 6 inputs the low-speed clock switching enable signal LSECSSON. The high-speed clock switching enable signal HSECSSON is input. The output of the second selector 6 is connected to the first input of the third selector 7 and the first input of the fourth selector 8, and outputs the high-speed clock signal hse_clk. The second input of the third selector 7 is connected to the output of the HSI clock 4. The selection terminal of the third selector 7 inputs the frequency multiplication selection signal pll_src. The output of the third selector 7 is connected to the input of the PLL clock 9. The output of the PLL clock 9 is connected to the second input of the fourth selector 8. The third input of the fourth selector 8 is connected to the output of the HSI clock 4. The output of the fourth selector 8 outputs the system clock signal sys_clk.

[0007] The aforementioned chip clock system incorporates a clock safety system (CSS), including CSS on the LSE clock and CSS on the HSE clock. The adoption of LSECSS and HSECSS addresses LSE and HSE clock failures. In the event of an LSE or HSE clock failure, the low-speed clock switching enable signal LSECSSON is set high, and / or the high-speed clock switching enable signal HSECSSON is set high, switching between the LSI clock and / or the HSI clock. However, the coverage of this clock safety system is relatively limited. If the HSI or LSI clock experiences frequency calibration failure due to process deviations, or if the frequency cannot be fine-tuned to the target value due to voltage or temperature variations, this clock safety system will be unable to resolve such issues, leading to device malfunction. The impact of process errors during the MPW (Multi-Project Wafer) stage on device performance is particularly significant, and the impact on chip testing and verification is even more severe. Summary of the Invention

[0008] The purpose of this invention is to provide a chip clock system and its operation method to provide a more stable clock signal.

[0009] The chip clock system of this invention includes an LSE clock, an HSE clock, an LSI clock, an HSI clock, a first selector, a second selector, a third selector, a fourth selector, a PLL clock, and a clock module register. The output of the LSE clock is connected to the first input of the first selector. The first selector's selection terminal receives a low-speed clock switching enable signal LSECSSON, and its output terminal outputs a low-speed clock signal lse_clk. The output of the HSE clock is connected to the first input of the second selector. The second selector's selection terminal receives a high-speed clock switching enable signal HSECSSON. The second selector's output terminal is connected to the first inputs of the third and fourth selectors and outputs a high-speed clock signal hse_clk. The third selector's selection terminal receives a frequency multiplication selection signal. The third selector's output terminal is connected to the input of the PLL clock. The PLL clock's output terminal is connected to the second input of the fourth selector, and the fourth selector's output terminal outputs the system clock signal sys_clk.

[0010] The chip's clock system also includes a backup high-speed clock, a backup clock register, a fifth selector, a sixth selector, an HSI clock detection divider, a PLL clock detection divider, and a counter, an HSI backup clock divider, and an LSI backup clock divider connected to the output of the backup high-speed clock. The counter outputs a backup clock ready signal lclk_rdy. The LSI clock output is connected to the first input of the fifth selector and outputs an LSI clock detection signal lsi_wdg_clk. The second input of the fifth selector is connected to the output of the LSI backup clock divider. The selection terminal of the fifth selector receives the LSI backup clock enable signal lsi_bk_on. The output of the fifth selector is connected to the second input of the first selector and outputs a low-speed clock signal lsi_clk. The first input of the sixth selector is connected to the output of the HSI clock. The second input of the selector is connected to the output of the HSI backup clock divider. The selection terminal of the sixth selector receives the HSI backup clock enable signal hsi_bk_on. The output of the sixth selector is connected to the second input of the second selector, the second input of the third selector, and the third input of the fourth selector, and outputs the high-speed clock signal hsi_clk. The input of the HSI clock detection divider is connected to the output of the HSI clock, and the output of the HSI clock detection divider outputs the HSI clock detection signal hsi_wdg_clk. The input of the PLL clock detection divider is connected to the output of the PLL clock, and the output of the PLL clock detection divider outputs the PLL clock detection signal pll_wdg_clk. The fourth input of the fourth selector is connected to the output of the backup high-speed clock, and the selection terminal of the fourth selector receives the PLL backup clock enable signal pll_bk_on.

[0011] Preferably, the HSI clock detection divider includes a first-stage HSI clock detection divider and a second-stage HSI clock detection divider. The input of the first-stage HSI clock detection divider is connected to the output of the HSI clock, the output of the first-stage HSI clock detection divider is connected to the input of the second-stage HSI clock detection divider, and the output of the second-stage HSI clock detection divider outputs the HSI clock detection signal hsi_wdg_clk.

[0012] Preferably, the PLL clock detection divider includes a first-stage PLL clock detection divider and a second-stage PLL clock detection divider. The input of the first-stage PLL clock detection divider is connected to the output of the PLL clock, the output of the first-stage PLL clock detection divider is connected to the input of the second-stage PLL clock detection divider, and the output of the second-stage PLL clock detection divider outputs the PLL clock detection signal pll_wdg_clk.

[0013] Preferably, the LSI backup clock divider includes a first-stage LSI backup clock divider and a second-stage LSI backup clock divider. The input of the first-stage LSI backup clock divider is connected to the output of the backup high-speed clock. The output of the first-stage LSI backup clock divider is connected to the input of the second-stage LSI backup clock divider. The output of the second-stage LSI backup clock divider is connected to the second input of the fifth selector.

[0014] Preferably, the backup high-speed clock includes a passive crystal oscillator, a backup clock internal oscillator, and two IO pad modules. The two ends of the passive crystal oscillator are respectively connected to the two input terminals of the backup clock internal oscillator through the two IO pad modules. The output terminal of the backup clock internal oscillator is connected to the input terminal of a counter, the input terminal of an HSI backup clock divider, the input terminal of an LSI backup clock divider, and the fourth input terminal of a fourth selector.

[0015] Preferably, the backup high-speed clock includes an active crystal oscillator and an IO pad module. The output of the active crystal oscillator is connected to the input of a counter, the input of an HSI backup clock divider, the input of an LSI backup clock divider, and the fourth input of a fourth selector through the IO pad module.

[0016] The operating method of the chip clock system described in this invention is used in the aforementioned chip clock system, and the operating method is as follows:

[0017] When the system powers on, the backup high-speed clock is started by default, and the clock signal output by the backup high-speed clock is used as the system clock. After the backup high-speed clock is ready (when the kernel reads LCLKRDYF as 1, that is, when lclk_rdy equals 1, the system can run under the LCLK clock), the kernel configures the clock module register and the backup clock register, and initializes and checks whether each clock has a fault (that is, whether it can start and run normally).

[0018] If some clocks fail (i.e. cannot start or run normally), a backup clock strategy is used.

[0019] If all clocks are functioning correctly (i.e., all can start and run normally), the backup high-speed clock is discontinued, and the LSE clock, HSE clock, LSI clock, HSI clock, and PLL clock are switched to be used. During the operation of the clock system, each clock is monitored in real time for failure. If some clocks fail, the backup clock strategy is used.

[0020] Specifically, if some clocks fail, the backup clock strategy is implemented as follows:

[0021] If the LSE clock fails but the LSI clock is normal, the kernel configures the clock module register to set the low-speed clock switching enable signal LSECSSON to a high level, stopping the use of the LSE clock and switching to the use of the LSI clock.

[0022] If both the LSE clock and LSI clock fail, the kernel configures the clock module register and the backup clock register, sets the low-speed clock switching enable signal LSECSSON to high, sets the LSI backup clock enable signal lsi_bk_on to high, stops using the LSE clock and LSI clock, and switches to using the LSI backup clock (obtained by dividing the backup high-speed clock).

[0023] If the HSE clock fails but the HSI clock is normal, the kernel configures the clock module register to set the high-speed clock switching enable signal HSECSSON to a high level, stopping the use of the HSE clock and switching to the use of the HSI clock.

[0024] If both the HSE clock and the HSI clock fail, the kernel configures the clock module register and the backup clock register, sets the high-speed clock switching enable signal HSECSSON to a high level, sets the HSI backup clock enable signal hsi_bk_on to a high level, stops using the HSE clock and the HSI clock, and switches to using the HSI backup clock (obtained by dividing the backup high-speed clock).

[0025] If the LSI clock and / or HSI clock and / or PLL clock fail, the kernel configures the backup clock register, setting the LSI backup clock enable signal lsi_bk_on to high and / or the HSI backup clock enable signal hsi_bk_on to high and / or the PLL backup clock enable signal pll_bk_on to high, stopping the use of the LSI clock and / or HSI clock and / or PLL clock, and switching to the use of the LSI backup clock and / or HSI backup clock and / or the PLL backup clock (provided by the backup high-speed clock) (derived from a frequency division of the backup high-speed clock).

[0026] Preferably, the method for real-time detection of LSI clock failure during clock system operation is as follows: the kernel configures a backup clock register, generates an LSI clock detection signal lsi_wdg_clk for software dog feeding, and periodically reads the value of the clock module register. Then, it determines whether the dog feeding is normal and whether the count range of the decrementing counter is within the normal range. If so, it indicates that the LSI clock is normal; otherwise, it indicates that the LSI clock has failed.

[0027] Preferably, the method for real-time detection of HSI clock failure during clock system operation is as follows: the kernel configures a backup clock register, generates an HSI clock detection signal hsi_wdg_clk for software dog feeding, and periodically reads the value of the clock module register. Then, it determines whether the dog feeding is normal and whether the count range of the decrementing counter is within the normal range. If so, it indicates that the HSI clock is normal; otherwise, it indicates that the HSI clock has failed.

[0028] Preferably, the method for real-time detection of whether the PLL clock is faulty during the operation of the clock system is as follows: the kernel configures a backup clock register, generates a PLL clock detection signal pll_wdg_clk for software dog feeding, and periodically reads the value of the clock module register. Then it determines whether the dog can be fed normally and whether the count range of the decrementing counter is within the normal range. If so, it means that the PLL clock is normal; otherwise, it means that the PLL clock is faulty.

[0029] This invention provides a more comprehensive clock security system that can identify faults in the HSE, LSE, HSI, LSI, and PLL clocks in real time. When a clock fails, a backup high-speed clock is used to generate a corresponding backup clock through frequency division for seamless switching to replace the faulty clock. It only requires one backup high-speed clock (LCLK) to generate a PLL backup clock (PLL_BK), and the backup high-speed clock (LCLK) can generate HSI backup clocks (HSI_BK) and LSI backup clocks (LSI_BK) through frequency division. Together with the existing HSECSS and LSECSS functions, this provides a more stable clock signal for the chip, ensuring the completion of chip functional testing and verification, reducing technical bottlenecks caused by process errors or process limitations, and achieving the goals of cost reduction and shortened development cycle. Whether in the MPW testing and verification stage where there are process risks or process limitations in the RC and OSC oscillators of the HSI and LSI clocks and the PLL clock, or in emergency situations during actual use, the chip clock system of this invention can provide a stable clock signal. This invention achieves a more comprehensive, secure, and flexible clocking solution, and ensures that multiple clock sources are equipped with safe backup clocks, making the solution more universal and providing more comprehensive protection, especially for the early design and testing of chips. Attached Figure Description

[0030] Figure 1 This is a diagram of the existing chip clock system architecture.

[0031] Figure 2 This is a diagram of the chip clock system architecture in Example 1.

[0032] Figure 3 This is a schematic diagram of the spare clock register in Example 1.

[0033] Figure 4 This is a flowchart of the operation of the chip clock system in Example 1.

[0034] Figure 5 This is a flowchart illustrating the real-time detection of LSI clock malfunctions during the operation of the clock system in Example 1.

[0035] Figure 6 This is a flowchart illustrating the real-time detection of whether the HSI clock malfunctions during the operation of the clock system in Example 1.

[0036] Figure 7 This is a flowchart illustrating the real-time detection of whether the PLL clock malfunctions during the operation of the clock system in Example 1.

[0037] Figure 8 This is a diagram of the chip clock system architecture in Example 2. Detailed Implementation

[0038] Example 1: As Figure 2 , Figure 3 As shown, the chip clock system in this embodiment includes LSE clock 1, HSE clock 2, LSI clock 3, HSI clock 4, first selector 5, second selector 6, third selector 7, fourth selector 8, PLL clock 9, clock module register, backup high-speed clock 10, backup clock register, fifth selector 11, sixth selector 12, HSI clock detection divider, PLL clock detection divider, counter 13, HSI backup clock divider 14, and LSI backup clock divider. The HSI clock detection divider includes HSI clock detection first-stage divider 15 and HSI clock detection second-stage divider 16. The PLL clock detection divider includes PLL clock detection first-stage divider 17 and PLL clock detection second-stage divider 18. The LSI backup clock divider includes LSI backup clock first-stage divider 19 and LSI backup clock second-stage divider 20. The backup high-speed clock 10 includes a passive crystal oscillator 21 (48 MHz, covering the backup requirements of LSE, LSI, and PLL clocks), an internal backup clock oscillator 22, and two IO pad modules. The two ends of the passive crystal oscillator 21 are connected to the two inputs of the internal backup clock oscillator 22 via the two IO pad modules. The output of the internal backup clock oscillator 22 is connected to the inputs of a counter 13, an HSI backup clock divider 14, and an LSI backup clock first-stage divider 19. The output of the counter 13 outputs a backup clock ready signal lclk_rdy. Since the passive crystal oscillator 21 requires a certain amount of time to start oscillating, the backup high-speed clock signal is delayed by the counter 13 until it stabilizes, generating the backup clock ready signal lclk_rdy. The lclk signal following lclk_rdy provides a stable clock for the system. The output of the LSI backup clock first-stage divider 19 is connected to the input of the LSI backup clock second-stage divider 20.

[0039] The output of LSI clock 3 is connected to the first input of the fifth selector 11 and outputs the LSI clock detection signal lsi_wdg_clk. The second input of the fifth selector 11 is connected to the output of the second-stage frequency divider 20 of the LSI backup clock. The selection terminal of the fifth selector 11 inputs the LSI backup clock enable signal lsi_bk_on, and the output of the fifth selector 11 outputs the low-speed clock signal lsi_clk.

[0040] The output of HSI clock 4 is connected to the first input of the sixth selector 12. The second input of the sixth selector 12 is connected to the output of the HSI standby clock divider 14. The selection terminal of the sixth selector 12 receives the HSI standby clock enable signal hsi_bk_on, and the output of the sixth selector 12 outputs the high-speed clock signal hsi_clk.

[0041] The output of LSE clock 1 is connected to the first input of the first selector 5. The second input of the first selector 5 is connected to the output of the fifth selector 11. The selection terminal of the first selector 5 receives the low-speed clock switching enable signal LSECSSON, and the output of the first selector 5 outputs the low-speed clock signal lse_clk.

[0042] The output of HSE clock 2 is connected to the first input of the second selector 6. The second input of the second selector 6 is connected to the output of the sixth selector 12. The selection terminal of the second selector 6 receives the high-speed clock switching enable signal HSECSSON. The output of the second selector 6 is connected to the first input of the third selector 7 and the first input of the fourth selector 8, and outputs the high-speed clock signal hse_clk. The second input of the third selector 7 is connected to the output of the sixth selector 12. The selection terminal of the third selector 7 receives the frequency multiplication selection signal pll_src. The output of the third selector 7 is connected to the input of PLL clock 9. The output of PLL clock 9 is connected to the second input of the fourth selector 8. The third input of the fourth selector 8 is connected to the output of the sixth selector 12. The fourth input of the fourth selector 8 is connected to the output of the backup clock internal oscillator 22. The selection terminal of the fourth selector 8 receives the PLL backup clock enable signal pll_bk_on. The output of the fourth selector 8 outputs the system clock signal sys_clk.

[0043] The input of the first-stage frequency divider 15 of the HSI clock detection is connected to the output of the HSI clock 4. The output of the first-stage frequency divider 15 of the HSI clock detection is connected to the input of the second-stage frequency divider 16 of the HSI clock detection. The output of the second-stage frequency divider 16 of the HSI clock detection outputs the HSI clock detection signal hsi_wdg_clk.

[0044] The input terminal of the first-stage frequency divider 17 of the PLL clock detection is connected to the output terminal of the PLL clock 9. The output terminal of the first-stage frequency divider 17 of the PLL clock detection is connected to the input terminal of the second-stage frequency divider 18 of the PLL clock detection. The output terminal of the second-stage frequency divider 18 of the PLL clock detection outputs the PLL clock detection signal pll_wdg_clk.

[0045] like Figure 3As shown, the kernel can read and write the backup clock register via the bus. The backup clock register contains information on whether to enable the backup high-speed clock (LCLK) as the backup clock for HSI / LSI / PLL, as well as the corresponding division factor. The configurable parameters and bit widths of the backup clock register are as follows:

[0046] Bit0 LCLKRDYF LCLK (i.e., the standby high-speed clock) is set to 1 by hardware and cleared by software via the LCLKRDYC bit.

[0047] 0: LCLK not ready;

[0048] 1: LCLK is ready.

[0049] Bit1 LCLKRDYIE LCLK Enables ready interrupt.

[0050] 0: No interrupt is generated after LCLK is ready;

[0051] 1: An interrupt is generated after LCLK is ready.

[0052] Bit2 LCLKRDYC LCLK Ready Flag Clear Bit.

[0053] 0: Do not clear the LCLKRDYF flag;

[0054] 1: Clear the LCLKRDYF flag.

[0055] Bit3 Reserved.

[0056] Bit4 HSI_BK_ON enables the HSI backup clock, which is generated by LCLK.

[0057] 0: LCLK generation of HSI backup clock is not enabled;

[0058] 1: Enable LCLK to generate HSI backup clock.

[0059] Bit7:5 HSI_DIV_BY_LCLK[2:0] HSI spare clock division factor.

[0060] 000: The frequency of the clock signal lclk is used as the frequency of the clock signal hsi_bk_clk;

[0061] 001: Half the frequency of the clock signal lclk is used as the frequency of the clock signal hsi_bk_clk;

[0062] 010: 1 / 4 of the frequency of the clock signal lclk is used as the frequency of the clock signal hsi_bk_clk;

[0063] 011: 1 / 6 of the frequency of the clock signal lclk is used as the frequency of the clock signal hsi_bk_clk;

[0064] 100: 1 / 8 of the frequency of the clock signal lclk is used as the frequency of the clock signal hsi_bk_clk;

[0065] 101: 1 / 10 of the frequency of the clock signal lclk is used as the frequency of the clock signal hsi_bk_clk;

[0066] 110: 1 / 12 of the frequency of the clock signal lclk is used as the frequency of the clock signal hsi_bk_clk.

[0067] Bit8 LSI_BK_ON enables the LSI backup clock, which is generated by LCLK.

[0068] 0: LCLK generation of LSI backup clock is not enabled;

[0069] 1: Enable LCLK to generate an LSI backup clock.

[0070] Bit11:9 LSI_DIV1_BY_LCLK[2:0] LSI spare clock division factor (the first-level division factor).

[0071] 000: Half the frequency of the clock signal lclk is used as the frequency of the clock signal lsi_div1_by_lclk;

[0072] 001: One-quarter of the frequency of the clock signal lclk is used as the frequency of the clock signal lsi_div1_by_lclk;

[0073] 010: 1 / 8 of the frequency of the clock signal lclk is used as the frequency of the clock signal lsi_div1_by_lclk;

[0074] 011: 1 / 16 of the frequency of the clock signal lclk is used as the frequency of the clock signal lsi_div1_by_lclk;

[0075] 100: 1 / 32 of the frequency of the clock signal lclk is used as the frequency of the clock signal lsi_div1_by_lclk;

[0076] 101: 1 / 64 of the frequency of the clock signal lclk is used as the frequency of the clock signal lsi_div1_by_lclk;

[0077] 110: 1 / 128 of the frequency of the clock signal lclk is used as the frequency of the clock signal lsi_div1_by_lclk;

[0078] 111: 1 / 256 of the frequency of the clock signal lclk is used as the frequency of the clock signal lsi_div1_by_lclk.

[0079] Bit15:12 LSI_DIV2_BY_LCLK[3:0] LSI spare clock division factor (the second-level division factor).

[0080] 0000: The frequency of the clock signal lsi_div1_by_lclk is used as the frequency of the clock signal lsi_bk_clk;

[0081] 0001: Half the frequency of the clock signal lsi_div1_by_lclk is used as the frequency of the clock signal lsi_bk_clk;

[0082] 0010: 1 / 4 of the frequency of the clock signal lsi_div1_by_lclk is used as the frequency of the clock signal lsi_bk_clk;

[0083] 0011: 1 / 6 of the frequency of the clock signal lsi_div1_by_lclk is used as the frequency of the clock signal lsi_bk_clk;

[0084] 0100: 1 / 8 of the frequency of the clock signal lsi_div1_by_lclk is used as the frequency of the clock signal lsi_bk_clk;

[0085] 0101: 1 / 10 of the frequency of the clock signal lsi_div1_by_lclk is used as the frequency of the clock signal lsi_bk_clk;

[0086] 0110: 1 / 12 of the frequency of the clock signal lsi_div1_by_lclk is used as the frequency of the clock signal lsi_bk_clk;

[0087] 0111: 1 / 14 of the frequency of the clock signal lsi_div1_by_lclk is used as the frequency of the clock signal lsi_bk_clk;

[0088] 1000: 1 / 16 of the frequency of the clock signal lsi_div1_by_lclk is used as the frequency of the clock signal lsi_bk_clk;

[0089] 1001: 1 / 18 of the frequency of the clock signal lsi_div1_by_lclk is used as the frequency of the clock signal lsi_bk_clk;

[0090] 1010: 1 / 20 of the frequency of the clock signal lsi_div1_by_lclk is used as the frequency of the clock signal lsi_bk_clk;

[0091] 1011: 1 / 22 of the frequency of the clock signal lsi_div1_by_lclk is used as the frequency of the clock signal lsi_bk_clk;

[0092] 1100: 1 / 24 of the frequency of the clock signal lsi_div1_by_lclk is used as the frequency of the clock signal lsi_bk_clk;

[0093] 1101: 1 / 26 of the frequency of the clock signal lsi_div1_by_lclk is used as the frequency of the clock signal lsi_bk_clk;

[0094] 1110: 1 / 28 of the frequency of the clock signal lsi_div1_by_lclk is used as the frequency of the clock signal lsi_bk_clk;

[0095] 1111: 1 / 30 of the frequency of the clock signal lsi_div1_by_lclk is used as the frequency of the clock signal lsi_bk_clk.

[0096] Bit16 PLL_BK_ON enables the PLL backup clock, which is generated by LCLK.

[0097] 0: LCLK is not enabled to generate a PLL backup clock;

[0098] 1: Enable LCLK to generate a PLL backup clock.

[0099] Bit19:17 PLL_DIV1_WDG[2:0] PLL clock detection frequency division coefficient (the first-level frequency division coefficient).

[0100] 000: Half the frequency of the clock signal pll_clk is used as the frequency of the clock signal pll_div1_wdg;

[0101] 001: One-quarter of the frequency of the clock signal pll_clk is used as the frequency of the clock signal pll_div1_wdg;

[0102] 010: 1 / 8 of the frequency of the clock signal pll_clk is used as the frequency of the clock signal pll_div1_wdg;

[0103] 011: 1 / 16 of the frequency of the clock signal pll_clk is used as the frequency of the clock signal pll_div1_wdg;

[0104] 100: 1 / 32 of the frequency of the clock signal pll_clk is used as the frequency of the clock signal pll_div1_wdg;

[0105] 101: 1 / 64 of the frequency of the clock signal pll_clk is used as the frequency of the clock signal pll_div1_wdg;

[0106] 110: 1 / 128 of the frequency of the clock signal pll_clk is used as the frequency of the clock signal pll_div1_wdg;

[0107] 111: 1 / 256 of the frequency of the clock signal pll_clk is used as the frequency of the clock signal pll_div1_wdg.

[0108] Bit23:20 PLL_DIV2_WDG[3:0] PLL clock detection frequency division coefficient (the second-level frequency division coefficient);

[0109] 0000: The frequency of the clock signal pll_div1_wdg is used as the frequency of the PLL clock detection signal pll_wdg_clk;

[0110] 0001: Half the frequency of the clock signal pll_div1_wdg is used as the frequency of the PLL clock detection signal pll_wdg_clk; 0010: One-quarter of the frequency of the clock signal pll_div1_wdg is used as the frequency of the PLL clock detection signal pll_wdg_clk;

[0111] 0011: 1 / 6 of the frequency of the clock signal pll_div1_wdg is used as the frequency of the PLL clock detection signal pll_wdg_clk; 0100: 1 / 8 of the frequency of the clock signal pll_div1_wdg is used as the frequency of the PLL clock detection signal pll_wdg_clk; 0101: 1 / 10 of the frequency of the clock signal pll_div1_wdg is used as the frequency of the PLL clock detection signal pll_wdg_clk;

[0112] 0110: 1 / 12 of the frequency of the clock signal pll_div1_wdg is used as the frequency of the PLL clock detection signal pll_wdg_clk;

[0113] 0111: 1 / 14 of the frequency of the clock signal pll_div1_wdg is used as the frequency of the PLL clock detection signal pll_wdg_clk; 1000: 1 / 16 of the frequency of the clock signal pll_div1_wdg is used as the frequency of the PLL clock detection signal pll_wdg_clk;

[0114] 1001: 1 / 18 of the frequency of the clock signal pll_div1_wdg is used as the frequency of the PLL clock detection signal pll_wdg_clk;

[0115] 1010: 1 / 20 of the frequency of the clock signal pll_div1_wdg is used as the frequency of the PLL clock detection signal pll_wdg_clk;

[0116] 1011: 1 / 22 of the frequency of the clock signal pll_div1_wdg is used as the frequency of the PLL clock detection signal pll_wdg_clk;

[0117] 1100: 1 / 24 of the frequency of the clock signal pll_div1_wdg is used as the frequency of the PLL clock detection signal pll_wdg_clk;

[0118] 1101: 1 / 26 of the frequency of the clock signal pll_div1_wdg is used as the frequency of the PLL clock detection signal pll_wdg_clk;

[0119] 1110: 1 / 28 of the frequency of the clock signal pll_div1_wdg is used as the frequency of the PLL clock detection signal pll_wdg_clk;

[0120] 1111: 1 / 30 of the frequency of the clock signal pll_div1_wdg is used as the frequency of the PLL clock detection signal pll_wdg_clk.

[0121] Bit24 Reserved.

[0122] Bit27:25 HSI_DIV1_WDG[2:0] HSI clock detection division factor (first-level division factor).

[0123] 000: Half the frequency of the HSI clock signal is used as the frequency of the clock signal hsi_div1_wdg;

[0124] 001: 1 / 4 of the frequency of the HSI clock signal is used as the frequency of the clock signal hsi_div1_wdg;

[0125] 010: 1 / 8 of the frequency of the HSI clock signal is used as the frequency of the clock signal hsi_div1_wdg;

[0126] 011: 1 / 16 of the frequency of the HSI clock signal is used as the frequency of the clock signal hsi_div1_wdg;

[0127] 100: 1 / 32 of the frequency of the HSI clock signal is used as the frequency of the clock signal hsi_div1_wdg;

[0128] 101: 1 / 64 of the frequency of the HSI clock signal is used as the frequency of the clock signal hsi_div1_wdg;

[0129] 110: 1 / 128 of the frequency of the HSI clock signal is used as the frequency of the clock signal hsi_div1_wdg;

[0130] 111: 1 / 256 of the frequency of the HSI clock signal is used as the frequency of the clock signal hsi_div1_wdg.

[0131] Bit31:28 HSI_DIV2_WDG[3:0] HSI clock detection division factor (the second-level division factor).

[0132] 0000: The frequency of the clock signal hsi_div1_wdg is used as the frequency of the HSI clock detection signal hsi_wdg_clk;

[0133] 0001: Half the frequency of the clock signal hsi_div1_wdg is used as the frequency of the HSI clock detection signal hsi_wdg_clk;

[0134] 0010: 1 / 4 of the frequency of the clock signal hsi_div1_wdg is used as the frequency of the HSI clock detection signal hsi_wdg_clk;

[0135] 0011: 1 / 6 of the frequency of the clock signal hsi_div1_wdg is used as the frequency of the HSI clock detection signal hsi_wdg_clk;

[0136] 0100: 1 / 8 of the frequency of the clock signal hsi_div1_wdg is used as the frequency of the HSI clock detection signal hsi_wdg_clk;

[0137] 0101: 1 / 10 of the frequency of the clock signal hsi_div1_wdg is used as the frequency of the HSI clock detection signal hsi_wdg_clk;

[0138] 0110: 1 / 12 of the frequency of the clock signal hsi_div1_wdg is used as the frequency of the HSI clock detection signal hsi_wdg_clk;

[0139] 0111: 1 / 14 of the frequency of the clock signal hsi_div1_wdg is used as the frequency of the HSI clock detection signal hsi_wdg_clk;

[0140] 1000: 1 / 16 of the frequency of the clock signal hsi_div1_wdg is used as the frequency of the HSI clock detection signal hsi_wdg_clk;

[0141] 1001: 1 / 18 of the frequency of the clock signal hsi_div1_wdg is used as the frequency of the HSI clock detection signal hsi_wdg_clk;

[0142] 1010: 1 / 20 of the frequency of the clock signal hsi_div1_wdg is used as the frequency of the HSI clock detection signal hsi_wdg_clk;

[0143] 1011: 1 / 22 of the frequency of the clock signal hsi_div1_wdg is used as the frequency of the HSI clock detection signal hsi_wdg_clk;

[0144] 1100: 1 / 24 of the frequency of the clock signal hsi_div1_wdg is used as the frequency of the HSI clock detection signal hsi_wdg_clk;

[0145] 1101: 1 / 26 of the frequency of the clock signal hsi_div1_wdg is used as the frequency of the HSI clock detection signal hsi_wdg_clk;

[0146] 1110: 1 / 28 of the frequency of the clock signal hsi_div1_wdg is used as the frequency of the HSI clock detection signal hsi_wdg_clk;

[0147] 1111: 1 / 30 of the frequency of the clock signal hsi_div1_wdg is used as the frequency of the HSI clock detection signal hsi_wdg_clk.

[0148] like Figures 4 to 7 The operating method of the chip clock system shown is used in the aforementioned chip clock system, where the backup high-speed clock is functioning normally (no fault has occurred). Under the premise that the backup high-speed clock is functioning normally, the operating method of the chip clock system includes the following steps:

[0149] Step 1: Power on the system and start the backup high-speed clock by default. Use the clock signal output by the backup high-speed clock as the system clock, and then proceed to Step 2.

[0150] Step 2: Determine if the standby clock ready signal lclk_rdy is equal to 1. If it is, proceed to step 3; otherwise, continue with step 2.

[0151] Step 3: Configure the kernel clock module register and spare clock register, initialize and detect each clock, and then execute Step 4.

[0152] Step 4: Determine if any clocks are malfunctioning (i.e., unable to start or run normally, such as a clock not being ready or a clock frequency error not meeting the specification). If so, proceed to step 8; otherwise (i.e., if all clocks are functioning correctly), proceed to step 5.

[0153] Step 5: Stop using the backup high-speed clock, switch to LSE clock 1, HSE clock 2, LSI clock 3, HSI clock 4 and PLL clock 9, and then proceed to Step 6.

[0154] Step 6: Detect each clock in real time, and then proceed to Step 7.

[0155] The principle of real-time detection of various clocks is similar to that of a software watchdog.

[0156] like Figure 5 As shown, the methods for real-time detection of whether LSI clock 3 has malfunctioned include:

[0157] The first step is for the kernel to configure the standby clock register, generate the LSI clock detection signal lsi_wdg_clk for software dog feeding, and periodically read the value of the clock module register before executing the second step.

[0158] The second step is to determine whether the dog can be fed normally and whether the count range of the decrementing counter is within the normal range. If so, proceed to the third step; otherwise, proceed to the fourth step.

[0159] The third step is to determine that LSI clock 3 is normal, and then the process ends.

[0160] Step 4: Determine if LSI clock 3 is faulty, then end.

[0161] like Figure 6 As shown, the methods for real-time detection of whether HSI clock 4 has malfunctioned include:

[0162] The first step is to configure the backup clock register in the kernel, generate the HSI clock detection signal hsi_wdg_clk for software dog feeding, and periodically read the value of the clock module register before proceeding to the second step.

[0163] The second step is to determine whether the dog can be fed normally and whether the count of the decrementing counter is within the normal range. If so, proceed to the third step; otherwise, proceed to the fourth step.

[0164] The third step is to determine that HSI clock 4 is normal, and then the process ends.

[0165] Step 4: Determine that HSI clock 4 is faulty, and then end.

[0166] like Figure 7 As shown, the methods for real-time detection of whether PLL clock 9 is faulty include:

[0167] The first step is to configure the backup clock register in the kernel, generate the PLL clock detection signal pll_wdg_clk for software dog feeding, and periodically read the value of the clock module register before proceeding to the second step.

[0168] The second step is to determine whether the dog can be fed normally and whether the count range of the decrementing counter is within the normal range. If so, proceed to the third step; otherwise, proceed to the fourth step.

[0169] The third step is to determine that PLL clock 9 is normal, and then end the process.

[0170] Step 4: Determine if PLL clock 9 is faulty, then end the process.

[0171] In addition, the fault diagnosis method for the HSE clock is the same as that for the existing technology, and the fault diagnosis method for the LSE clock is the same as that for the existing technology.

[0172] Step 7: Determine if any clocks are faulty (e.g., clock frequency error does not meet the specification). If so, proceed to step 8; otherwise (i.e., if all clocks are not faulty), return to step 6.

[0173] Step 8: Use the backup clock strategy, then end. The specific method for using the backup clock strategy is as follows:

[0174] If LSE clock 1 fails while LSI clock 3 is normal, the kernel configures the clock module register to set the low-speed clock switching enable signal LSECSSON to high (i.e., set to 1), stopping the use of LSE clock 1 and switching to LSI clock 3.

[0175] If both LSE clock 1 and LSI clock 3 fail, the kernel configures the clock module register and the backup clock register, sets the low-speed clock switching enable signal LSECSSON to high level, sets the LSI backup clock enable signal lsi_bk_on to high level (i.e., sets it to 1), stops using LSE clock 1 and LSI clock 3, and switches to using the LSI backup clock (corresponding to the clock signal lsi_bk_clk) (obtained by dividing the backup high-speed clock).

[0176] If HSE clock 2 fails while HSI clock 4 is normal, the kernel configures the clock module register to set the high-speed clock switching enable signal HSECSSON to high (i.e., set to 1), stopping the use of HSE clock 2 and switching to HSI clock 4.

[0177] If both HSE clock 2 and HSI clock 4 fail, the kernel configures the clock module register and the backup clock register, sets the high-speed clock switching enable signal HSECSSON to high level, sets the HSI backup clock enable signal hsi_bk_on to high level (i.e., sets it to 1), stops using HSE clock 2 and HSI clock 4, and switches to using the HSI backup clock (corresponding to the clock signal hsi_bk_clk) (obtained by dividing the backup high-speed clock).

[0178] If LSI clock 3 fails, the kernel configures the backup clock register, sets the LSI backup clock enable signal lsi_bk_on to a high level, stops using LSI clock 3, and switches to the LSI backup clock (corresponding to the clock signal lsi_bk_clk) (obtained by dividing the backup high-speed clock).

[0179] If HSI clock 4 fails, the kernel configures the backup clock register, sets the HSI backup clock enable signal hsi_bk_on to a high level, stops using HSI clock 4, and switches to the HSI backup clock (corresponding to the clock signal hsi_bk_clk) (obtained by dividing the backup high-speed clock).

[0180] If PLL clock 9 fails, the kernel configures the backup clock register, sets the PLL backup clock enable signal pll_bk_on to a high level (i.e., set to 1), stops using PLL clock 9, and switches to the PLL backup clock (corresponding to the clock signal pll_bk_clk) (provided by the backup high-speed clock).

[0181] Example 2: The structure and operation method of the chip clock system in this example are mostly the same as those in Example 1. The only difference is that the backup high-speed clock 10 includes an active crystal oscillator and an IO pad module. The output of the active crystal oscillator is connected to the input of the counter 13, the input of the HSI backup clock divider 14, the input of the LSI backup clock first-stage divider 19, and the fourth input of the fourth selector 8 through the IO pad module.

Claims

1. A chip clock system, comprising an LSE clock (1), an HSE clock (2), an LSI clock (3), an HSI clock (4), a first selector (5), a second selector (6), a third selector (7), a fourth selector (8), a PLL clock (9), and a clock module register; the output of the LSE clock (1) is connected to the first input of the first selector (5), the first selector (5) receives a low-speed clock switching enable signal LSECSSON at its selection terminal and outputs a low-speed clock signal lse_clk at its output terminal; the output of the HSE clock (2) is connected to the second selector (6) at its first input terminal. One input terminal, the selection terminal of the second selector (6) inputs the high-speed clock switching enable signal HSECSSON, the output terminal of the second selector (6) is connected to the first input terminal of the third selector (7) and the first input terminal of the fourth selector (8), and outputs the high-speed clock signal hse_clk, the selection terminal of the third selector (7) inputs the frequency multiplication selection signal pll_src, the output terminal is connected to the input terminal of the PLL clock (9), the output terminal of the PLL clock (9) is connected to the second input terminal of the fourth selector (8), and the output terminal of the fourth selector (8) outputs the system clock signal sys_clk; characterized in that: It also includes a backup high-speed clock (10), a backup clock register, a fifth selector (11), a sixth selector (12), an HSI clock detection divider, a PLL clock detection divider, and a counter (13), an HSI backup clock divider (14), and an LSI backup clock divider connected to the output of the backup high-speed clock (10); the output of the counter (13) outputs the backup clock ready signal lclk_rdy; the output of the LSI clock (3) is connected to the first input of the fifth selector (11) and outputs the LSI clock detection signal lsi_wdg_clk; the second input of the fifth selector (11) is connected to the output of the LSI backup clock divider, the selector inputs the LSI backup clock enable signal lsi_bk_on; the output of the fifth selector (11) is connected to the second input of the first selector (5) and outputs the low-speed clock signal lsi_clk; the sixth selector (11)... 2) The first input terminal is connected to the output terminal of HSI clock (4), the second input terminal is connected to the output terminal of HSI backup clock divider (14), and the selection terminal is connected to the HSI backup clock enable signal hsi_bk_on. The output terminal of the sixth selector (12) is connected to the second input terminal of the second selector (6), the second input terminal of the third selector (7), and the third input terminal of the fourth selector (8), and outputs the high-speed clock signal hsi_clk. The input terminal of the HSI clock detection divider is connected to the output terminal of HSI clock (4), and the output terminal outputs the HSI clock detection signal hsi_wdg_clk. The input terminal of the PLL clock detection divider is connected to the output terminal of PLL clock (9), and the output terminal outputs the PLL clock detection signal pll_wdg_clk. The fourth input terminal of the fourth selector (8) is connected to the output terminal of the backup high-speed clock (10), and the selection terminal is connected to the PLL backup clock enable signal pll_bk_on.

2. The chip clock system according to claim 1, characterized in that: The HSI clock detection divider includes a first-stage HSI clock detection divider (15) and a second-stage HSI clock detection divider (16). The input of the first-stage HSI clock detection divider (15) is connected to the output of the HSI clock (4), and the output is connected to the input of the second-stage HSI clock detection divider (16). The output of the second-stage HSI clock detection divider (16) outputs the HSI clock detection signal hsi_wdg_clk.

3. The chip clock system according to claim 1, characterized in that: The PLL clock detection divider includes a first-stage PLL clock detection divider (17) and a second-stage PLL clock detection divider (18). The input of the first-stage PLL clock detection divider (17) is connected to the output of the PLL clock (9), and the output is connected to the input of the second-stage PLL clock detection divider (18). The output of the second-stage PLL clock detection divider (18) outputs the PLL clock detection signal pll_wdg_clk.

4. The chip clock system according to claim 1, characterized in that: The LSI backup clock divider includes an LSI backup clock first-stage divider (19) and an LSI backup clock second-stage divider (20). The input of the LSI backup clock first-stage divider (19) is connected to the output of the backup high-speed clock (10), and the output is connected to the input of the LSI backup clock second-stage divider (20). The output of the LSI backup clock second-stage divider (20) is connected to the second input of the fifth selector (11).

5. The chip clock system according to any one of claims 1 to 4, characterized in that: The backup high-speed clock (10) includes a passive crystal oscillator (21), a backup clock internal oscillator (22), and two IO pad modules. The two ends of the passive crystal oscillator (21) are connected to the two input terminals of the backup clock internal oscillator (22) through the two IO pad modules. The output terminal of the backup clock internal oscillator (22) is connected to the input terminal of the counter (13), the input terminal of the HSI backup clock divider (14), the input terminal of the LSI backup clock divider, and the fourth input terminal of the fourth selector (8).

6. The chip clock system according to any one of claims 1 to 4, characterized in that: The backup high-speed clock (10) includes an active crystal oscillator and an IO pad module. The output of the active crystal oscillator is connected to the input of the counter (13), the input of the HSI backup clock divider (14), the input of the LSI backup clock divider, and the fourth input of the fourth selector (8) through the IO pad module.

7. A method for operating a chip clock system, used in the chip clock system as described in any one of claims 1 to 6, wherein the method of operation is as follows: When the system powers on, the backup high-speed clock is started by default, and the clock signal output by the backup high-speed clock is used as the system clock. After the backup high-speed clock is ready, the kernel configures the clock module register and the backup clock register, and initializes and checks whether each clock has a fault. If some clocks fail, a backup clock strategy is used; If no clocks fail, the backup high-speed clock is stopped and the LSE clock (1), HSE clock (2), LSI clock (3), HSI clock (4) and PLL clock (9) are switched to be used. During the operation of the clock system, each clock is monitored in real time for failure. If some clocks fail, the backup clock strategy is used. Specifically, if some clocks fail, the backup clock strategy is implemented as follows: If the LSE clock (1) fails and the LSI clock (3) is normal, the kernel configures the clock module register to make the low-speed clock switching enable signal LSECSSON high, stops using the LSE clock (1), and switches to using the LSI clock (3). If both LSE clock (1) and LSI clock (3) fail, the kernel configures the clock module register and the backup clock register, sets the low-speed clock switching enable signal LSECSSON to a high level, sets the LSI backup clock enable signal lsi_bk_on to a high level, stops using LSE clock (1) and LSI clock (3), and switches to using the LSI backup clock. If the HSE clock (2) fails and the HSI clock (4) is normal, the kernel configures the clock module register to make the high-speed clock switching enable signal HSECSSON high, stops using the HSE clock (2), and switches to using the HSI clock (4). If both HSE clock (2) and HSI clock (4) fail, the kernel configures the clock module register and the backup clock register, sets the high-speed clock switching enable signal HSECSSON to a high level, sets the HSI backup clock enable signal hsi_bk_on to a high level, stops using HSE clock (2) and HSI clock (4), and switches to using the HSI backup clock. If the LSI clock (3) and / or HSI clock (4) and / or PLL clock (9) fails, the kernel configures the backup clock register to make the LSI backup clock enable signal lsi_bk_on high and / or the HSI backup clock enable signal hsi_bk_on high and / or the PLL backup clock enable signal pll_bk_on high, thereby stopping the use of the LSI clock (3) and / or HSI clock (4) and / or PLL clock (9) and switching to the use of the LSI backup clock and / or HSI backup clock and / or PLL backup clock.

8. The method for operating the chip clock system according to claim 7, characterized in that: The method for real-time detection of whether the LSI clock (3) has a fault during the operation of the clock system is as follows: the kernel configures the backup clock register, generates the LSI clock detection signal lsi_wdg_clk for software dog feeding, and periodically reads the value of the clock module register, and then judges whether the dog can be fed normally and the counting range of the decrementing counter is within the normal range. If so, it means that the LSI clock (3) is normal; otherwise, it means that the LSI clock (3) has a fault. The method for real-time detection of whether the HSI clock (4) has a fault during the operation of the clock system is as follows: the kernel configures the backup clock register, generates the HSI clock detection signal hsi_wdg_clk for software dog feeding, and periodically reads the value of the clock module register. Then it determines whether the dog can be fed normally and whether the counting range of the decrementing counter is within the normal range. If so, it means that the HSI clock (4) is normal; otherwise, it means that the HSI clock (4) has a fault. The method for real-time detection of whether the PLL clock (9) has malfunctioned during the operation of the clock system is as follows: the kernel configures the backup clock register, generates the PLL clock detection signal pll_wdg_clk for software dog feeding, and periodically reads the value of the clock module register. Then it determines whether the dog can be fed normally and whether the counting range of the decrementing counter is within the normal range. If so, it means that the PLL clock (9) is normal; otherwise, it means that the PLL clock (9) has malfunctioned.

Images