FPGA-based floating-point multiplier and calculation method
By designing floating-point multiply-accumulators on FPGAs and extending the multiplier layer and adder array, the problem of insufficient resource utilization in existing technologies is solved, and the speed of large-scale multiply-accumulator operations is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-10-18
- Publication Date
- 2026-03-20
AI Technical Summary
When existing multiply-accumulate operations are implemented on FPGAs, they are limited by the basic processing unit structure, which prevents the effective utilization of more on-chip resources, thus limiting the speed improvement of large-scale multiply-accumulate operations.
Design an FPGA-based floating-point multiply-accumulator, including a data allocation module, a floating-point multiplier layer, a floating-point adder array, and an accumulator. By extending the multiplier layer and adder array, more on-chip resources can be used to improve the computing speed.
By extending the multiplier layer and adder array, the upper limit of multiply-accumulate operation speed on the FPGA is increased, achieving more efficient computing performance.
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Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of computer hardware structure and circuit design, and relates to an infinitely extended floating point multiplier-adder and a floating point multiplication and addition calculation method, in particular to a floating point multiplier-adder and a calculation method based on FPGA. BACKGROUND
[0002] The multiplication and addition operation is a basic operation in scientific calculation and has been widely applied in various machine learning algorithms such as deep convolutional neural network and matrix multiplication operation. The existing multiplication and addition operation is generally realized by CPU processor, but is limited by CPU operation logic, and a large-scale multiplication and addition operation will occupy a large amount of time, which cannot meet the current operation demand.
[0003] In recent years, the FPGA technology has developed rapidly, and due to the great increase of available logic gates, on-chip available registers and other resources, its function has changed from simple logic replacement to complex intensive calculation processing. Benefited from its parallel execution logic, the calculation of large-scale data can obtain a faster speed than CPU.
[0004] At present, the implementation of large-scale multiplication and addition operation on FPGA is mostly realized by linear array structure composed of basic processing units (PE) and its improvement. The basic processing unit can complete a multiplication and addition operation once, but with the increase of available resources of FPGA, the speed limit of using more on-chip resources to improve the speed is not high due to the basic unit structure. SUMMARY
[0005] One object of the application is to provide a floating point multiplier-adder based on FPGA, and another object of the application is to provide a calculation method of the floating point multiplier-adder based on FPGA.
[0006] To achieve the above object, the floating point multiplier-adder based on FPGA comprises a data distribution module, a floating point multiplier layer, a floating point adder array and an accumulator.
[0007] The data distribution module is used for sending the to-be-calculated data and control signals required for multiplication and addition to the floating point multiplier layer.
[0008] The floating point multiplier layer is composed of a plurality of multiplier modules, which are used for receiving the to-be-calculated data and sending the calculation product and control signals to the floating point adder array.
[0009] The floating-point adder array is composed of several layers of adder layers, and each layer of adder is composed of several adder modules performing the same batch of addition operations. The floating-point adder array is used for summing the calculation results of the floating-point multiplier layer and transmitting the final sum result and control signals to the accumulator.
[0010] The accumulator is used for accumulating the results obtained by the floating-point adder array until the termination signal is obtained to end the calculation and output the result.
[0011] The control signal sent by the data distribution module is the control signal input by the data distribution module to the floating-point multiplier layer. The control signal is a termination signal or a new input signal.
[0012] The control signal sent by the floating-point multiplier layer includes:
[0013] 1) The control signal sent by the floating-point multiplier layer to the data distribution module: a working state limiting signal.
[0014] 2) The control signal sent by the floating-point multiplier layer to the floating-point adder array: a termination signal or a new input signal.
[0015] The control signal sent by the floating-point adder array includes:
[0016] 1) The control signal sent by the floating-point adder array to the floating-point multiplier layer: a working state limiting signal.
[0017] 2) The control signal sent by the floating-point adder array to the accumulator: a termination signal or a new input signal.
[0018] The control signal sent by the accumulator includes:
[0019] The control signal sent by the accumulator to the floating-point adder array: a working state limiting signal.
[0020] The processing flow of the working state limiting signal is as follows: when the next module connected to the module is in a working state and has cached a to-be-calculated data, the working state limiting signal of the module is set to 1, at this time, the module receives the signal and enters a to-be-distributed state, until the next module processes the working state data and reads the to-be-calculated data, and the working state limiting signal is set to 0.
[0021] The processing flow of the termination signal is as follows: when the transmitted data is the last group of data (a, b)' or the calculation result related to the last group of data (a, b)', the termination signal is set.
[0022] The data (a, b)' is the last group of data in the calculation.
[0023] The termination signal is set to 0 after one clock.
[0024] The processing flow of the new input signal is that when the module completes calculation and transmits the result to the next module, the result output is set to 1; and the new input signal is set to 0 after one clock.
[0025] The floating-point multiplication and addition calculation method of the floating-point multiplier based on the FPGA comprises,
[0026] a. obtaining a plurality of groups of data (a, b) to be operated;
[0027] b. the data (a, b) are sequentially distributed to the multiplier modules in the floating-point multiplier layer to obtain partial products;
[0028] c. the partial products are summed by the floating-point adder array to obtain a partial product sum;
[0029] d. the partial product sum is accumulated by the accumulator to obtain a multiplication and addition result.
[0030] The step a specifically comprises: obtaining the data (a, b) through a data bus, or reading out the data (a, b) in a storage module through an address; and the storage module is an on-chip storage resource or an external storage device.
[0031] The step b specifically comprises: a data distribution module distributes the data (a, b) in the step a to the multiplier modules in the floating-point multiplier layer in a sequential order, and the multiplier modules perform multiplication on the data (a, b) to obtain partial products and transfer the results to the floating-point adder array.
[0032] The step c specifically comprises: a first layer of adder layers of the floating-point adder array receives the calculation results of the multiplier layer and completes the first calculation, and then is transmitted to the next layer; and then each layer of adder layers receives the calculation results of the previous layer and is transmitted to the next layer, until only one adder module 31 in the layer is calculated, and the final summation result and a control signal are transmitted to the accumulator;
[0033] The step d specifically comprises: the accumulator obtains the partial product sum calculated by the floating-point adder array and performs accumulation; when a termination signal Fin=1 is obtained, the accumulation state is ended, the accumulation result is output, and the cache is emptied until the next data arrives.
[0034] The on-chip storage resource is one or a combination of ROM and RAM, and the external storage device is one or a combination of an SD card, a U disk and DDR3.
[0035] When the data is distributed to the multiplier module:
[0036] 1) If the multiplier to be allocated is in an idle state or is working but has not cached any data to be calculated, the data allocation module will allocate the data to the multiplier; if the multiplier to be allocated is in a working state and has already cached a data to be calculated, the data allocation module will enter the allocation state until the multiplier to be allocated finishes processing the working state data and reads the data to be calculated.
[0037] 2) If the assigned data (a,b)' is the last set of required data, then the data transmission termination signal Fin = 1; otherwise, the termination signal Fin = 0.
[0038] When the multiplier completes its calculation and transmits part of the product to the adder module of the first layer in the floating-point adder array:
[0039] 1) If the adder module connected to the multiplier is in an idle state or is working but has not cached any data to be calculated, the multiplier will allocate the data to the adder module; if the adder module connected to the multiplier is in a working state and has already cached a data to be calculated, the multiplier will enter a waiting state until the adder module to be allocated finishes processing the working state data and reads the data to be calculated.
[0040] 2) If the allocated data is the product of the last part, then the data transmission termination signal Fin = 1; otherwise, the termination signal Fin = 0.
[0041] The floating-point multiplier layer consists of 2k multiplier modules.
[0042] The number of adder layers and the number of adder modules within each adder layer are determined by the following rules:
[0043] The first layer of adders consists of k adder modules;
[0044] The second adder layer consists of k / 2 adder modules. If the sum is not divisible, it is rounded down and the kth adder module is marked as a signal to be connected. The number of subsequent adder layers is determined by this logic.
[0045] 1) If the number of adder modules in the previous layer x is divisible by 2, then the number of adder modules in this layer is x / 2. If there is a signal to be connected, it will be carried over to the next layer.
[0046] 2) If the number of adder modules x in the previous layer is not divisible by 2 and there is no signal to be connected, then the number of adder modules in this layer is (x-1) / 2, and the xth adder module is marked as a signal to be connected.
[0047] 3) If the number of adder modules in the last layer is not divisible by 2 and there is a signal to be connected, the number of adder modules in the current layer is x / 2, and the x / 2th adder module is connected to the xth adder module in the last layer and the signal to be connected;
[0048] 4) When the number of adder modules in the current layer is one and there is no signal to be connected, the current layer is the last layer of adder, and the partial product sum is output to the accumulator.
[0049] All adder modules in the floating-point adder array have the following logic: let the two input ends of the adder module be a and b, and the output end be c; then:
[0050] When the termination signal Fin_a of a is 1, c=a and the termination signal Fin_c of c is 1;
[0051] When the termination signal Fin_b of b is 1, c=a+b and the termination signal Fin_c of c is 1;
[0052] When the termination signals Fin_a and Fin_b are both 0, c=a+b and the termination signal Fin_c of c is 0.
[0053] The floating-point multiplier-adder and the calculation method based on FPGA have the beneficial effect that more on-chip resources are used to improve the upper limit of speed by extending the multiplier layer and the adder array, and the contents of the multiplier layer, the adder array, and the accumulation module do not need to be changed. For ordinary technical personnel in the field, it is very simple and efficient to configure different numbers of multipliers in the multiplier layer according to different FPGA chip resources, which improves the upper limit of operation time. BRIEF DESCRIPTION OF DRAWINGS
[0054] Figure 1 It is a structural diagram of a floating-point multiplier-adder;
[0055] Figure 2 It is a structural diagram of a multiplier layer in a floating-point multiplier-adder;
[0056] Figure 3 It is a structural diagram of an adder array in a floating-point multiplier-adder;
[0057] Figure 4 It is a structural diagram of a multiplier state machine in a floating-point multiplier-adder;
[0058] Figure 5 It is a structural diagram of a six-column multiplier-adder;
[0059] Figure 6 It is a flowchart of a floating-point multiplication and addition calculation method;
[0060] In the diagram: 1-Data allocation module, 2-Floating-point multiplier layer, 21-Multiplier module, 3-Floating-point adder array, 31-Adder module, 4-Accumulator;
[0061] 44 - Operating state limit signal; 45 - New input signal;
[0062] 401 - Idle state (Over), 402 - Read cache state (Start), 403 - Front-end processing state (Reset), 404 - Multiply by zero state (Zerock), 405 - Mantissa multiplication state (Cheng), 406 - Mantissa normalization state (Infifl), 407 - Exponent addition state (Exequal), 408 - Pending assignment state, 411 - Initial state (Load), 412 - Working state (Doing). Detailed Implementation
[0063] Example 1
[0064] like Figures 1-6 As shown, the floating-point multiply-accumulator based on FPGA of the present invention includes a data allocation module 1, a floating-point multiplier layer 2, a floating-point adder array 3, and an accumulator 4;
[0065] The data allocation module 1 is used to send the data to be calculated and the control signals to be multiplied and added to the floating point multiplier layer 2.
[0066] The floating-point multiplier layer 2 consists of several multiplier modules 21, which are used to receive the data to be calculated and send the calculated product result and control signal to the floating-point adder array 3.
[0067] The floating-point adder array 3 consists of several adder layers, each of which consists of several adder modules 31 that perform the same batch of addition operations. The floating-point adder array 3 is used to sum the calculation results of the floating-point multiplier layer 2 and transmit the final summation result and control signal to the accumulator 4.
[0068] The accumulator 4 is used to accumulate the results obtained from the floating-point adder array 3 until a termination signal is obtained to end the calculation and output the result.
[0069] The control signals issued by the data allocation module 1 are the control signals input by the data allocation module to the floating-point multiplier layer 2. The control signals are termination signals and new input signals.
[0070] The control signals issued by the floating-point multiplier layer 2 include:
[0071] 1) Control signals sent from floating-point multiplier layer 2 to data allocation module 1: operating state limit signals;
[0072] 2) Control signal sent by floating-point multiplier layer 2 to floating-point adder array 3: termination signal, new input signal.
[0073] The control signal sent by the floating-point adder array 3 is:
[0074] 1) Control signal sent by floating-point adder array 3 to floating-point multiplier layer 2: working state limiting signal;
[0075] 2) Control signal sent by floating-point adder array 3 to accumulator 4: termination signal, new input signal.
[0076] The control signal sent by the accumulator 4 is:
[0077] The control signal sent by the accumulator 4 to the floating-point adder array 3 is: working state limiting signal.
[0078] The processing flow of the working state limiting signal is: when the next module connected to the module is in working state and has cached a to-be-calculated data, the working state limiting signal of the next module to the module is set to 1, at this time the module receives the signal and enters the to-be-distributed state, until the to-be-distributed next module processes the working state data and reads the to-be-calculated data, and the working state limiting signal is set to 0.
[0079] The processing flow of the termination signal is: when the transmitted data is the last group of data (a, b)' required for calculation or the calculation result related to the last group of data (a, b)', the termination signal;
[0080] The data (a, b)' is the last group of data for calculation;
[0081] The termination signal is set to 0 after one clock;
[0082] The processing flow of the new input signal is: when the module completes calculation and transmits the result to the next module, the new input signal is set to 1; the new input signal is set to 0 after one clock.
[0083] The calculation method of the floating-point multiplier-accumulator based on FPGA comprises:
[0084] a. Obtain a plurality of groups of data (a, b) required for operation through a data bus;
[0085] b. The data (a, b) is sequentially distributed to the multiplier module 21 in the floating-point multiplier layer 2 to obtain partial products, the data distribution module 1 distributes the data a and b in step a to the multiplier module 21 in the floating-point multiplier layer 2 in the order, and the multiplier module 21 performs multiplication operation on the data a and b to obtain partial products, and the result is transferred to the floating-point adder array 3;
[0086] c. The partial products are summed by the floating-point adder array 3 to obtain partial product sums. The first layer of adders of the floating-point adder array 3 receives the calculation results of the multiplier layer 2 and completes the first calculation, and then passes to the next layer. Each layer of adders then receives the calculation results of the previous layer and passes to the next layer until the adder module 31 in the layer has only one, and the calculation is completed. The final summation result and the control signal are passed to the accumulator 4;
[0087] d. The partial product sums are accumulated by the accumulator 4 to obtain the multiplication and addition result. The accumulator 4 obtains the partial product sums calculated by the floating-point adder array 3 for accumulation. When the termination signal Fin = 1 is obtained, the accumulation state is ended, the accumulation result is output, and the buffer is emptied until the next data arrives.
[0088] When the data is sent to the multiplier module 21:
[0089] 1) If the multiplier module 21 to be allocated is in an idle state or is working but has no buffered data to be calculated, the data allocation module 1 allocates the data to the multiplier module 21. If the multiplier module 21 to be sent is in a working state and has buffered a data to be calculated, the data allocation module 1 enters a waiting allocation state until the multiplier module 21 to be allocated processes the working state data and reads the data to be calculated.
[0090] 2) If the allocated data (a, b)' is the last set of required data, the data transmission termination signal Fin = 1 is accompanied. Otherwise, the termination signal Fin = 0.
[0091] When the multiplier calculates and transmits the partial product to the adder module 31 in the first layer of the floating-point adder array:
[0092] 1) If the adder module 31 connected to the multiplier module 21 is in an idle state or is working but has no buffered data to be calculated, the multiplier module 21 allocates the data to the adder module 31. If the adder module 31 connected to the multiplier module 21 is in a working state and has buffered a data to be calculated, the multiplier module 21 enters a waiting allocation state until the adder module 31 to be allocated processes the working state data and reads the data to be calculated.
[0093] 2) If the allocated data is the last partial product, the data transmission termination signal Fin = 1 is accompanied. Otherwise, the termination signal Fin = 0.
[0094] The floating-point multiplier layer 2 is composed of 2k multiplier modules 21;
[0095] The number of adder layers and adder modules 31 in the adder layer is composed of the following rules:
[0096] The first layer of adder layer is composed of k adder modules 31;
[0097] The second layer of adder layer is composed of k / 2 adder modules 31, if not divisible, then take down and mark the kth adder module 31 as a signal to be connected; the number of subsequent adder layers is determined by this logic:
[0098] 1) If the number x of adder modules 31 of the previous layer is divisible by 2, then the number of adder modules 31 of the current layer is x / 2, if there is a signal to be connected, then it is extended to the next layer;
[0099] 2) If the number x of adder modules 31 of the previous layer is not divisible by 2 and there is no signal to be connected, then the number of adder modules 31 of the current layer is (x-1) / 2, and the xth adder module 31 is marked as a signal to be connected;
[0100] 3) If the number x of adder modules 31 of the previous layer is not divisible by 2 and there is a signal to be connected, then the number of adder modules 31 of the current layer is x / 2, and the x / 2th adder module 31 is connected to the xth adder module 31 of the previous layer and the signal to be connected;
[0101] 4) When the number of adder modules 31 of the current layer is one and there is no signal to be connected, the current layer is the last layer of adder layer, and part of the product is output to the accumulator.
[0102] All adders in the floating-point adder array have the following logic: let the two input ends of the adder be a and b, and the output end be c; then:
[0103] When the termination signal Fin_a of a is 1, c=a and the termination signal Fin_c of c is 1;
[0104] When the termination signal Fin_b of b is 1, c=a+b and the termination signal Fin_c of c is 1;
[0105] When the termination signals Fin_a and Fin_b are both 0, c=a+b and the termination signal Fin_c of c is 0.
[0106] Embodiment 2
[0107] The floating-point multiplier-adder based on FPGA provided by the application, as shown in the figure, comprises a data distributor 1, a floating-point multiplier layer 2, a floating-point adder array 3 and an accumulator 4, Figures 1-6
[0108] The data distributor 1 is used to send the data to be calculated and control signals required for multiplication and addition to the floating-point multiplier layer 2;
[0109] The floating-point multiplier layer 2 is composed of at least two multiplier modules 21, which are used to receive data to be calculated and transmit the calculated product and control signals to the floating-point adder array 3.
[0110] The floating-point adder array 3 is composed of an adder layer, which is provided with at least one layer and is composed of at least one adder module 31, which is used to transmit the calculated result and control signals to the accumulator 4.
[0111] The number of layers of the adder layer and the number of adder modules 31 in the layer are related to the number of multiplications in the floating-point multiplier layer 2, and are used to transmit the calculated result and control signals to the accumulator 4.
[0112] The accumulator 4 is used to accumulate the results obtained by the floating-point adder array 3 until a termination signal is obtained to end the calculation and output the result.
[0113] The control signals sent by the data distribution module 1 to the floating-point multiplier layer 2 include a termination signal Fin, new input signals new_a and new_b.
[0114] The control signals sent by the floating-point multiplier layer 2 to the data distribution module 1 include a working state limiting signal hold_in.
[0115] The control signals sent by the floating-point multiplier layer 2 to the floating-point adder array 3 include termination signals Fin_a and Fin_b, and new input signals new_a and new_b.
[0116] The control signals sent by the floating-point adder array 3 to the floating-point multiplier layer 2 include a working state limiting signal hold_in.
[0117] The control signals sent by the floating-point adder array 3 to the accumulator 4 include a termination signal Fin and a new input signal new.
[0118] The control signals sent by the accumulator 4 to the floating-point adder array 3 include a working state limiting signal hold_in.
[0119] The processing flow of the working state limiting signal hold_in is as follows: when the next module connected to the module is in a working state and has cached a data to be calculated, the working state limiting signal hold_in of the module is 1, at this time the module receives this signal and enters a waiting distribution state, until the next module in the working state processes the data to be calculated and reads the data to be calculated, and the working state limiting signal hold_in is 0.
[0120] The processing flow of the termination signal Fin (Fin_a, Fin_b, and the like are all heteronym names) is as follows: when the transmitted data is the last group of data (a, b)' required for calculation or the calculation result related to the last group of data (a, b)', the termination signal Fin = 1.
[0121] The termination signal Fin becomes Fin = 0 after one clock.
[0122] The processing flow of the new input signal new (new_a, new_b, new_in, and the like are all heteronym names) is as follows: when the module finishes calculation and transmits the result to the next module, the new input signal new = 1 is outputted.
[0123] The new input signal new becomes new = 0 after one clock.
[0124] The floating-point multiplication-adder calculation method of the floating-point multiplication-adder based on FPGA runs as follows:
[0125] When the control signal sent by the floating-point multiplier layer 2 to the data distribution module 1 is the working state limiting signal hold_in, when a certain multiplier module 21 connected with the data distribution module 1 is in the working state and has buffered a to-be-calculated data, the multiplier module 21 gives the working state limiting signal hold_in = 1 to the data distribution module 1, at this time, the data distribution module 1 receives the signal and enters the to-be-distributed state, until the to-be-calculated data is processed and read by the working state data of the to-be-distributed multiplier module 21.
[0126] The working state limiting signal name for controlling the next module is hold_in, and the working state limiting signal name for controlling the previous module is hold_out, both of which are working state limiting signals, and the different names are only different from the perspective of the module, and there is no essential difference.
[0127] As shown in Figure 4 The calculation part state of the multiplier module 21 includes the idle state Over 401, the reading buffer state Start 402, the front-end processing state Reset 403, the multiplication zero judgment state Zerock 404, the mantissa multiplication state Cheng 405, the mantissa normalization state Infifl 406, the exponent addition state Exequal 407, and the to-be-assigned state 408; the pre-input signal control part state of the multiplier module 21 includes the initial state Load 411 and the working state Doing 412.
[0128] The input signal control part of the multiplier module 21 is in the initial state Load 411, which sets the working state restriction signal hold_out of the previous module to zero, indicating that the data can be received, and then the state machine jumps to the working state Doing 412. The function of the working state Doing 412 is that when the new input signal 45new_in=1, the data to be calculated is pre-cached, and the working state restriction signal 44hold_out is set to high level. At the same time, if the termination signal Fin=1, the data is marked, and until the state of the multiplier calculation part reaches the read cache state Start 402, the working state restriction signal hold_out is set to low level. The high level of hold_out can also be understood as having data to be calculated.
[0129] The working state of the multiplier module 21 is specifically: the initial state of the multiplier is in the idle state Over 401, at this time all internal signals are set to zero, when the working state restriction signal 44hold_out is high, the state jumps to the read cache state Start 402. The function of the read cache state Start 402 is to read the pre-cached data to be calculated in Doing 412, and to identify whether the data is termination data, and then the state jumps to the front-end processing state Reset 403. The function of the front-end processing state Reset 403 is to separate the exponent and restore the mantissa of the data, and the sign bit of the result is calculated through an XOR gate, and then the state jumps to the zero multiplication judgment state Zerock 404. The function of the zero multiplication judgment state Zerock 404 is to judge whether a and b are zero, if there is zero, the output is directly zero, and jump to the assignment state 408, if not, the state jumps to the mantissa multiplication state Cheng 405. The function of the mantissa multiplication state Cheng 405 is to multiply the mantissa, and then the state jumps to the mantissa normalization state Infifl 406. The function of the mantissa normalization state Infifl 406 is to adjust the format of the mantissa to the required floating point format and calculate the carry, and then the state jumps to the exponent addition state Exequal 407. The function of the exponent addition state Exequal 407 is to add the exponents and add the carry, and then the state jumps to the assignment state 408. The function of the assignment state 408 is that when the working state restriction signal hold_in==1, it indicates that the next module is in the working state and has cached a data to be calculated, at this time the module enters the waiting state, until hold_in==0, the calculation result is output and the new output signal new_out is set to high level, and then the state jumps to the idle state Over 401.
[0130] It should be noted that the logic and structure of the floating point adder array and the floating point adder module are similar.
[0131] The calculation method of the FPGA-based floating-point multiplier-adder, which comprises the following specific steps:
[0132] 1) obtaining data;
[0133] 2) distributing the data to each multiplier module 21;
[0134] 3) determining whether the multiplier module 21 is idle at this time, if not, entering a waiting distribution state until idle, and then inputting data;
[0135] 4) the multiplier module 21 calculates partial products;
[0136] 5) inputting the partial products to the floating-point adder array 3;
[0137] 6) determining whether the adder module 31 is idle at this time, if not, entering a waiting distribution state until idle, and then inputting data;
[0138] 7) the adder module 31 of the first layer calculates the sum corresponding to the multiplier;
[0139] 8) transmitting the result to the adder module 31 of the next layer;
[0140] 9) determining whether the adder module 31 of the next layer is idle at this time, if not, entering a waiting distribution state until idle, and then inputting data;
[0141] 10) calculating the result;
[0142] 11) determining whether this layer is the last layer of the adder module 31, if not, repeating steps 8) to 10) until the last layer of the adder module 31;
[0143] 12) transmitting the partial products and the sum to the accumulator 4;
[0144] 13) determining whether the accumulator 4 is idle at this time, if not, entering a waiting distribution state until idle, and then inputting data;
[0145] 14) the accumulator 4 performs accumulation;
[0146] 15) determining whether the calculation is complete, if not, repeating steps 2) to 14) until all groups of data are calculated;
[0147] 16) outputting the multiplication-addition result.
Claims
1. A floating-point multiply-accumulator based on FPGA, comprising a data allocation module (1), a floating-point multiplier layer (2), a floating-point adder array (3), and an accumulator (4), characterized in that: The data allocation module (1) is used to send the data to be calculated and the control signals to be multiplied and added to the floating point multiplier layer (2). The floating-point multiplier layer (2) consists of several multiplier modules (21) used to receive the data to be calculated and send the calculated product result and control signal to the floating-point adder array (3). The floating-point adder array (3) consists of several adder layers. Each adder layer consists of several adder modules (31) that perform the same batch of addition operations. The floating-point adder array (3) is used to sum the calculation results of the floating-point multiplier layer (2) and transmit the final summation result and control signal to the accumulator (4). The accumulator (4) is used to accumulate the results obtained from the floating-point adder array (3) until a termination signal is obtained to end the calculation and output the result; The processing flow of the working state limit signal is as follows: When the next-level module connected to this module is in the working state and has cached a piece of data to be calculated, the next-level module sets the working state limit signal of this module to 1. At this time, this module receives this signal and enters the waiting-to-be-allocated state until the next-level module to be allocated finishes processing the working state data and reads the data to be calculated, and then the working state limit signal is set to zero. The processing flow of the termination signal is as follows: when the transmitted data is the last set of data (a,b)' to be calculated or the calculation result related to the last set of data (a,b)', the termination signal is activated; The data (a, b)' is used for calculation The last set of data ; The termination signal is set to zero after one clock cycle. The processing flow for the new input signal is as follows: when this module completes the calculation and transmits the result to the next module, the output of the accompanying result is set to 1; the new input signal is set to zero after one clock cycle.
2. The FPGA-based floating-point multiply-accumulator according to claim 1, characterized in that: The control signal issued by the data allocation module (1) is the control signal input by the data allocation module to the floating-point multiplier layer (2), and the control signal is a termination signal and a new input signal.
3. The FPGA-based floating-point multiply-accumulator according to claim 1, characterized in that: The control signals issued by the floating-point multiplier layer (2) include: 1) Control signals sent from the floating-point multiplier layer (2) to the data allocation module (1): operating state limit signals; 2) Control signals sent from the floating-point multiplier layer (2) to the floating-point adder array (3): termination signal and new input signal.
4. The FPGA-based floating-point multiply-accumulator according to claim 1, characterized in that: The control signals issued by the floating-point adder array (3) include: 1) Control signals sent from the floating-point adder array (3) to the floating-point multiplier layer (2): operating state limit signals; 2) Control signals sent from the floating-point adder array (3) to the accumulator (4): termination signal; new input signal.
5. The FPGA-based floating-point multiply-accumulator according to claim 1, characterized in that: The control signal issued by the accumulator (4) is: The control signal sent by the accumulator (4) to the floating-point adder array (3) is the working state limit signal.
6. A floating-point multiply-accumulate calculation method based on an FPGA, which employs the floating-point multiply-accumulate as described in claim 1, characterized in that: include, a. Obtain several sets of data (a, b) that need to be calculated; b. The data (a, b) are sequentially distributed to the multiplier module (21) in the floating-point multiplier layer (2) to obtain a partial product; c. The partial product is obtained by summing the partial products using the floating-point adder array (3); d. The partial product sum is accumulated by accumulator (4) to obtain the multiplication-addition result.
7. The floating-point multiply-accumulate calculation method based on an FPGA as described in claim 6, characterized in that: Step a specifically involves: acquiring data (a, b) via the data bus, or reading the data (a, b) from the storage module via an address; the storage module is either on-chip storage or an external storage device.
8. The floating-point multiply-accumulate calculation method based on an FPGA as described in claim 7, characterized in that: Step b is specifically as follows: the data allocation module (1) allocates the data (a,b) mentioned in step a to the multiplier module (21) in the floating-point multiplier layer (2) in order. The multiplier module (21) performs a multiplication operation on the data (a,b) to obtain a partial product and transfers the result to the floating-point adder array (3).
9. The floating-point multiply-accumulate calculation method based on an FPGA as described in claim 7, characterized in that: Step c specifically involves the following: the first adder layer of the floating-point adder array (3) receives the calculation result of the floating-point multiplier layer (2) and completes the first calculation, and then passes it to the next layer; Each adder layer then receives the calculation result from the previous layer and passes it to the next layer until there is only one adder module (31) in that layer. The calculation is then completed, and the final summation result and control signal are passed to the accumulator (4). The specific steps of step d are as follows: the accumulator (4) obtains the partial product sum calculated by the floating-point adder array (3) and accumulates it. When the termination signal Fin=1 is obtained, the accumulation state ends, the accumulation result is output and the buffer is cleared until the next data arrives.