Heterogeneous soc ship target detection and tracking power consumption optimization method and electronic device

Abstract

The application relates to a heterogeneous SOC ship target detection and tracking power consumption optimization method and electronic equipment, and the method comprises the following steps: adjusting bit precision and neural network levels to construct a plurality of algorithm model matrices with different power consumptions; collecting the working states of each software by using a low-power CPU to calculate the power consumption changes of the software; according to the power consumption changes, the FPGA and the high-performance CPU used for target detection are controlled to be turned on and off; and according to the total power consumption and a preset power consumption threshold, a suitable algorithm is selected from the algorithm matrix, and the high-performance CPU used for target tracking in operation is temporarily controlled to be turned off. According to the application, on the basis of efficiently completing ship target detection, the CPU and the FPGA are dynamically turned on and off, the detection algorithm is dynamically adjusted, the balance between the system power consumption and the calculation capacity is ensured, and the power consumption is greatly reduced.

Description

Technical Field

[0001] This invention relates to the field of ship target detection technology, specifically to a method and electronic device for optimizing power consumption in ship target detection and tracking based on heterogeneous SOC. Background Technology

[0002] With the continuous evolution of operational concepts and systems, only by comprehensively and rapidly grasping the battlefield situation can quick decisions be made to gain operational advantage. Satellites possess the characteristics of all-weather operation, long-range visibility, and high accuracy, enabling the detection and tracking of naval targets through image recognition technology. However, due to the large volume of satellite image data, low satellite transmission efficiency, and numerous transfer nodes, a significant amount of time is consumed before the target detection software on the ground can perform its detection. Therefore, to address the timeliness issue of target detection, real-time detection and tracking on satellites can be considered. Given the power consumption limitations of satellites, the detection equipment needs to be highly efficient, highly reliable, and low-power; the traditional CPU+GPU approach can no longer meet this requirement.

[0003] In recent years, image detection, recognition and tracking technologies have been widely researched and applied, but the detection accuracy and continuous tracking capability of devices under low power consumption conditions are still insufficient; while improving detection capability will lead to increased power consumption and extended detection time. Summary of the Invention

[0004] In view of the above-mentioned technical problems, the present invention proposes a power consumption optimization method and electronic device for ship target detection and tracking based on heterogeneous SOC, which has the advantages of high reliability, high efficiency and low power consumption.

[0005] The technical solution to achieve the purpose of this invention is: a power consumption optimization method for ship target detection and tracking based on heterogeneous SOC, comprising the following steps:

[0006] Step S1: By adjusting the bit precision and neural network layers, construct multiple algorithm model matrices with different power consumption.

[0007] Step S2: Use a low-power CPU to collect the working status of each software and calculate the power consumption changes of the software.

[0008] Step S3: Based on the power consumption changes, control the FPGA used for target detection to turn on and off, and control the high-performance CPU used for target tracking to turn on and off;

[0009] Step S4: Based on the total power consumption and the preset power consumption threshold, select the algorithm model and temporarily shut down the high-performance CPU used for target tracking.

[0010] According to one aspect of the present invention, step S1 specifically includes:

[0011] Step S11: On the convolutional neural network, convert the convolution kernel to a fixed point form;

[0012] Step S12: Adjust bit precision;

[0013] Step S13: Adjust the neural network layers;

[0014] Step S14: Train the model on a high-performance GPU server;

[0015] Step S15: Generate IP core, download IP core and model to FPGA for testing, and calculate power consumption;

[0016] Step S16: Repeat steps S12 to S15 to construct multiple algorithm model matrices with different power consumption.

[0017] According to one aspect of the present invention, step S3 specifically includes:

[0018] Step S301: Determine whether the power consumption of the software is consistently less than or equal to a preset threshold over a period of time;

[0019] Step S302: When the power consumption of the target detection software is less than or equal to a preset threshold, the target detection software is determined to be in standby mode, and the FPGA is controlled to shut down.

[0020] Step S303: When the power consumption of the target tracking software is less than or equal to a preset threshold, the target tracking software is determined to be in standby mode, and the high-performance CPU is controlled to shut down.

[0021] According to one aspect of the present invention, in step S4, selecting an algorithm model based on the total power consumption and a preset power consumption threshold specifically includes:

[0022] Step S401: Calculate the total power consumption of the system in real time;

[0023] Step S402: Calculate the total power consumption of the system and the sum of the power consumption of multiple algorithm models. Based on the sum of power consumption and the preset power consumption threshold, determine the optimal algorithm model.

[0024] Step S403: Transmit the algorithm model confirmed in step S402 to the FPGA for target detection.

[0025] According to one aspect of the invention, step S402 includes:

[0026] The power consumption is compared with the preset power consumption thresholds in descending order. When the power consumption is less than the preset power consumption threshold, the algorithm model corresponding to that power consumption is confirmed as the best algorithm model.

[0027] When the minimum power consumption exceeds the preset power consumption threshold, the high-performance CPU in operation will be temporarily shut down until the target detection is completed before target tracking is performed.

[0028] According to one aspect of the present invention, an electronic device is provided, comprising: at least one low-performance CPU, at least one high-performance CPU, at least one FPGA, one or more memories, and one or more computer programs; wherein the processor is connected to the memory, the one or more computer programs are stored in the memory, and when the electronic device is running, the processor executes the one or more computer programs stored in the memory to cause the electronic device to perform a power consumption optimization method for ship target detection and tracking based on heterogeneous SOC as described in any of the above technical solutions.

[0029] According to one aspect of the present invention, a computer-readable storage medium is provided for storing computer instructions, which, when executed by a processor, implement a power consumption optimization method for ship target detection and tracking based on heterogeneous SOC as described in any of the above technical solutions.

[0030] Based on the concept of this invention, a power consumption optimization method and electronic device for ship target detection and tracking based on heterogeneous SOC are proposed. The efficient detection algorithm running on FPGA is constructed by adjusting bit precision and neural network layers to construct multiple algorithm model matrices with different power consumption. The detection model is selected according to the power consumption changes of the software, the total power consumption, and the preset power consumption threshold. While ensuring efficient ship target detection, the detection algorithm is dynamically adjusted by dynamically turning the CPU and FPGA on and off to ensure a balance between system power consumption and computing power, which greatly reduces power consumption.

[0031] According to one aspect of the present invention, in a convolutional neural network, the convolution kernel is converted to fixed-point form, which reduces the use of FPGA resources and reduces the precision of the convolutional neural network to half precision, thereby reducing the output of each network layer so that it can be stored in the memory inside the FPGA, effectively accelerating the inference time, solving the problem of weak floating-point operation capability on the FPGA, and designing an algorithm matrix problem that is determined by multiple factors such as network size, precision, accuracy, and power consumption. Attached Figure Description

[0032] Figure 1 The diagram illustrates a flowchart of a method for optimizing the power consumption of ship target detection and tracking based on a heterogeneous SOC according to an embodiment of the present invention. Detailed Implementation

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0034] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. The embodiments cannot be described in detail here, but the embodiments of the present invention are not limited to the following embodiments.

[0035] like Figure 1 As shown, the present invention provides a method for optimizing the power consumption of ship target detection and tracking based on heterogeneous SOC, characterized by comprising the following steps:

[0036] Step S1: By adjusting the bit precision and neural network layers, construct multiple algorithm model matrices with different power consumption.

[0037] Step S2: Use a low-power CPU to collect the working status of each software and calculate the power consumption changes of the software.

[0038] Step S3: Based on the power consumption changes, control the FPGA used for target detection to turn on and off, and control the high-performance CPU used for target tracking to turn on and off;

[0039] Step S4: Based on the total power consumption and the preset power consumption threshold, select the algorithm model and temporarily shut down the high-performance CPU used for target tracking.

[0040] In this embodiment, the high-efficiency detection algorithm running on the FPGA constructs multiple algorithm model matrices with different power consumption by adjusting bit precision and neural network levels. Based on the power consumption changes of the software, the total power consumption, and the preset power consumption threshold, the detection model is selected. While ensuring efficient completion of ship target detection, the detection algorithm is dynamically adjusted by dynamically turning the CPU and FPGA on and off to ensure a balance between system power consumption and computing power, which greatly reduces power consumption.

[0041] In one embodiment of the present invention, preferably, step S1 specifically includes:

[0042] Step S11: On the convolutional neural network, the convolution kernel is converted to a fixed point form to reduce the use of FPGA resources;

[0043] Step S12: Adjust the bit precision. The limit can be adjusted to one bit, with a conversion factor of 1, which can convert the floating-point coefficient into a binary value.

[0044] Step S13: Adjust the neural network layers;

[0045] Step S14: Train the model on a high-performance GPU server;

[0046] Step S15: Generate IP core, download IP core and model to FPGA for testing, and calculate power consumption;

[0047] Step S16: Repeat steps S12 to S15 to construct multiple algorithm model matrices with different power consumption.

[0048] In this embodiment, the precision of the convolutional neural network is reduced to half precision, which reduces the output of each network layer so that it can be stored in the memory inside the FPGA, effectively accelerating the inference time. This solves the problem of weak floating-point arithmetic capability on the FPGA and addresses the algorithm matrix problem that is determined by multiple factors such as network size, precision, accuracy, and power consumption.

[0049] In one embodiment of the present invention, preferably, step S3 specifically includes:

[0050] Step S301: Determine whether the power consumption of the software is consistently less than or equal to a preset threshold over a period of time;

[0051] Step S302: When the power consumption of the target detection software is less than or equal to a preset threshold, it can be determined that the target detection software is in standby mode and the FPGA is controlled to shut down.

[0052] Step S303: When the power consumption of the target tracking software is less than or equal to a preset threshold, it can be determined that the target tracking software is in standby mode, and the high-performance CPU is controlled to be turned off.

[0053] In this embodiment, if the target detection software is in standby mode, the FPGA is turned off; if the target tracking software is in standby mode, the high-performance CPU is turned off, thereby reducing system power consumption.

[0054] In one embodiment of the present invention, preferably, in step S4, selecting an algorithm model based on the total power consumption and a preset power consumption threshold specifically includes:

[0055] Step S401: Calculate the total power consumption of the system in real time;

[0056] Step S402: Calculate the total power consumption of the system and the sum of the power consumption of multiple algorithm models. Based on the sum of power consumption and the preset power consumption threshold, determine the optimal algorithm model.

[0057] Step S403: Transmit the algorithm model confirmed in step S402 to the FPGA for target detection.

[0058] In one embodiment of the present invention, preferably, step S402 includes:

[0059] The power consumption is compared with the preset power consumption thresholds in descending order. When the power consumption is less than the preset power consumption threshold, the algorithm model corresponding to that power consumption is confirmed as the best algorithm model.

[0060] When the minimum power consumption exceeds the preset power consumption threshold, the high-performance CPU running in operation is temporarily shut down, and target tracking processing is resumed after the target detection is completed.

[0061] When a new detection task arrives, the FPGA is woken up and calculates the total power consumption of the system in real time. If the power consumption is acceptable, the best matching model is found from the algorithm model matrix and downloaded to the FPGA in real time for target detection. If the target tracking software consumes too much power and cannot find a suitable model, target tracking is stopped and target detection is performed first.

[0062] When a new target tracking requirement arises, the high-performance CPU is activated to perform target tracking calculations. At this time, the power management service calculates the total power consumption of the system in real time. If the power consumption is acceptable, the target tracking software runs. If the power consumption of the target detection algorithm is too high, causing the total power consumption to exceed the limit, the task is placed in a queue, the high-performance CPU is shut down, and target tracking processing is resumed after target detection is completed.

[0063] According to one aspect of the present invention, an electronic device is provided, comprising: at least one low-performance CPU, at least one high-performance CPU, at least one FPGA, one or more memories, and one or more computer programs; wherein the processor is connected to the memory, the one or more computer programs are stored in the memory, and when the electronic device is running, the processor executes the one or more computer programs stored in the memory to cause the electronic device to perform the power consumption optimization method for ship target detection and tracking based on heterogeneous SOC as described in any of the above technical solutions.

[0064] According to one aspect of the present invention, a computer-readable storage medium is provided for storing computer instructions, which, when executed by a processor, implement a power consumption optimization method for ship target detection and tracking based on heterogeneous SOC as described in any of the above technical solutions.

[0065] In summary, this invention proposes a power consumption optimization method and electronic device for ship target detection and tracking based on heterogeneous SOC, and a high-efficiency detection algorithm running on FPGA. By adjusting bit precision and neural network levels, multiple algorithm model matrices with different power consumption are constructed. Based on the power consumption changes of the software, the total power consumption, and the preset power consumption threshold, the detection model matrix is ​​selected. While ensuring efficient ship target detection, the system balances power consumption and computing power by dynamically turning the CPU and FPGA on and off, and dynamically adjusting the detection algorithm, thus greatly reducing power consumption.

[0066] Furthermore, it should be noted that the present invention can be provided as a method, apparatus, or computer program product. Therefore, embodiments of the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code.

[0067] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0068] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing terminal equipment to cause a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0069] It should also be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0070] Finally, it should be noted that the above description represents a preferred embodiment of the present invention. It should be pointed out that although preferred embodiments have been described, those skilled in the art, once they understand the basic inventive concept of the present invention, can make various improvements and modifications without departing from the principles described herein. These improvements and modifications should also be considered within the scope of protection of the present invention. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present invention.

Claims

1. A method for optimizing the power consumption of ship target detection and tracking based on heterogeneous SOC, characterized in that, Includes the following steps: Step S1: By adjusting the bit precision and neural network layers, construct multiple algorithm model matrices with different power consumption. Step S2: Use a low-power CPU to collect the working status of each software and calculate the power consumption changes of the software. Step S3: Based on the power consumption changes, control the FPGA used for target detection to turn on and off, and control the high-performance CPU used for target tracking to turn on and off; Step S4: Based on the total power consumption and the preset power consumption threshold, select the algorithm model and temporarily control the shutdown of the high-performance CPU used for target tracking. In step S4, an algorithm model is selected based on the total power consumption and a preset power consumption threshold, specifically including: Step S401: Calculate the total power consumption of the system in real time; Step S402: Calculate the total power consumption of the system and the sum of the power consumption of multiple algorithm models. Based on the sum of power consumption and the preset power consumption threshold, determine the optimal algorithm model. Step S403: Transmit the algorithm model confirmed in step S402 to the FPGA for target detection; Step S402 includes: The power consumption is compared with the preset power consumption thresholds in descending order. When the power consumption is less than the preset power consumption threshold, the algorithm model corresponding to that power consumption is confirmed as the best algorithm model. When the minimum power consumption exceeds the preset power consumption threshold, the high-performance CPU running in operation is temporarily shut down, and target tracking processing is resumed after the target detection is completed.

2. The method according to claim 1, characterized in that, Step S1 specifically includes: Step S11: On the convolutional neural network, convert the convolution kernel to a fixed point form; Step S12: Adjust bit precision; Step S13: Adjust the neural network layers; Step S14: Train the model on a high-performance GPU server; Step S15: Generate IP core, download IP core and model to FPGA for testing, and calculate power consumption; Step S16: Repeat steps S12 to S15 to construct multiple algorithm model matrices with different power consumption.

3. The method according to claim 1, characterized in that, Step S3 specifically includes: Step S301: Determine whether the power consumption of the software is consistently less than or equal to a preset threshold over a period of time; Step S302: When the power consumption of the target detection software is less than or equal to a preset threshold, it can be determined that the target detection software is in standby mode, and then the FPGA is controlled to shut down. Step S303: When the power consumption of the target tracking software is less than or equal to a preset threshold, it can be determined that no target tracking calculation is being performed, and the high-performance CPU is then shut down.

4. An electronic device, characterized in that, include: The device comprises at least one low-performance CPU, at least one high-performance CPU, at least one FPGA, one or more memories, and one or more computer programs; wherein the processor is connected to the memory, the one or more computer programs are stored in the memory, and when the electronic device is running, the processor executes the one or more computer programs stored in the memory to cause the electronic device to perform the power consumption optimization method for ship target detection and tracking based on heterogeneous SOC as described in any one of claims 1 to 3.

5. A computer-readable storage medium, characterized in that, Used to store computer instructions, which, when executed by a processor, implement the power consumption optimization method for ship target detection and tracking based on heterogeneous SOC as described in any one of claims 1 to 3.

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