A chip package defect detection and positioning method and device

Abstract

The application discloses a chip packaging defect detection and positioning method and device, and the method comprises the following steps: performing PCA preprocessing on a test set and a training set of a chip packaging image; training a deep tensor dictionary learning method based on the features extracted from the training set, so as to obtain a trained deep tensor dictionary; determining a sparse coding third-order matrix based on the features extracted from the test set and the trained deep tensor dictionary; and judging whether the chip packaging image to be detected has defects and positioning the defects based on the sparse coding third-order matrix. The application describes the main features of the image through a three-dimensional dictionary, strengthens the feature expression ability of the deep tensor dictionary by combining deep learning, and approximately represents the image by combining sparse coding, so that whether the image is abnormal can be judged according to the error between the actual image and the approximate representation, and the abnormal position of the image can be positioned according to the sparse coding, thereby improving the detection speed and the detection accuracy of the chip packaging defect detection.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip defect detection, in particular to a chip packaging defect detection and positioning method and device. BACKGROUND

[0002] In view of the urgent need for intelligent chip packaging defect detection, the traditional method requires manual participation, which reduces the speed of the detection process. A pure deep neural network requires a large number of negative samples, and when the number of negative samples is small, the accuracy is low.

[0003] Therefore, new methods and ideas must be considered to assist chip packaging defect detection, improve calculation accuracy, and accelerate the intelligent development of the process line. SUMMARY

[0004] The main purpose of the present application is to provide a chip packaging defect detection and positioning method and device, which aims to solve the technical problem of low detection speed and detection accuracy of current chip packaging defect detection.

[0005] To achieve the above purpose, the present application provides a chip packaging defect detection and positioning method, which comprises the following steps:

[0006] S1: PCA pretreatment is performed on the test set and the training set of the chip packaging image;

[0007] S2: The features extracted from the training set are trained by a deep tensor dictionary learning method to obtain a trained deep tensor dictionary;

[0008] S3: Based on the features extracted from the test set and the trained deep tensor dictionary, a sparse coding third-order matrix is determined;

[0009] S4: According to the sparse coding third-order matrix, it is judged whether the chip packaging image to be detected has defects and the defect positioning.

[0010] Optionally, the step S1 specifically comprises:

[0011] S101: The tensor matrix data of the normal image in the training set is extracted by PCA, and the next step is waited for processing;

[0012] S102: The tensor matrix data of the chip image to be detected in the test set is extracted by PCA, and further processing is waited for.

[0013] Optionally, the step S2 specifically comprises:

[0014] S201: The tensor matrix data Y of the normal image is extracted by PCA to obtain The next step is waited for processing;

[0015] S202: input error tolerance, maximum depth layer, tensor dictionary size parameters;

[0016] S203, for the feature tensor matrix, by K-TSVD tensor dictionary learning method;

[0017] S204, get three-dimensional tensor dictionary Sparse coding third-order matrix And the depth layer +1;

[0018] S205, determine whether the layer reaches the maximum layer;

[0019] S206, if not reach the maximum layer, the sparse coding third-order matrix As input, return to S203 for tensor dictionary learning; if the maximum layer is reached, multiply the tensor matrix obtained by each layer to obtain the perfect tensor dictionary Task end.

[0020] Optionally, the step S3 specifically comprises: inputting the features extracted from the chip image to be detected in the test set into the trained deep tensor dictionary, and obtaining a sparse coding third-order matrix through a tensor dictionary learning method.

[0021] Optionally, in the step S4, judging whether the chip package image to be detected has defects specifically comprises:

[0022] judging whether the error of the sparse coding third-order matrix is greater than the tolerance error, if yes, the image has defects, and the position of the defects in the image is obtained according to the non-zero element position of the sparse coding third-order matrix; if not, the image does not have defects.

[0023] Optionally, the step of obtaining the position of the defects in the image according to the non-zero element position of the sparse coding third-order matrix specifically comprises:

[0024] S401, divide the matrix data of the chip package image to be tested into different block matrix data Yp(j), j = 1, 2,..., p, and wait for the next step processing;

[0025] S402, for a given j, find the corresponding part Dp(j) in the deep tensor dictionary D and the sparse coding matrix part Ap(j), calculate the error e(j) = Yp(j)-Dp(j)*Ap(j), and j+1;

[0026] S403, judge whether j is greater than p, if yes, go to the next step, if not, return to S402;

[0027] S404, for all e(j), find the maximum one in the norm, and the block part in the test image corresponding to the maximum one is the defect, and the task ends.

[0028] In addition, in order to achieve the above object, the application also provides a chip packaging defect detection and positioning device, the device comprises:

[0029] The preprocessing module is used for PCA preprocessing of the test set and the training set of the chip packaging image;

[0030] The training module is used for training the extracted features of the training set by the deep tensor dictionary learning method, and obtaining the trained deep tensor dictionary;

[0031] The determining module is used for determining the sparse coding third-order matrix based on the extracted features of the test set and the trained deep tensor dictionary;

[0032] The judging module is used for judging whether the chip packaging image to be detected has defects and defect positioning according to the sparse coding third-order matrix.

[0033] The application has the following beneficial effects:

[0034] The continuous information of the image is included. The method selects a two-dimensional matrix as an atom of a three-dimensional dictionary, avoids cutting the image into vector data, and thus destroys the continuous relationship of the image in the horizontal or vertical direction. The whole image is directly taken as an input, and each element is a two-dimensional matrix, and the continuous relationship of the image in the horizontal and vertical directions is not destroyed, so that more perfect information can be extracted, and the effect is better.

[0035] The reliability of the result is improved. The idea of deep learning is combined, the sparse coding obtained at a time is further processed by three-dimensional tensor dictionary learning to obtain corresponding deep tensor dictionary and third-order sparse coding, which is equivalent to secondary feature extraction of the sparse coding. Therefore, the dictionary obtained by combining the dictionary each time has stronger feature description capability, and the accuracy of defect judgment is higher.

[0036] The abnormal positioning is realized. After obtaining the complete dictionary, the sparse coding third-order matrix corresponding to the image is actually a position representation of the image features. According to the position of the sparse coding, the error of the image block can be calculated, so that the error of the block with the largest error can be determined, and the defect positioning is realized. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 It is a schematic diagram of training the training set of the chip packaging and judging the defects and positioning of the test set of the application.

[0038] Figure 2 It is a flowchart of deep tensor dictionary learning of the application.

[0039] Figure 3 It is a structure block diagram of deep tensor dictionary learning of the application.

[0040] Figure 4 The flowchart of the deep tensor dictionary learning for locating the anomaly of the present application.

[0041] Figure 5 The structural block diagram of the chip package defect detection and positioning device in the present application.

[0042] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0043] It should be understood that the specific embodiments described herein are merely intended to explain the present application and not to limit the present application.

[0044] The chip package defect detection and positioning method provided by the embodiments of the present application is described with reference to Figure 1 , Figure 1 The flowchart of the chip package defect detection and positioning method embodiment of the present application.

[0045] In the present embodiment, the chip package defect detection and positioning method comprises the following steps:

[0046] S100-1, extracting features from the normal image tensor matrix data by PCA, and waiting for the next step processing;

[0047] S100-2, extracting features from the chip image tensor matrix data to be detected by PCA, and waiting for further processing;

[0048] S200, training the feature tensor matrix by the deep tensor dictionary learning method;

[0049] S300, obtaining the completed tensor dictionary and the third-order sparse coding matrix;

[0050] S400, inputting the image of S100-2, and obtaining the sparse coding third-order matrix by the tensor dictionary learning method;

[0051] S500, judging the error, if the error is greater than the allowable error, the image has defects, and the position of the defects in the image is given according to the non-zero element position of the sparse coding third-order matrix, if the error is less than the allowable error, the image has no defects, and the task is completed.

[0052] Further, in order to describe the flow and structure of the deep tensor dictionary learning part in more detail, the input parameters are given in the specific details: Figure 2 and Figure 3 The error threshold e, that is, the stopping criterion of each tensor dictionary training, ensures that the error reaches the allowable range.

[0053] Referring to Figure 2 , the present application relates to a flowchart of deep tensor dictionary learning, including the following contents:

[0054] S100, extracting features from normal image tensor matrix data Y by PCA, obtaining Waiting for the next step processing;

[0055] S200, input error tolerance, maximum depth layer number, tensor dictionary size parameters;

[0056] S300, for the feature tensor matrix, through K-TSVD tensor dictionary learning method;

[0057] S400, obtain three-dimensional tensor dictionary Sparse coding third-order matrix And the number of depth layers +1;

[0058] S500, judge whether the layer number reaches the maximum layer number;

[0059] S600, if the maximum layer number is not reached, the sparse coding third-order matrix As input, return to S300 for tensor dictionary learning, if the maximum layer number is reached, multiply the tensor matrix obtained by each layer to obtain the perfect tensor dictionary Task is completed.

[0060] Further, in order to ensure the number of layers of deep tensor dictionary, give the maximum layer number s, iteration number i=1,2,…,s, ensure that the expression of the final perfect dictionary is stronger.

[0061] Referring to Figure 3 , the present application relates to a structural diagram of deep tensor dictionary learning, that is, the graphic explanation of Figure 2 .

[0062] Further, according to the size of the tensor of each third-order sparse coding, the size of the next dictionary and sparse coding is determined, so the size parameters need to be given.

[0063] Referring to Figure 4 , the present application relates to a defect positioning flowchart of deep tensor dictionary learning, including the following contents:

[0064] S100, divide the to-be-tested certain image matrix data into different block matrix data Yp(j) according to certain rules, j=1,2,...,p, and wait for the next step processing;

[0065] S200, for a given j, find the corresponding part Dp(j) in the depth tensor dictionary D and the sparse coding matrix part Ap(j), and calculate the error e(j) = Yp(j)-Dp(j)*Ap(j), and j+1;

[0066] S300, judge whether j is greater than p, if yes, go to the next step, if not, return to S200;

[0067] S400, for all e(j), find the maximum one in the norm, which corresponds to the block part in the test image, that is, the defect location, and the task is completed.

[0068] Further, the flow chart of the image defect detection and positioning is obtained by Figure 4 It is explained that the matrix data of the image to be tested is divided into different block matrix data according to certain rules, and the corresponding part of the depth tensor dictionary D and the corresponding part of the sparse coding matrix A are found out, and the error is calculated according to the block, so as to determine the defect location.

[0069] In the embodiment, a chip packaging defect detection and positioning method is provided, which describes the main features of the image through a three-dimensional dictionary, strengthens the feature expression ability of the depth tensor dictionary by combining deep learning, and approximately represents the image by combining sparse coding, so as to judge whether the image is abnormal according to the error between the actual image and the approximate representation, and locate the abnormal position of the image according to the sparse coding, thereby improving the detection speed and detection accuracy of the chip packaging defect detection.

[0070] Referring to Figure 5 , Figure 5 is a structural block diagram of the first embodiment of the chip packaging defect detection and positioning device of the application.

[0071] As Figure 5 shown, the chip packaging defect detection and positioning device provided by the embodiment of the application comprises:

[0072] The preprocessing module 10 is used for PCA preprocessing of the test set and the training set of the chip packaging image;

[0073] The training module 20 is used for training the extracted features of the training set by the depth tensor dictionary learning method, and obtaining the trained depth tensor dictionary;

[0074] The determination module 30 is used for determining the sparse coding third-order matrix based on the extracted features of the test set and the trained depth tensor dictionary;

[0075] The judgment module 40 is used for judging whether the chip packaging image to be detected has defects and defect positioning according to the sparse coding third-order matrix.

[0076] Other embodiments or specific implementations of the chip package defect detection and positioning apparatus of the present application can refer to the above-mentioned method embodiments, and will not be described here again.

[0077] In addition, the embodiments of the present application also propose a storage medium, and the storage medium stores a chip package defect detection and positioning program. When the chip package defect detection and positioning program is executed by a processor, the steps of the chip package defect detection and positioning method described above are implemented. Therefore, the description will not be repeated here. In addition, the description of the beneficial effects of using the same method will also not be repeated. For technical details not disclosed in the computer-readable storage medium embodiments involved in the present application, please refer to the description of the method embodiments of the present application. For example, the program instructions can be deployed to be executed on one computing device, or executed on multiple computing devices located in one place, or executed on multiple computing devices distributed in multiple places and interconnected through a communication network.

[0078] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware. The above-mentioned program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the above-mentioned method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0079] In addition, it should be noted that the above-described device embodiments are only schematic, and the units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or distributed on multiple network units. According to actual needs, part or all of the modules can be selected to achieve the purpose of the present embodiment. In addition, the device embodiments provided by the present application in the drawings show that the connection between the modules indicates that there is a communication connection between them, which can be implemented as one or more communication buses or signal lines. Those of ordinary skill in the art can understand and implement it without creative labor.

[0080] Through the description of the above embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software necessary general hardware, of course, can also be implemented by special hardware including special integrated circuit, special CPU, special memory, special component and the like. Generally, the functions completed by the computer program can be easily realized by the corresponding hardware, and the specific hardware structure for realizing the same function can also be various, such as analog circuit, digital circuit or special circuit and the like. However, for the present application, the software program implementation is a better embodiment. Based on such understanding, the technical solutions of the present application or the part of the prior art can be embodied in the form of software product, which is stored in a readable storage medium, such as a floppy disk, a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc., including a plurality of instructions for making a computer device (which can be a personal computer, a server, or a network device, etc.) execute the method described in various embodiments of the present application.

Claims

1. A method of chip package defect detection and localization, the method comprising: The method comprises the following steps: S1: PCA preprocessing is performed on a test set and a training set of chip packaging images; S2: features extracted from the training set are trained by a deep tensor dictionary learning method to obtain a trained deep tensor dictionary; the step S2 specifically comprises: S201: Extract features of the tensor matrix data Y of the normal image by PCA to obtain A(0) Wait for the next step of processing; S202: inputting an error tolerance value, a maximum number of deep layers, and a size parameter of a tensor dictionary; S203: for a feature tensor matrix, a K-TSVD tensor dictionary learning method is used; S204, obtaining a three-dimensional tensor dictionary D(i) , a sparse coding third-order matrix A(i) and setting the depth layer number +1; S205: determining whether the number of layers reaches the maximum number of layers; S206, if the maximum number of layers is not reached, sparse coding third order matrix A(i) is obtained As input, return to S203 to carry out tensor dictionary learning; if the maximum number of layers is reached, the tensor matrix obtained in each layer is multiplied to obtain a completed tensor dictionary D = D(1)*D(2)*...*D(s) , the task is completed; S3: based on features extracted from the test set and the trained deep tensor dictionary, a sparse coding third-order matrix is determined; S4: based on the sparse coding third-order matrix, it is determined whether the chip packaging image to be detected has defects and the defect positioning.

2. The method of claim 1, wherein, The step S1 specifically comprises: S101: features of tensor matrix data of normal images in the training set are extracted by PCA, and the next step is waited for; S102: features of tensor matrix data of chip images to be detected in the test set are extracted by PCA, and the next step is waited for.

3. The method of claim 2, wherein, The step S3 specifically comprises: features of the chip images to be detected in the test set are input into the trained deep tensor dictionary, and a sparse coding third-order matrix is obtained by a tensor dictionary learning method.

4. The method of claim 1, wherein, In the step S4, whether the chip packaging image to be detected has defects is determined, specifically comprising: determining whether the error of the sparse coding third-order matrix is greater than the tolerance error, if yes, the image has defects, and the position of the defect in the image is obtained according to the non-zero element position of the sparse coding third-order matrix; if not, the image does not have defects.

5. The method of claim 4, wherein, The step of obtaining the position of the defect in the image according to the non-zero element position of the sparse coding third-order matrix specifically comprises: S401: matrix data of the chip packaging image to be tested is divided into different block matrix data Yp(j), j = 1, 2,..., p, and the next step is waited for; S402: for a given j, the corresponding part Dp(j) in the deep tensor dictionary D and the sparse coding matrix part Ap(j) are found out, the error e(j) = Yp(j)-Dp(j)*Ap(j) is calculated, and j+1 is added; S403: determining whether j is greater than p, if yes, the next step is entered, if not, returning to S402; S404: for all e(j), the maximum one in the norm is found out, which is the defect in the block part of the test image, and the task is completed.

6. A chip package defect detection and localization apparatus, characterized by, The device comprises: a preprocessing module configured to perform PCA preprocessing on a test set and a training set of chip packaging images; a training module configured to train features extracted from the training set by a deep tensor dictionary learning method to obtain a trained deep tensor dictionary; specifically comprising: Feature extraction is performed on the tensor matrix data Y of the normal image by PCA to obtain A(0) Wait for the next step of processing; inputting an error tolerance value, a maximum number of deep layers, and a size parameter of a tensor dictionary again; using a K-TSVD tensor dictionary learning method for a feature tensor matrix again; a three-dimensional tensor dictionary D(i) is obtained a sparse encoding third-order matrix A(i) and the depth layer number is +1; determining whether the number of layers reaches the maximum number of layers; if not, sparse coding third-order matrix A(i) As input, return S203 to proceed tensor dictionary learning; if the maximum number of layers is reached, the tensor matrix obtained in each layer is multiplied to obtain the perfect tensor dictionary D = D(1)*D(2)*...*D(s) , the task is completed; a determination module configured to determine a sparse coding third-order matrix based on features extracted from the test set and the trained deep tensor dictionary; a judgment module configured to determine whether a chip packaging image to be detected has defects and defect positioning based on the sparse coding third-order matrix.

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