Pixel circuit, driving method and display device

Abstract

The present invention provides a pixel circuit, a driving method, and a display device. The pixel circuit includes a light-emitting element, a driving circuit, a compensation circuit, a compensation control circuit, and a data writing circuit. The compensation circuit maintains the potential of the control terminal of the driving circuit during a hold frame included in a display cycle. The compensation control circuit controls the connection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of a scanning signal. The data writing circuit writes a data voltage to the first terminal of the driving circuit under the control of a scanning signal. The driving circuit is configured to drive the light-emitting element under the control of the potential of its control terminal. The present invention employs a compensation circuit that can maintain the potential of the control terminal of the driving circuit during the hold frame included in the display cycle. This allows the potential of the control terminal of the driving circuit to be maintained for a long time even at low frequencies, thereby improving display quality at low frequencies.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit, a driving method and a display device. Background Art

[0002] In the field of AMOLED (active matrix organic light-emitting diode) displays, with the widespread application of display products, the size of display products has increased, and the demand for thinness and battery life has required display products to save power and lower display frequencies. Currently, LTPS (low-temperature polysilicon) display products are used. Due to the characteristics of intrinsic TFT (thin-film transistor), leakage current still exists when the TFT is turned off. There is a difference in voltage when maintaining the display and refreshing for a long time, resulting in subjective observation of brightness changes and flickering in the same grayscale. The leakage current of LTPS transistors is in E -13 The lower the display frequency, the longer the hold time, the longer the leakage current, the more obvious the difference in the brightness of the light-emitting element, and the more flickering. Conventional technical means are to reduce leakage current through design and process, but there is limited room for improvement. Summary of the Invention

[0003] In one aspect, an embodiment of the present invention provides a pixel circuit including a light-emitting element, a driving circuit, a compensation circuit, a compensation control circuit, and a data writing circuit;

[0004] The compensation circuit is electrically connected to the control terminal of the driving circuit, and is used to maintain the potential of the control terminal of the driving circuit during a hold frame included in a display cycle;

[0005] The compensation control circuit is electrically connected to the scanning end, the control end of the driving circuit and the second end of the driving circuit respectively, and is used to control the communication between the control end of the driving circuit and the second end of the driving circuit under the control of the scanning signal provided by the scanning end;

[0006] The data writing circuit is electrically connected to the scanning terminal, the data line and the first terminal of the driving circuit respectively, and is used to write the data voltage provided by the data line into the first terminal of the driving circuit under the control of the scanning signal;

[0007] The driving circuit is used to drive the light emitting element under the control of the potential of the control terminal.

[0008] Optionally, the compensation circuit includes a first initialization circuit, a first control circuit, a second control circuit and a first energy storage circuit;

[0009] The first initialization circuit is electrically connected to the first reset terminal, the control terminal of the driving circuit, and the control node respectively, and is used to control the communication between the control terminal of the driving circuit and the control node under the control of a first reset signal provided by the first reset terminal;

[0010] The first control circuit is electrically connected to the first control terminal, the write node and the control node respectively, and is used to control the communication between the write node and the control node under the control of a first control signal provided by the first control terminal;

[0011] The second control circuit is electrically connected to the second control terminal, the data line and the write node respectively, and is used to provide the data voltage provided by the data line to the write node under the control of the second control signal provided by the second control terminal;

[0012] A first end of the first energy storage circuit is electrically connected to the write node, a second end of the first energy storage circuit is electrically connected to a first voltage end, and the first energy storage circuit is used to store electrical energy.

[0013] Optionally, the compensation circuit further includes a third control circuit;

[0014] The third control circuit is electrically connected to the third control terminal, the first initial voltage terminal and the control node respectively, and is used to write an initial voltage provided by the first initial voltage terminal into the control node under the control of a third control signal provided by the third control terminal.

[0015] Optionally, the first control end and the first reset end are the same control end;

[0016] The first initialization circuit includes a first transistor, and the first control circuit includes a second transistor;

[0017] The gate of the first transistor is electrically connected to the first reset terminal, the first electrode of the first transistor is electrically connected to the control node, and the second electrode of the first transistor is electrically connected to the control terminal of the driving circuit;

[0018] A gate of the second transistor is electrically connected to the first control terminal, a first electrode of the second transistor is electrically connected to the write node, and a second electrode of the second transistor is electrically connected to the control node.

[0019] Optionally, the first transistor is a p-type transistor, and the second transistor is an n-type transistor; or,

[0020] The first transistor is an n-type transistor, and the second transistor is a p-type transistor.

[0021] Optionally, the second control circuit includes a third transistor; the first energy storage circuit includes a first capacitor;

[0022] The gate of the third transistor is electrically connected to the second control terminal, the first electrode of the third transistor is electrically connected to the data line, and the second electrode of the third transistor is electrically connected to the write node;

[0023] A first end of the first capacitor is electrically connected to the write node, and a second end of the first capacitor is electrically connected to a first voltage end.

[0024] Optionally, the third control circuit includes a fourth transistor;

[0025] The gate of the fourth transistor is electrically connected to the third control terminal, the first electrode of the fourth transistor is electrically connected to the first initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the control node;

[0026] The third control terminal and the first reset terminal are the same control terminal;

[0027] The fourth transistor and the transistor included in the first initialization circuit are both p-type transistors; or the fourth transistor and the transistor included in the first initialization circuit are both n-type transistors.

[0028] Optionally, the compensation circuit includes a fourth control circuit, a fifth control circuit and a second energy storage circuit;

[0029] The first end of the second energy storage circuit is electrically connected to the control end of the driving circuit; the second end of the second energy storage circuit is electrically connected to the write node;

[0030] The fourth control circuit is electrically connected to the fourth control terminal, the first voltage terminal and the write node respectively, and is used to control the communication between the first voltage terminal and the write node under the control of a fourth control signal provided by the fourth control terminal;

[0031] The fifth control circuit is electrically connected to the second voltage terminal, the write node and the second initial voltage terminal respectively, and is used to control the connection between the write node and the second initial voltage terminal under the control of the second voltage signal provided by the second voltage terminal.

[0032] Optionally, the fourth control terminal and the scanning terminal are the same control terminal; the fourth control circuit includes a fifth transistor, and the fifth control circuit includes a sixth transistor;

[0033] The gate of the fifth transistor is electrically connected to the scan terminal, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the write node;

[0034] The gate of the sixth transistor is electrically connected to the second voltage terminal, the first electrode of the sixth transistor is electrically connected to the write node, and the second electrode of the sixth transistor is electrically connected to the second initial voltage terminal.

[0035] Optionally, the first voltage terminal is a first high voltage terminal, the second voltage terminal is a second high voltage terminal, and the sixth transistor is a p-type transistor;

[0036] The fifth transistor and the transistor included in the data writing circuit are both p-type transistors; or the fifth transistor and the transistor included in the data writing circuit are both n-type transistors.

[0037] Optionally, the second control end and the scanning end are the same control end;

[0038] The compensation control circuit includes a seventh transistor, the data writing circuit includes an eighth transistor; the driving circuit includes a driving transistor;

[0039] The gate of the seventh transistor is electrically connected to the scanning end, the first electrode of the seventh transistor is electrically connected to the gate of the driving transistor, and the second electrode of the seventh transistor is electrically connected to the second electrode of the driving transistor;

[0040] A gate of the eighth transistor is electrically connected to the scanning end, a first electrode of the eighth transistor is electrically connected to the data line, and a second electrode of the eighth transistor is electrically connected to the first electrode of the driving transistor.

[0041] Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a first light emitting control circuit, a second light emitting control circuit, and a second initialization circuit;

[0042] The first light-emitting control circuit is electrically connected to the light-emitting control line, the first voltage terminal, and the first terminal of the driving circuit, respectively, and is configured to control the communication between the first voltage terminal and the first terminal of the driving circuit under the control of the light-emitting control signal provided by the light-emitting control line;

[0043] The second light emitting control circuit is electrically connected to the light emitting control line, the second end of the drive circuit, and the first electrode of the light emitting element, respectively, and is used to control the second end of the drive circuit to be connected to the first electrode of the light emitting element under the control of the light emitting control signal;

[0044] The second initialization circuit is electrically connected to the second reset terminal, the third initial voltage terminal and the first electrode of the light-emitting element respectively, and is configured to provide a third initial voltage provided by the third initial voltage terminal to the first electrode of the light-emitting element under the control of a second reset signal provided by the second reset terminal;

[0045] The second electrode of the light emitting element is electrically connected to the third voltage terminal.

[0046] Optionally, the driving circuit includes a driving transistor;

[0047] The first light emitting control circuit includes a ninth transistor, the second light emitting control circuit includes a tenth transistor, and the second initialization circuit includes an eleventh transistor;

[0048] The gate of the ninth transistor is electrically connected to the light emitting control line, the first electrode of the ninth transistor is electrically connected to the first voltage terminal, and the second electrode of the ninth transistor is connected to the first electrode of the driving transistor;

[0049] The gate of the tenth transistor is electrically connected to the light emitting control line, the first electrode of the tenth transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the tenth transistor is electrically connected to the first electrode of the light emitting element;

[0050] The gate of the eleventh transistor is electrically connected to the second reset terminal, the first electrode of the eleventh transistor is electrically connected to the third initial voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the first electrode of the light emitting element.

[0051] In a second aspect, an embodiment of the present invention provides a driving method, which is applied to the above-mentioned pixel circuit, wherein the display period includes a hold frame; the driving method includes:

[0052] In the holding frame, the compensation circuit maintains the potential of the control terminal of the driving circuit.

[0053] In a third aspect, an embodiment of the present invention provides a display device, characterized in that it includes the above-mentioned pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 is a structural diagram of a pixel circuit according to an embodiment of the present invention;

[0055] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0056] Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0057] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0058] Figure 5 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0059] Figure 6 yes Figure 5 An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0060] Figure 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0061] Figure 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0062] Figure 9 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0063] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0064] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0065] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the gate electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0066] The pixel circuit described in the embodiment of the present invention includes a light-emitting element, a driving circuit, a compensation circuit, a compensation control circuit and a data writing circuit;

[0067] The compensation circuit is electrically connected to the control terminal of the driving circuit, and is used to maintain the potential of the control terminal of the driving circuit during a hold frame included in a display cycle;

[0068] The compensation control circuit is electrically connected to the scanning end, the control end of the driving circuit and the second end of the driving circuit respectively, and is used to control the communication between the control end of the driving circuit and the second end of the driving circuit under the control of the scanning signal provided by the scanning end;

[0069] The data writing circuit is electrically connected to the scanning terminal, the data line and the first terminal of the driving circuit respectively, and is used to write the data voltage provided by the data line into the first terminal of the driving circuit under the control of the scanning signal;

[0070] The driving circuit is used to drive the light emitting element under the control of the potential of the control terminal.

[0071] The pixel circuit described in the embodiment of the present invention adopts a compensation circuit. The compensation circuit can maintain the potential of the control end of the driving circuit during the holding frame included in the display cycle, so that the potential of the control end of the driving circuit can be maintained for a long time at low frequency, thereby improving the display quality at low frequency, achieving low frequency and low power consumption, and increasing battery life, thereby increasing application scenarios.

[0072] The embodiment of the present invention does not increase the process flow and difficulty, and the cost does not change, and can achieve the improvement of low-frequency image quality capabilities of display products.

[0073] In at least one embodiment of the present invention, the compensation circuit maintains the potential of the control end of the driving circuit in the holding frame, which may refer to: in the holding frame, the compensation circuit maintains the potential of the control end of the driving circuit, so that the absolute value of the difference between the potential of the control end of the driving circuit in the holding frame and the potential of the control end of the driving circuit in the refresh frame is less than a predetermined voltage difference, so that the potential of the control end of the driving circuit in the holding frame is approximately the same as the potential of the control end of the driving circuit in the refresh frame; the predetermined voltage difference may be, for example, less than or equal to 0.1V, but is not limited thereto.

[0074] In a specific implementation, the pixel circuit may include a compensation control circuit and a data writing circuit. The compensation control circuit controls the connection between the control end of the driving circuit and the second end of the driving circuit under the control of the scanning signal. The data writing circuit writes the data voltage to the first end of the driving circuit under the control of the scanning signal.

[0075] like Figure 1 As shown, the pixel circuit according to the embodiment of the present invention includes a light emitting element EL, a driving circuit 10, a compensation circuit 11, a compensation control circuit 41 and a data writing circuit 42;

[0076] The compensation circuit 11 is electrically connected to the control terminal of the driving circuit 10 and is used to maintain the potential of the control terminal of the driving circuit 10 during the hold frame included in the display cycle;

[0077] The compensation control circuit 41 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 10, and the second terminal of the driving circuit 10, respectively, and is used to control the communication between the control terminal of the driving circuit 10 and the second terminal of the driving circuit 10 under the control of the scanning signal provided by the scanning terminal G1;

[0078] The data writing circuit 42 is electrically connected to the scan terminal G1, the data line Data and the first terminal of the driving circuit 10 respectively, and is used to write the data voltage Vdata provided by the data line Data into the first terminal of the driving circuit 10 under the control of the scan signal;

[0079] The driving circuit 10 is configured to drive the light emitting element EL under the control of the potential of the control terminal thereof.

[0080] In the related art, when the p-type transistor is turned off, the leakage current is E -13 Level, the leakage current Ioff can be equal to K(W / L)×(Vgs-Vth) 2 , Vth is the threshold voltage, Vgs is the gate-source voltage, and when the p-type transistor is turned off, the current value of Ioff changes as the potential of the gate of the transistor increases.

[0081] In related art, with the demand for low power consumption, based on a display resolution of 1080×2340, when the display frequency is 120Hz and 30Hz, the refresh frame duration and the hold frame duration included in one frame are as follows:

[0082] When the display frequency is 120Hz, the refresh frame duration is (1 / 120 / (2340+16))s, the refresh frame duration is 3.537us, and the hold frame duration is 8329.796us;

[0083] When the display frequency is 30 Hz, the refresh frame duration is (1 / 30 / (2340+16))s, the refresh frame duration is 14.148us, and the hold frame duration is 33319.185us.

[0084] According to preliminary estimates, when the display frequency is 30Hz, the time it takes to maintain a frame is four times the time it takes to maintain a frame when the display frequency is 120Hz. Assuming the same leakage current, when the display frequency is 30Hz, the leakage charge is four times the leakage charge when the display frequency is 120Hz. As a result, when maintaining the frame, the voltage at the control end of the drive circuit drops a lot, resulting in different drive currents and different display brightness of the light-emitting elements. When the display frequency is low, obvious differences can be felt, resulting in flickering defects.

[0085] In at least one embodiment of the present invention, the compensation circuit includes a first initialization circuit, a first control circuit, a second control circuit, and a first energy storage circuit;

[0086] The first initialization circuit is electrically connected to the first reset terminal, the control terminal of the driving circuit, and the control node respectively, and is used to control the communication between the control terminal of the driving circuit and the control node under the control of a first reset signal provided by the first reset terminal;

[0087] The first control circuit is electrically connected to the first control terminal, the write node and the control node respectively, and is used to control the communication between the write node and the control node under the control of a first control signal provided by the first control terminal;

[0088] The second control circuit is electrically connected to the second control terminal, the data line and the write node respectively, and is used to provide the data voltage provided by the data line to the write node under the control of the second control signal provided by the second control terminal;

[0089] A first end of the first energy storage circuit is electrically connected to the write node, a second end of the first energy storage circuit is electrically connected to a first voltage end, and the first energy storage circuit is used to store electrical energy.

[0090] In a specific implementation, the compensation circuit may include a first initialization circuit, a first control circuit, a second control circuit and a first energy storage circuit. The first initialization circuit controls the connection between the control end of the driving circuit and the control node under the control of a first reset signal. The first control circuit controls the connection between the write node and the control node under the control of a first control signal. The second control circuit provides a data voltage to the write node under the control of a second control signal.

[0091] like Figure 2 As shown, in Figure 1 Based on the embodiment of the pixel circuit shown, the compensation circuit includes a first initialization circuit 21, a first control circuit 22, a second control circuit 23 and a first energy storage circuit 24;

[0092] The first initialization circuit 21 is electrically connected to the first reset terminal R1, the control terminal of the driving circuit 10, and the control node N0, respectively, and is used to control the communication between the control terminal of the driving circuit 10 and the control node N0 under the control of the first reset signal provided by the first reset terminal R1;

[0093] The first control circuit 22 is electrically connected to the first control terminal Ct1, the write node Vc and the control node N0, respectively, and is configured to control the communication between the write node Vc and the control node N0 under the control of a first control signal provided by the first control terminal Ct1;

[0094] The second control circuit 23 is electrically connected to the second control terminal Ct2, the data line Data and the write node Vc, and is configured to provide the data voltage Vdata provided by the data line Data to the write node Vc under the control of the second control signal provided by the second control terminal Ct2;

[0095] A first end of the first energy storage circuit 24 is electrically connected to the write node Vc, and a second end of the first energy storage circuit 24 is electrically connected to the first voltage terminal V1. The first energy storage circuit 24 is used to store electrical energy.

[0096] In at least one embodiment of the present invention, the first voltage terminal may be a first high voltage terminal, the first control terminal and the first reset terminal may be the same control terminal, and the second control terminal and the scan terminal may be the same control terminal, but the present invention is not limited thereto.

[0097] Optionally, the compensation circuit further includes a third control circuit;

[0098] The third control circuit is electrically connected to the third control terminal, the first initial voltage terminal and the control node respectively, and is used to write an initial voltage provided by the first initial voltage terminal into the control node under the control of a third control signal provided by the third control terminal.

[0099] In a specific implementation, the pixel circuit may further include a third control circuit, which writes the first initial voltage into the control node under the control of a third control signal.

[0100] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the pixel circuit shown, the compensation circuit may further include a third control circuit 31;

[0101] The third control circuit 31 is electrically connected to the third control terminal Ct3, the first initial voltage terminal I1 and the control node N0 respectively, and is used to write an initial voltage Vinit1 provided by the first initial voltage terminal I1 into the control node N0 under the control of a third control signal provided by the third control terminal Ct3.

[0102] In at least one embodiment of the present invention, the third control terminal and the first reset terminal may be the same control terminal, but the present invention is not limited thereto.

[0103] Optionally, the first control end and the first reset end are the same control end;

[0104] The first initialization circuit includes a first transistor, and the first control circuit includes a second transistor;

[0105] The gate of the first transistor is electrically connected to the first reset terminal, the first electrode of the first transistor is electrically connected to the control node, and the second electrode of the first transistor is electrically connected to the control terminal of the driving circuit;

[0106] A gate of the second transistor is electrically connected to the first control terminal, a first electrode of the second transistor is electrically connected to the write node, and a second electrode of the second transistor is electrically connected to the control node.

[0107] Optionally, the first transistor is a p-type transistor, and the second transistor is an n-type transistor; or,

[0108] The first transistor is an n-type transistor, and the second transistor is a p-type transistor.

[0109] Optionally, the second control circuit includes a third transistor; the first energy storage circuit includes a first capacitor;

[0110] The gate of the third transistor is electrically connected to the second control terminal, the first electrode of the third transistor is electrically connected to the data line, and the second electrode of the third transistor is electrically connected to the write node;

[0111] A first end of the first capacitor is electrically connected to the write node, and a second end of the first capacitor is electrically connected to a first voltage end.

[0112] Optionally, the third control circuit includes a fourth transistor;

[0113] The gate of the fourth transistor is electrically connected to the third control terminal, the first electrode of the fourth transistor is electrically connected to the first initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the control node.

[0114] In at least one embodiment of the present invention, the third control terminal and the first reset terminal are the same control terminal;

[0115] The fourth transistor and the transistor included in the first initialization circuit are both p-type transistors; or the fourth transistor and the transistor included in the first initialization circuit are both n-type transistors.

[0116] Optionally, the second control end and the scanning end are the same control end;

[0117] The transistors included in the second control circuit, the transistors included in the compensation control circuit, and the transistors included in the data writing circuit are all p-type transistors; or,

[0118] The transistors included in the second control circuit, the transistors included in the compensation control circuit, and the transistors included in the data writing circuit are all n-type transistors.

[0119] Optionally, the compensation control circuit includes a seventh transistor, the data writing circuit includes an eighth transistor; and the driving circuit includes a driving transistor;

[0120] The gate of the seventh transistor is electrically connected to the scanning end, the first electrode of the seventh transistor is electrically connected to the gate of the driving transistor, and the second electrode of the seventh transistor is electrically connected to the second electrode of the driving transistor;

[0121] A gate of the eighth transistor is electrically connected to the scanning end, a first electrode of the eighth transistor is electrically connected to the data line, and a second electrode of the eighth transistor is electrically connected to the first electrode of the driving transistor.

[0122] The pixel circuit according to at least one embodiment of the present invention further includes a first light emitting control circuit, a second light emitting control circuit, and a second initialization circuit;

[0123] The first light-emitting control circuit is electrically connected to the light-emitting control line, the first voltage terminal, and the first terminal of the driving circuit, respectively, and is configured to control the communication between the first voltage terminal and the first terminal of the driving circuit under the control of the light-emitting control signal provided by the light-emitting control line;

[0124] The second light emitting control circuit is electrically connected to the light emitting control line, the second end of the drive circuit, and the first electrode of the light emitting element, respectively, and is used to control the second end of the drive circuit to be connected to the first electrode of the light emitting element under the control of the light emitting control signal;

[0125] The second initialization circuit is electrically connected to the second reset terminal, the third initial voltage terminal and the first electrode of the light-emitting element respectively, and is configured to provide a third initial voltage provided by the third initial voltage terminal to the first electrode of the light-emitting element under the control of a second reset signal provided by the second reset terminal;

[0126] The second electrode of the light emitting element is electrically connected to the third voltage terminal.

[0127] In a specific implementation, the pixel circuit may include a first light-emitting control circuit, a second light-emitting control circuit and a second initialization circuit. The first light-emitting control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the light-emitting control signal. The second light-emitting control circuit controls the connection between the second terminal of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal. The second initialization circuit provides a third initial voltage to the first pole of the light-emitting element under the control of the second reset signal.

[0128] In at least one embodiment of the present invention, the third voltage terminal may be a low voltage terminal.

[0129] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a first light emitting control circuit 51, a second light emitting control circuit 52, a second initialization circuit 53 and a second energy storage circuit 54;

[0130] The first light emitting control circuit 51 is electrically connected to the light emitting control line EM, the first voltage terminal V1, and the first terminal of the driving circuit 10, respectively, and is used to control the communication between the first voltage terminal V1 and the second terminal of the driving circuit 10 under the control of the light emitting control signal provided by the light emitting control line EM;

[0131] The second light emitting control circuit 52 is electrically connected to the light emitting control line EM, the second end of the driving circuit 10, and the first electrode of the light emitting element EL, respectively, and is used to control the second end of the driving circuit 10 to communicate with the first electrode of the light emitting element EL under the control of the light emitting control signal;

[0132] The second initialization circuit 53 is electrically connected to the second reset terminal R2, the third initial voltage terminal I3 and the first electrode of the light-emitting element EL, respectively, and is configured to provide a third initial voltage Vinit3 provided by the third initial voltage terminal I3 to the first electrode of the light-emitting element EL under the control of the second reset signal provided by the second reset terminal R2;

[0133] A first end of the second energy storage circuit 54 is electrically connected to the control end of the driving circuit 10 , and a second end of the second energy storage circuit 54 is electrically connected to the first voltage end V1 ;

[0134] The second electrode of the light emitting element EL is electrically connected to the third voltage terminal V3.

[0135] Optionally, the driving circuit includes a driving transistor;

[0136] The first light emitting control circuit includes a ninth transistor, the second light emitting control circuit includes a tenth transistor, and the second initialization circuit includes an eleventh transistor;

[0137] The gate of the ninth transistor is electrically connected to the light emitting control line, the first electrode of the ninth transistor is electrically connected to the first voltage terminal, and the second electrode of the ninth transistor is connected to the first electrode of the driving transistor;

[0138] The gate of the tenth transistor is electrically connected to the light emitting control line, the first electrode of the tenth transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the tenth transistor is electrically connected to the first electrode of the light emitting element;

[0139] The gate of the eleventh transistor is electrically connected to the second reset terminal, the first electrode of the eleventh transistor is electrically connected to the third initial voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the first electrode of the light emitting element.

[0140] like Figure 5 As shown, in Figure 4 Based on at least one embodiment of the pixel circuit shown, the first initialization circuit includes a first transistor T1, the first control circuit includes a second transistor T2; the driving circuit includes a driving transistor DT;

[0141] The gate of the first transistor T1 is electrically connected to the first reset terminal R1, the source of the first transistor T1 is electrically connected to the control node N0, and the drain of the first transistor T1 is electrically connected to the gate of the driving transistor DT;

[0142] The gate of the second transistor T2 is electrically connected to the first reset terminal R1, the source of the second transistor T2 is electrically connected to the write node Vc, and the drain of the second transistor T2 is electrically connected to the control node N0;

[0143] The second control circuit includes a third transistor T3; the first energy storage circuit includes a first capacitor C1;

[0144] The gate of the third transistor T3 is electrically connected to the scan terminal G1, the source of the third transistor T3 is electrically connected to the data line Data, and the drain of the third transistor T3 is electrically connected to the write node Vc;

[0145] A first end of the first capacitor C1 is electrically connected to the write node Vc, and a second end of the first capacitor C1 is electrically connected to a first high voltage terminal VDD;

[0146] The third control circuit includes a fourth transistor T4;

[0147] The gate of the fourth transistor T4 is electrically connected to the first reset terminal R1, the source of the fourth transistor T4 is electrically connected to the first initial voltage terminal I1, and the drain of the fourth transistor T4 is electrically connected to the control node N0; the first initial voltage terminal I1 is used to provide a first initial voltage Vinit1;

[0148] The compensation control circuit includes a seventh transistor T7, and the data writing circuit includes an eighth transistor T8;

[0149] The gate of the seventh transistor T7 is electrically connected to the scanning terminal G1, the source of the seventh transistor T7 is electrically connected to the gate of the driving transistor DT, and the drain of the seventh transistor T7 is electrically connected to the drain of the driving transistor DT;

[0150] The gate of the eighth transistor T8 is electrically connected to the scanning terminal G1, the first electrode of the eighth transistor T8 is electrically connected to the data line Data, and the drain of the eighth transistor T8 is electrically connected to the source of the driving transistor DT;

[0151] The first light emitting control circuit includes a ninth transistor T9, the second light emitting control circuit includes a tenth transistor T10, and the second initialization circuit includes an eleventh transistor T11; the second energy storage circuit includes a second capacitor C2; and the light emitting element is an organic light emitting diode O1;

[0152] The gate of the ninth transistor T9 is electrically connected to the light emitting control line EM, the source of the ninth transistor T9 is electrically connected to the first high voltage terminal VDD, and the drain of the ninth transistor T9 is connected to the source of the driving transistor DT;

[0153] The gate of the tenth transistor T10 is electrically connected to the light emitting control line EM, the source of the tenth transistor T10 is electrically connected to the drain of the driving transistor DT, and the drain of the tenth transistor T10 is electrically connected to the anode of the organic light emitting diode O1;

[0154] The gate of the eleventh transistor T11 is electrically connected to the second reset terminal R2, the source of the eleventh transistor T11 is electrically connected to the third initial voltage terminal I3, the drain of the eleventh transistor T11 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal VSS;

[0155] A first end of the second capacitor C2 is electrically connected to the gate of the driving transistor DT, and a second end of the second capacitor C2 is electrically connected to the first high voltage terminal VDD.

[0156] exist Figure 5 In at least one embodiment of the pixel circuit shown, T2 is an n-type transistor, and all transistors except T2 are p-type transistors, but the present invention is not limited thereto.

[0157] In at least one embodiment of the present invention, the voltage value of the first high voltage signal provided by VDD can be greater than or equal to 4V and less than or equal to 5V. For example, the voltage value of the first high voltage signal can be 4.6V, the voltage value of the data voltage Vdata can be greater than or equal to 2V and less than or equal to 7V, and the voltage value of Vinit1 can be greater than or equal to -3.3V and less than or equal to -3V, but the present invention is not limited thereto.

[0158] like Figure 6 As shown, the present invention Figure 5When at least one embodiment of the pixel circuit shown is in operation, a display cycle may include a refresh frame and a hold frame S2 that are arranged in sequence;

[0159] The refresh frame may include a reset phase S11, a data writing phase S12 and a light emitting phase S13 which are arranged in sequence;

[0160] In the reset phase S11, EM outputs a high voltage signal, R1 outputs a low voltage signal, G1 provides a high voltage signal, R2 provides a high voltage signal, T1 is turned on, T4 is turned on, and T2 is turned off, so as to write the first initial voltage Vinit1 provided by I1 into the gate of DT;

[0161] In the data writing phase S12, EM provides a high voltage signal, R1 provides a high voltage signal, G1 provides a low voltage signal, Data provides a data voltage Vdata, R2 provides a low voltage signal, T3 is turned on, T7 and T8 are turned on to write Vdata into the source of DT, control the connection between the gate of DT and the drain of DT, and control the connection between the data line Data and Vc; T2 is turned on; T1 is turned off;

[0162] At the beginning of the data writing phase S12, DT is turned on and C2 is charged through Vdata to increase the potential of the gate of DT until the potential of the gate of DT becomes Vdata+Vth. DT is then turned off and charging stops; Vth is the threshold voltage of DT.

[0163] In the light-emitting stage S13, EM provides a low voltage signal, R1 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a high voltage signal, T9 and T10 are turned on, DT drives O1 to emit light, and at this time the gate-source voltage of DT is Vdata+Vth-VDD, and the light-emitting current of O1 is independent of Vth;

[0164] In the holding frame S2, EM provides a low voltage signal, R1 provides a high voltage signal, G1 provides a high voltage signal, R2 provides a high voltage signal, T2 is turned on, and the control Vc and N0 are connected; at this time, the potential of N0 is approximately equal to Vdata-Vth3-Vth2, where Vth3 is the threshold voltage of T3, Vth2 is the threshold voltage of T2, the potential of N0 is not much different from the gate potential of DT, the source potential of T1 is not much different from the drain potential of T1, the leakage current of T1 is reduced, and the gate potential of DT can be maintained for a long time at low frequency, thereby ensuring the display quality at low frequency.

[0165] The present invention Figure 5 The pixel circuit shown can make the voltage difference between the source of T1 and the drain of T1 almost zero during the hold frame.

[0166] In at least one embodiment of the present invention, the compensation circuit includes a fourth control circuit, a fifth control circuit, and a second energy storage circuit;

[0167] The first end of the second energy storage circuit is electrically connected to the control end of the driving circuit; the second end of the second energy storage circuit is electrically connected to the write node;

[0168] The fourth control circuit is electrically connected to the fourth control terminal, the first voltage terminal and the write node respectively, and is used to control the communication between the first voltage terminal and the write node under the control of a fourth control signal provided by the fourth control terminal;

[0169] The fifth control circuit is electrically connected to the second voltage terminal, the write node and the second initial voltage terminal respectively, and is used to control the connection between the write node and the second initial voltage terminal under the control of the second voltage signal provided by the second voltage terminal.

[0170] In a specific implementation, the compensation circuit may include a fourth control circuit, a fifth control circuit and a second energy storage circuit. The fourth control circuit controls the connection between the first voltage terminal and the write node under the control of a fourth control signal provided by the fourth control terminal. The fifth control circuit controls the connection between the write node and the second initial voltage terminal under the control of the second voltage signal.

[0171] like Figure 7 As shown, in Figure 1 Based on the embodiment of the pixel circuit shown, the compensation circuit includes a fourth control circuit 81, a fifth control circuit 82 and a second energy storage circuit 54;

[0172] A first end of the second energy storage circuit 54 is electrically connected to the control end of the driving circuit 10; a second end of the second energy storage circuit 54 is electrically connected to the write node Vc;

[0173] The fourth control circuit 81 is electrically connected to the fourth control terminal Ct4, the first voltage terminal V1 and the write node Vc, and is used to control the communication between the first voltage terminal V1 and the write node Vc under the control of a fourth control signal provided by the fourth control terminal Ct4;

[0174] The fifth control circuit 82 is electrically connected to the second voltage terminal V2, the write node Vc and the second initial voltage terminal I2 respectively, and is used to control the connection between the write node Vc and the second initial voltage terminal I2 under the control of the second voltage signal provided by the second voltage terminal V2.

[0175] In at least one embodiment of the present invention, the first voltage terminal may be a first high voltage terminal, the second voltage terminal may be a second high voltage terminal, and the second initial voltage terminal is used to provide a second initial voltage Vinit2.

[0176] Optionally, the voltage value of the second high voltage signal provided by the second high voltage terminal may be greater than the voltage value of the first high voltage signal provided by the first high voltage terminal; for example, the voltage value of the first high voltage signal may be greater than or equal to 4V and less than or equal to 5V, and the voltage value of the second high voltage signal may be greater than or equal to 7.7V and less than or equal to 8V;

[0177] The voltage value of the second initial voltage Vinit2 may be greater than the voltage value of the first high voltage signal. For example, the voltage value of the second initial voltage Vinit2 may be greater than 4.6V, but is not limited thereto.

[0178] Optionally, the fourth control terminal and the scanning terminal are the same control terminal; the fourth control circuit includes a fifth transistor, and the fifth control circuit includes a sixth transistor;

[0179] The gate of the fifth transistor is electrically connected to the scan terminal, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the write node;

[0180] The gate of the sixth transistor is electrically connected to the second voltage terminal, the first electrode of the sixth transistor is electrically connected to the write node, and the second electrode of the sixth transistor is electrically connected to the second initial voltage terminal.

[0181] Optionally, the first voltage terminal is a first high voltage terminal, the second voltage terminal is a second high voltage terminal, and the sixth transistor is a p-type transistor;

[0182] The fifth transistor and the transistor included in the data writing circuit are both p-type transistors; or the fifth transistor and the transistor included in the data writing circuit are both n-type transistors.

[0183] like Figure 8 As shown, in Figure 7 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a first light emitting control circuit 51, a second light emitting control circuit 52, a second initialization circuit 53 and a first initialization circuit 21;

[0184] The first initialization circuit 21 is electrically connected to the first reset terminal R1, the control terminal of the driving circuit 10, and the control node N0, respectively, and is used to control the communication between the control terminal of the driving circuit 10 and the control node N0 under the control of the first reset signal provided by the first reset terminal R1;

[0185] The first light emitting control circuit 51 is electrically connected to the light emitting control line EM, the first voltage terminal V1, and the first terminal of the driving circuit 10, respectively, and is used to control the communication between the first voltage terminal V1 and the second terminal of the driving circuit 10 under the control of the light emitting control signal provided by the light emitting control line EM;

[0186] The second light emitting control circuit 52 is electrically connected to the light emitting control line EM, the second end of the driving circuit 10, and the first electrode of the light emitting element EL, respectively, and is used to control the second end of the driving circuit 10 to communicate with the first electrode of the light emitting element EL under the control of the light emitting control signal;

[0187] The second initialization circuit 53 is electrically connected to the second reset terminal R2, the third initial voltage terminal I3 and the first electrode of the light-emitting element EL, respectively, and is configured to provide a third initial voltage Vinit3 provided by the third initial voltage terminal I3 to the first electrode of the light-emitting element EL under the control of the second reset signal provided by the second reset terminal R2;

[0188] The second electrode of the light emitting element EL is electrically connected to the third voltage terminal V3.

[0189] like Figure 9 As shown, in Figure 8 Based on at least one embodiment of the pixel circuit shown, the first initialization circuit includes a first transistor; the fourth control circuit includes a fifth transistor T5; and the fifth control circuit includes a sixth transistor T6;

[0190] The gate of the first transistor T1 is electrically connected to the first reset terminal R1, the source of the first transistor T1 is electrically connected to the first initial voltage terminal I1, and the drain of the first transistor T1 is electrically connected to the gate of the driving transistor DT; the first initial voltage terminal I1 is used to provide a first initial voltage Vinit1;

[0191] The gate of the fifth transistor T5 is electrically connected to the scanning terminal G1, the source of the fifth transistor T5 is electrically connected to the first high voltage terminal VDD, and the drain of the fifth transistor T5 is electrically connected to the write node Vc;

[0192] The gate of the sixth transistor T6 is electrically connected to the second high voltage terminal VGH, the source of the sixth transistor T6 is electrically connected to the write node Vc, and the drain of the sixth transistor T6 is electrically connected to the second initial voltage terminal I2;

[0193] The compensation control circuit includes a seventh transistor T7, and the data writing circuit includes an eighth transistor T8;

[0194] The gate of the seventh transistor T7 is electrically connected to the scanning terminal G1, the source of the seventh transistor T7 is electrically connected to the gate of the driving transistor DT, and the drain of the seventh transistor T7 is electrically connected to the drain of the driving transistor DT;

[0195] The gate of the eighth transistor T8 is electrically connected to the scanning terminal G1, the first electrode of the eighth transistor T8 is electrically connected to the data line Data, and the drain of the eighth transistor T8 is electrically connected to the source of the driving transistor DT;

[0196] The first light emitting control circuit includes a ninth transistor T9, the second light emitting control circuit includes a tenth transistor T10, and the second initialization circuit includes an eleventh transistor T11; the second energy storage circuit includes a second capacitor C2; and the light emitting element is an organic light emitting diode O1;

[0197] The gate of the ninth transistor T9 is electrically connected to the light emitting control line EM, the source of the ninth transistor T9 is electrically connected to the first high voltage terminal VDD, and the drain of the ninth transistor T9 is connected to the source of the driving transistor DT;

[0198] The gate of the tenth transistor T10 is electrically connected to the light emitting control line EM, the source of the tenth transistor T10 is electrically connected to the drain of the driving transistor DT, and the drain of the tenth transistor T10 is electrically connected to the anode of the organic light emitting diode O1;

[0199] The gate of the eleventh transistor T11 is electrically connected to the second reset terminal R2, the source of the eleventh transistor T11 is electrically connected to the third initial voltage terminal I3, the drain of the eleventh transistor T11 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal VSS;

[0200] A first end of the second capacitor C2 is electrically connected to the gate of the driving transistor DT, and a second end of the second capacitor C2 is electrically connected to the writing node Vc.

[0201] exist Figure 9 In at least one embodiment of the pixel circuit shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0202] The present invention Figure 9 At least one embodiment of the pixel circuit shown uses T5 and T6 , and the width-to-length ratio of T5 and the width-to-length ratio of T6 can be selected based on the width-to-length ratio of T1 and the width-to-length ratio of T7 .

[0203] The present invention Figure 9The compensation method of at least one embodiment of the pixel circuit shown is to compensate for the lost charge by compensating the potential of the second end of the second capacitor C2 through the leakage current Ioff of the compensation circuit. Although the charge stored in the second capacitor C2 is reduced, the potential of the first end of C2 (that is, the potential of the gate of DT) does not change much.

[0204] The present invention Figure 9 In at least one embodiment of the pixel circuit shown, when in operation, the gate of T5 is electrically connected to the scanning terminal G1 to synchronize the pixel turn-on timing. When G1 provides a low voltage signal, Vc is connected to VDD.

[0205] When G1 provides a high voltage signal, T5 is turned off and is in the stage of generating leakage current;

[0206] The gate of T6 is electrically connected to VGH, and T6 is always in the off state. The leakage current of T6 affects the potential of Vc.

[0207] The drain of T6 is electrically connected to the second initial voltage terminal I2. The voltage value of the second initial voltage Vinit2 provided by the second initial voltage terminal I2 is greater than the voltage value of the first high voltage signal. During the cut-off time of T5, the potential of Vc continues to increase with the influence of the leakage current Ioff of T5. In the holding frame, when Ioff6-Ioff5 is approximately equal to Ioff1+Ioff7, the potential of the gate of DT can be maintained; wherein Ioff6 is the leakage current of T6, Ioff5 is the leakage current of T5, Ioff1 is the leakage current of T1, and Ioff7 is the leakage current of T7.

[0208] The present invention Figure 9 When at least one embodiment of the pixel circuit shown is in operation, no matter how the display frequency changes, the potential of the gate of DT is compensated by adopting T6, and the change in the potential of the gate of DT is reduced. At low frequencies, the brightness change caused by the voltage difference due to leakage will not be observable to the naked eye, effectively avoiding defects. LTPS (low-temperature polycrystalline silicon) devices can also display at low frequencies (the display frequency can be as low as 30 Hz, or even lower). In specific implementation, the voltage value of Vinit2 can be set to different voltage values according to different display frequencies to better match the requirements of the display panel.

[0209] In the related art, when Figure 9 When at least one embodiment of the pixel circuit shown does not include T5 and T6, when the potential of the gate of DT is greater than the potential of the drain of DT, the leakage current of the gate of DT may be Ioff-1; when the potential of the gate of DT is less than the potential of the drain of DT, the leakage current of the gate of DT may be Ioff-2.

[0210] Ioff-1=K×(W1 / L1)×((Vgh-Vg)-Vth1) 2 +K×((W7 / L7)×(Vgh-Vd)

[0211] -Vth7) 2 ;

[0212] Ioff-2=K×(W1 / L1)×((Vgh-Vg)-Vth1) 2 -K×((W7 / L7)×(Vgh-Vd)

[0213] -Vth7) 2 ;

[0214] Among them, K is the current coefficient, K is a fixed value, W1 / L1 is the width-to-length ratio of T1, W7 / L7 is the width-to-length ratio of T7, Vth1 is the threshold voltage of T1, Vth7 is the threshold voltage of T7, Vg is the potential of the gate of DT, Vd is the potential of the drain of DT, Vgh is the high voltage value of the high voltage signal provided by R1, and Vgh is also the high voltage value of the high voltage signal provided by G1.

[0215] The driving method according to an embodiment of the present invention is applied to the above-mentioned pixel circuit, wherein the display period includes maintaining a frame; the driving method includes:

[0216] In the holding frame, the compensation circuit maintains the potential of the control terminal of the driving circuit.

[0217] The display device according to the embodiment of the present invention includes the above-mentioned pixel circuit.

[0218] The display touch device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or the like.

[0219] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that: It includes a light-emitting element, a driving circuit, a compensation circuit, a compensation control circuit and a data writing circuit; The compensation circuit is electrically connected to the control terminal of the driving circuit, and is used to maintain the potential of the control terminal of the driving circuit during a hold frame included in a display cycle; The compensation control circuit is electrically connected to the scanning end, the control end of the driving circuit and the second end of the driving circuit respectively, and is used to control the communication between the control end of the driving circuit and the second end of the driving circuit under the control of the scanning signal provided by the scanning end; The data writing circuit is electrically connected to the scanning terminal, the data line and the first terminal of the driving circuit respectively, and is used to write the data voltage provided by the data line into the first terminal of the driving circuit under the control of the scanning signal; The driving circuit is used to drive the light emitting element under the control of the potential of the control terminal; The compensation circuit includes a first initialization circuit, a first control circuit, a second control circuit and a first energy storage circuit; The first initialization circuit is electrically connected to the first reset terminal, the control terminal of the driving circuit, and the control node respectively, and is used to control the communication between the control terminal of the driving circuit and the control node under the control of a first reset signal provided by the first reset terminal; The first control circuit is electrically connected to the first control terminal, the write node and the control node respectively, and is used to control the communication between the write node and the control node under the control of a first control signal provided by the first control terminal; The second control circuit is electrically connected to the second control terminal, the data line and the write node respectively, and is used to provide the data voltage provided by the data line to the write node under the control of the second control signal provided by the second control terminal; A first end of the first energy storage circuit is electrically connected to the write node, a second end of the first energy storage circuit is electrically connected to a first voltage end, and the first energy storage circuit is used to store electrical energy; The compensation circuit further includes a third control circuit; The third control circuit is electrically connected to the third control terminal, the first initial voltage terminal and the control node respectively, and is used to write an initial voltage provided by the first initial voltage terminal into the control node under the control of a third control signal provided by the third control terminal.

2. The pixel circuit according to claim 1, wherein: The first control terminal and the first reset terminal are the same control terminal; The first initialization circuit includes a first transistor, and the first control circuit includes a second transistor; The gate of the first transistor is electrically connected to the first reset terminal, the first electrode of the first transistor is electrically connected to the control node, and the second electrode of the first transistor is electrically connected to the control terminal of the driving circuit; A gate of the second transistor is electrically connected to the first control terminal, a first electrode of the second transistor is electrically connected to the write node, and a second electrode of the second transistor is electrically connected to the control node.

3. The pixel circuit according to claim 2, wherein: The first transistor is a p-type transistor, and the second transistor is an n-type transistor; or, The first transistor is an n-type transistor, and the second transistor is a p-type transistor.

4. The pixel circuit according to claim 1, wherein: The second control circuit includes a third transistor; the first energy storage circuit includes a first capacitor; The gate of the third transistor is electrically connected to the second control terminal, the first electrode of the third transistor is electrically connected to the data line, and the second electrode of the third transistor is electrically connected to the write node; A first end of the first capacitor is electrically connected to the write node, and a second end of the first capacitor is electrically connected to a first voltage end.

5. The pixel circuit according to claim 1, wherein: The third control circuit includes a fourth transistor; The gate of the fourth transistor is electrically connected to the third control terminal, the first electrode of the fourth transistor is electrically connected to the first initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the control node; The third control terminal and the first reset terminal are the same control terminal; The fourth transistor and the transistor included in the first initialization circuit are both p-type transistors; or the fourth transistor and the transistor included in the first initialization circuit are both n-type transistors.

6. The pixel circuit according to claim 1, wherein: The compensation circuit includes a fourth control circuit, a fifth control circuit and a second energy storage circuit; The first end of the second energy storage circuit is electrically connected to the control end of the driving circuit; the second end of the second energy storage circuit is electrically connected to the write node; The fourth control circuit is electrically connected to the fourth control terminal, the first voltage terminal and the write node respectively, and is used to control the communication between the first voltage terminal and the write node under the control of a fourth control signal provided by the fourth control terminal; The fifth control circuit is electrically connected to the second voltage terminal, the write node and the second initial voltage terminal respectively, and is used to control the connection between the write node and the second initial voltage terminal under the control of the second voltage signal provided by the second voltage terminal.

7. The pixel circuit according to claim 6, wherein: The fourth control terminal and the scanning terminal are the same control terminal; the fourth control circuit includes a fifth transistor, and the fifth control circuit includes a sixth transistor; The gate of the fifth transistor is electrically connected to the scan terminal, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the write node; The gate of the sixth transistor is electrically connected to the second voltage terminal, the first electrode of the sixth transistor is electrically connected to the write node, and the second electrode of the sixth transistor is electrically connected to the second initial voltage terminal.

8. The pixel circuit according to claim 7, wherein: The first voltage terminal is a first high voltage terminal, the second voltage terminal is a second high voltage terminal, and the sixth transistor is a p-type transistor; The fifth transistor and the transistor included in the data writing circuit are both p-type transistors; or the fifth transistor and the transistor included in the data writing circuit are both n-type transistors.

9. The pixel circuit according to claim 1, wherein: The second control end and the scanning end are the same control end; The compensation control circuit includes a seventh transistor, the data writing circuit includes an eighth transistor; the driving circuit includes a driving transistor; The gate of the seventh transistor is electrically connected to the scanning end, the first electrode of the seventh transistor is electrically connected to the gate of the driving transistor, and the second electrode of the seventh transistor is electrically connected to the second electrode of the driving transistor; A gate of the eighth transistor is electrically connected to the scanning end, a first electrode of the eighth transistor is electrically connected to the data line, and a second electrode of the eighth transistor is electrically connected to the first electrode of the driving transistor.

10. The pixel circuit according to claim 1, wherein: Also includes a first light emitting control circuit, a second light emitting control circuit and a second initialization circuit; The first light-emitting control circuit is electrically connected to the light-emitting control line, the first voltage terminal, and the first terminal of the driving circuit, respectively, and is configured to control the communication between the first voltage terminal and the first terminal of the driving circuit under the control of the light-emitting control signal provided by the light-emitting control line; The second light emitting control circuit is electrically connected to the light emitting control line, the second end of the drive circuit, and the first electrode of the light emitting element, respectively, and is used to control the second end of the drive circuit to be connected to the first electrode of the light emitting element under the control of the light emitting control signal; The second initialization circuit is electrically connected to the second reset terminal, the third initial voltage terminal and the first electrode of the light-emitting element respectively, and is configured to provide a third initial voltage provided by the third initial voltage terminal to the first electrode of the light-emitting element under the control of a second reset signal provided by the second reset terminal; The second electrode of the light emitting element is electrically connected to the third voltage terminal.

11. The pixel circuit according to claim 10, wherein: The driving circuit includes a driving transistor; The first light emitting control circuit includes a ninth transistor, the second light emitting control circuit includes a tenth transistor, and the second initialization circuit includes an eleventh transistor; The gate of the ninth transistor is electrically connected to the light emitting control line, the first electrode of the ninth transistor is electrically connected to the first voltage terminal, and the second electrode of the ninth transistor is connected to the first electrode of the driving transistor; The gate of the tenth transistor is electrically connected to the light emitting control line, the first electrode of the tenth transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the tenth transistor is electrically connected to the first electrode of the light emitting element; The gate of the eleventh transistor is electrically connected to the second reset terminal, the first electrode of the eleventh transistor is electrically connected to the third initial voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the first electrode of the light emitting element.

12. A driving method, applied to the pixel circuit according to any one of claims 1 to 11, characterized in that: The display cycle includes a holding frame; the driving method includes: In the holding frame, the compensation circuit maintains the potential of the control terminal of the driving circuit.

13. A display device, characterized in that: The method comprises the pixel circuit according to any one of claims 1 to 11.

Images