Pixel circuit driving method and scanning circuit

Abstract

This invention discloses a driving method and scanning circuit for a pixel circuit. The pixel circuit includes: a driving module, a data writing module, a first compensation module, a second compensation module, a gate reset module, an anode reset module, and a light-emitting control module. The driving method includes: multiple display cycles, each display cycle including a write frame and a hold frame; the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal each include at least two conduction pulses in the write frame, and each includes one conduction pulse in the hold frame; wherein, in the write frame, the conduction pulses of the first scan signal, the second scan signal, and the third scan signal are sequentially delayed and overlap. This invention can achieve multiple resets of the anode of the light-emitting device within each display cycle without increasing the complexity of the scanning circuit, balancing the display effect of the display panel and the achievement of a narrow bezel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a driving method and scanning circuit for a pixel circuit. Background Technology

[0002] Currently, in display modes such as Always On Display (AOD) that employ frame skipping, the anode reset of the light-emitting device only occurs once in the write frame within the same display cycle, and not in the hold frame. Therefore, the anode of the light-emitting device resets only once every relatively long interval, making the brightness change caused by the anode reset perceptible to the human eye, resulting in visual flicker. To address this issue, existing technologies require two types of scanning signals: one type includes a conduction pulse only in the write frame to control the gate reset and data writing processes of the driving transistors in the pixel circuit; the other type includes conduction pulses in both the write and hold frames to control the anode reset process of the light-emitting device. Because the waveforms of the two types of scanning signals are different, two sets of scanning circuits are required, making the overall structure of the scanning drive circuit complex and unfavorable for the design of narrow bezels on display panels. Therefore, existing technologies struggle to balance display quality and the achievement of narrow bezels. Summary of the Invention

[0003] This invention provides a driving method and scanning circuit for a pixel circuit, which enables multiple resets of the anode of the light-emitting device in each display cycle without increasing the complexity of the scanning circuit, thus balancing the display effect of the display panel and the achievement of a narrow bezel.

[0004] To achieve the above technical objectives, the embodiments of the present invention provide the following technical solutions:

[0005] A driving method for a pixel circuit, the pixel circuit comprising: a driving module, a data writing module, a first compensation module, a second compensation module, a gate reset module, an anode reset module, and a light emission control module; a first terminal of the gate reset module is connected to a first reference signal, the first compensation module is connected between a second terminal of the gate reset module and a control terminal of the driving module, and the second compensation module is connected between a second terminal of the gate reset module and a second terminal of the driving module; the gate reset module is connected to a first scan signal, the first compensation module is connected to a second scan signal, the data writing module and the second compensation module are both connected to a third scan signal, and the anode reset module is connected to a fourth scan signal;

[0006] The driving method includes: multiple display cycles, each display cycle including a write frame and a hold frame;

[0007] The first scan signal, the second scan signal, the third scan signal, and the fourth scan signal each include at least two conduction pulses in the write frame and one conduction pulse in the hold frame; wherein, in the write frame, the conduction pulses of the first scan signal, the second scan signal, and the third scan signal are sequentially delayed and overlap.

[0008] Optionally, the write frame includes:

[0009] During the gate reset phase, the gate reset module is turned on in response to the first scan signal, and the first compensation module is turned on in response to the second scan signal, so that the first reference signal is transmitted to the control terminal of the drive module.

[0010] During the data writing phase, the first compensation module is turned on in response to the second scan signal, and both the data writing module and the second compensation module are turned on in response to the third scan signal, so that the data voltage is written to the control terminal of the drive module.

[0011] In the first anode reset stage, the anode reset module is turned on in response to the fourth scan signal, so that the second reference signal is transmitted to the anode of the light-emitting device;

[0012] In the first light-emitting stage, the light-emitting control module responds to the light-emitting control signal and turns on, causing the driving module to generate a driving current according to the potential of the control terminal of the driving module, thereby driving the light-emitting device to emit light.

[0013] The hold frame includes:

[0014] In the second anode reset stage, the anode reset module is turned on in response to the fourth scan signal, so that the second reference signal is transmitted to the anode of the light-emitting device;

[0015] In the second light-emitting stage, the light-emitting control module responds to the light-emitting control signal and turns on, causing the driving module to generate a driving current according to the potential of the control terminal of the driving module, thereby driving the light-emitting device to emit light.

[0016] Optionally, the first reference signal is a first potential in the write frame and a floating potential in the hold frame;

[0017] The second reference signal is always maintained at the second potential;

[0018] Preferably, the first potential is the same as the second potential.

[0019] Optionally, the first scan signal connected to the pixel circuit of the next row is multiplexed to the fourth scan signal connected to the pixel circuit of the same row;

[0020] Alternatively, any one of the first, second, and third scan signals connected to the pixel circuit in this row can be multiplexed as the fourth scan signal connected to the pixel circuit in this row.

[0021] Optionally, the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal are provided by the same set of cascaded shift registers;

[0022] Preferably, the i-th level shift register, the (i+2)-th level shift register, and the (i+4)-th level shift register sequentially provide the first scan signal, the second scan signal, and the third scan signal to the same row of pixel circuits, respectively, where i is an integer greater than or equal to 1.

[0023] Accordingly, this embodiment of the invention also provides a scanning circuit, including: an input signal generation module and a cascaded multi-stage shift register; the input signal generation module is electrically connected to the input terminal of the first-stage shift register and is used to provide an input signal to the first-stage shift register;

[0024] The scan signal output by the shift register includes at least two conduction pulses in the write frame and one conduction pulse in the hold frame; the scan signal serves as the first scan signal, the second scan signal, the third scan signal, or the fourth scan signal in the pixel circuit driving method provided in any embodiment of the present invention.

[0025] Optionally, the first clock input of the odd-level shift register and the second clock input of the even-level shift register are both connected to the first clock signal; the second clock input of the odd-level shift register and the first clock input of the even-level shift register are both connected to the second clock signal.

[0026] The input signal covers at least two on-pulses of the first clock signal in the write frame, and the input signal covers one on-pulse of the first clock signal in the hold frame.

[0027] Optionally, the input signal generation module includes: a first transmission unit and a second transmission unit;

[0028] The control terminal of the first transmission unit is connected to a first switch signal, and the input terminal of the first transmission unit is connected to a first input signal. The control terminal of the second transmission unit is connected to a second switch signal, and the input terminal of the second transmission unit is connected to a second input signal. The output terminal of the first transmission unit is electrically connected to the output terminal of the second transmission unit and serves as the output terminal of the input signal generation module.

[0029] Preferably, the first transmission unit includes: a first transistor; the gate of the first transistor serves as the control terminal of the first transmission unit, the first electrode of the first transistor serves as the input terminal of the first transmission unit, and the second electrode of the first transistor serves as the output terminal of the first transmission unit;

[0030] The second transmission unit includes: a second transistor; the gate of the second transistor serves as the control terminal of the second transmission unit, the first terminal of the second transistor serves as the input terminal of the second transmission unit, and the second terminal of the second transistor serves as the output terminal of the second transmission unit.

[0031] Optionally, the first input signal includes a first pulse located in the write frame, the pulse width of the first pulse covering at least two on pulses of the first clock signal;

[0032] The second input signal includes a second pulse located in the hold frame; the pulse width of the second pulse covers one turn-on pulse of the first clock signal;

[0033] Preferably, the second input signal further includes a third pulse located in the write frame, the pulse width of the third pulse being the same as the pulse width of the second pulse.

[0034] Optionally, the first switching signal includes a fourth pulse located in the write frame, the pulse width of the fourth pulse covering the first pulse; the second switching signal includes a fifth pulse located in the hold frame, the fifth pulse coinciding with the second pulse;

[0035] or,

[0036] The first switch signal maintains an on potential in the write frame and an off potential in the hold frame; the second switch signal maintains the off potential in the write frame and the on potential in the hold frame.

[0037] The pixel circuit driving method provided in this invention includes at least two conduction pulses in each scan signal within the write frame. The overlapping periods of these conduction pulses are used to achieve gate reset and data writing in the write frame, ensuring normal driving of the pixel circuit. Furthermore, each scan signal is configured to include only a single conduction pulse in the hold frame, allowing the anode of the light-emitting device to be reset in each hold frame, thereby improving flicker and enhancing display performance. Additionally, the above configuration ensures that the waveforms of the scan signals are identical. The first, second, third, and fourth scan signals can be provided by the same set of cascaded shift registers, eliminating the need for additional scan circuitry in the display panel. This facilitates narrow bezel implementation and reduces power consumption. Therefore, compared to existing technologies, this invention can achieve multiple resets of the anode of the light-emitting device within each display cycle without increasing the complexity of the scan circuit, balancing display panel performance and narrow bezel implementation.

[0038] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0041] Figure 2 This is a schematic diagram of the driving timing of a pixel circuit provided in an embodiment of the present invention;

[0042] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0043] Figure 4 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0044] Figure 5 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0045] Figure 6 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0046] Figure 7 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0047] Figure 8 This is a schematic diagram of the simulation results of the pixel circuit driving method provided in the embodiment of the present invention;

[0048] Figure 9 This is a schematic diagram of a scanning circuit provided in an embodiment of the present invention;

[0049] Figure 10 This is a schematic diagram of the driving timing of a scanning circuit provided in an embodiment of the present invention;

[0050] Figure 11 This is a schematic diagram of the structure of a shift register provided in an embodiment of the present invention;

[0051] Figure 12 This is a schematic diagram of the driving timing of a shift register provided in an embodiment of the present invention;

[0052] Figure 13 This is a schematic diagram of the structure of an input signal generation module provided in an embodiment of the present invention;

[0053] Figure 14 This is a schematic diagram illustrating the correspondence between input signals and switch signals in an input signal generation module provided in an embodiment of the present invention;

[0054] Figure 15 This is a schematic diagram showing the correspondence between the input signal and the switch signal of another input signal generation module provided in an embodiment of the present invention. Detailed Implementation

[0055] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0056] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0057] This invention provides a pixel circuit driving method that can be applied to improve the flickering problem of display panels at low refresh rates. The driving method will now be described in conjunction with the pixel circuit to which it is applicable.

[0058] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. See also... Figure 1 The pixel circuit includes: a driving module 10, a data writing module 20, a first compensation module 30, a second compensation module 50, a gate reset module 40, an anode reset module 60, and a light emission control module 70. The first terminal of the gate reset module 40 is connected to a first reference signal Vref1, and its control terminal is connected to a first scan signal S1. The first compensation module 30 is connected between the second terminal of the gate reset module 40 and the control terminal of the driving module 10, and its control terminal is connected to a second scan signal S2. The second compensation module 50 is connected between the second terminal of the gate reset module 40 and the second terminal of the driving module 10, and its control terminal is connected to a third scan signal S3. The control terminal of the data writing module 20 is connected to the third scan signal S3, its first terminal is connected to a data voltage Vdata, and its second terminal is electrically connected to the first terminal of the driving module 10. The first terminal of the anode reset module 60 is connected to a second reference signal Vref2, its control terminal is connected to a fourth scan signal S4, and its second terminal is electrically connected to the anode of the OLED light-emitting device. The light-emitting control module 70, the driving module 10, and the light-emitting device OLED are connected in series between the first power supply terminal and the second power supply terminal. The first power supply terminal is connected to the first power signal ELVDD, the second power supply terminal is connected to the second power signal ELVSS, and the control terminal of the light-emitting control module 70 is connected to the light-emitting control signal EM.

[0059] Figure 2 This is a schematic diagram of the driving timing of a pixel circuit according to an embodiment of the present invention. Combined with... Figure 1 and Figure 2 The driving method for this pixel circuit includes multiple display cycles, each display cycle including a write frame F1 and a hold frame F2. The number of hold frames F2 in one display cycle can be determined based on the actual refresh rate and the duration of a single display frame, and is not limited here. The first scan signal S1, the second scan signal S2, the third scan signal S3, and the fourth scan signal S4 each include at least two conduction pulses in the write frame F1, and each include one conduction pulse in the hold frame F2.

[0060] In write frame F1, the turn-on pulses of the first scan signal S1, the second scan signal S2, and the third scan signal S3 are sequentially delayed and overlap. That is, in write frame F1, the initial turn-on pulses of the first scan signal S1, the second scan signal S2, and the third scan signal S3 appear sequentially, with overlapping turn-on pulses between the first scan signal S1 and the second scan signal S2, and overlapping turn-on pulses between the second scan signal S2 and the third scan signal S3. Figure 2 As shown, in the write frame F1, when each scan signal includes a dual-conduction pulse, the second conduction pulse of the first scan signal S1 overlaps with the first conduction pulse of the second scan signal S2, and the second conduction pulse of the second scan signal S2 overlaps with the first conduction pulse of the third scan signal S3.

[0061] The gate reset and data writing processes in frame F1 are both based on the aforementioned overlapping conduction pulses. Specifically, during the overlapping period of the conduction pulses of the first scan signal S1 and the second scan signal S2 (i.e., gate reset stage T1), the gate reset module 40 and the first compensation module 30 are simultaneously turned on. The first reference signal Vref1 is transmitted to the control terminal of the drive module 10 through the gate reset module 40 and the first compensation module 30, thereby resetting the control terminal of the drive module 10. During the overlapping period of the conduction pulses of the second scan signal S2 and the third scan signal S3 (i.e., data writing stage T2), the data writing module 20, the first compensation module 30, and the second compensation module 50 are simultaneously turned on. The data voltage Vdata is transmitted to the gate of the drive module 10 through the data writing module 20, the first and second terminals of the drive module 10, the second compensation module 50, and the first compensation module 30, thereby realizing data writing.

[0062] Furthermore, during the cutoff pulse of the light emission control signal EM in write frame F1, the anode reset process of the OLED device is not interfered with by other processes such as data writing in write frame F1 because the light emission control module 70 is turned off. Therefore, in write frame F1, the conduction pulse of the fourth scan signal S4 can coincide with, partially overlap with, or completely not overlap with the conduction pulses of other scan signals. The anode initialization process of the OLED device can be performed at any time during the cutoff pulse of the light emission control signal EM, and the specific reset timing can be set according to actual needs.

[0063] In each hold frame F2, the fourth scan signal S4 has a conduction pulse. Under the control of this conduction pulse, the anode reset module 60 is turned on, so that the second reference signal Vref2 can reset the anode of the light-emitting device OLED in each hold frame F2, thereby pulling the potential of the anode of the light-emitting device OLED down to the same potential as the anode reset process in the write frame F1. This ensures that the minimum brightness of the light-emitting device OLED in the write frame F1 and the hold frame F2 is at the same level, avoiding visual flicker caused by the difference in minimum brightness between the hold frame F2 and the display frame F1 under low refresh rates, especially when the display cycle is long and the number of hold frames F2 is large.

[0064] It should be noted that in each hold frame F2, the turn-on pulses of the first scan signal S1, the second scan signal S2 and the third scan signal S3 are delayed sequentially and do not overlap, so as to ensure that the first compensation module 30 and the gate reset module 40 are not turned on at the same time in the hold frame F2, or the first compensation module 30 and the second compensation module 50 are turned on at the same time, so as to avoid affecting the potential of the control terminal of the drive module 10.

[0065] See Figure 2 As can be seen, the waveforms of each scan signal are the same, the only difference being the start time of the conduction pulse. Therefore, the first scan signal S1, the second scan signal S2, the third scan signal S3 and the fourth scan signal S4 are provided by the same set of cascaded shift registers, and only one set of scan circuits needs to be configured in the display panel to provide all scan signals.

[0066] The pixel circuit driving method provided in this embodiment of the invention includes at least two conduction pulses in each scan signal within the write frame F1. The overlapping periods of these conduction pulses are used to achieve the gate reset and data writing process in the write frame F1, ensuring normal driving of the pixel circuit. Furthermore, each scan signal is configured to include only a single conduction pulse in the hold frame F2, allowing the anode of the OLED to be reset in each hold frame F2, thereby improving flicker and enhancing display performance. Additionally, the above configuration ensures that the waveforms of the scan signals are identical. The first scan signal S1, the second scan signal S2, the third scan signal S3, and the fourth scan signal S4 can be provided by the same set of cascaded shift registers, eliminating the need for additional scan circuitry in the display panel. This facilitates the implementation of narrow bezels and reduces power consumption. Therefore, compared to existing technologies, this embodiment of the invention can achieve multiple resets of the OLED anode in each display cycle without increasing the complexity of the scan circuit, balancing display performance and narrow bezel implementation.

[0067] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. See also... Figure 3For example, the driving module 10 includes a driving transistor M11, the data writing module 20 includes a transistor M12, the first compensation module 30 includes a transistor M13, the gate reset module 40 includes a transistor M14, the second compensation module 50 includes a transistor M15, the anode reset module 60 includes a transistor M16, and the light emission control module 70 includes transistors M17 and M18. Furthermore, the pixel circuit may also include a storage capacitor Cst connected between the gate of the driving transistor M11 and the first power supply terminal to maintain the gate potential of the driving transistor M11.

[0068] To reduce leakage current through the gate reset module 40, transistor M14 can be configured as a dual-gate structure. Furthermore, to reduce leakage current through the second compensation module 50, a third compensation module 80 composed of transistor M19 can be provided in the pixel circuit. Transistors M19 and M15 are connected in series between the second terminal of the driving module 10 and the second terminal of the gate reset module 40. Transistors M19 and M15 can be considered as a dual-gate structure, which can reduce leakage current. For example, the gate of transistor M19 can be configured as follows: Figure 3 The second scan signal S2 can be connected, or the third scan signal S3 can be connected.

[0069] The following is based on Figure 3 The pixel circuit structure in the text, taking as an example that all transistors in the pixel circuit are P-type transistors (with a low on-state potential) and each scan signal is a double pulse in the written frame, explains the specific driving method of the pixel circuit. Combined with... Figure 2 and Figure 3 For example, in the driving method of the pixel circuit, writing frame F1 includes:

[0070] During the gate reset phase T1, transistor M14 turns on in response to the first scan signal S1, and transistor M13 turns on in response to the second scan signal S2, so that the first reference signal Vref1 is transmitted to the gate of the driving transistor M11, thereby resetting the gate of the driving transistor M11.

[0071] During the data writing phase T2, transistors M13 and M19 turn on in response to the second scan signal S2, while transistors M12 and M15 both turn on in response to the third scan signal S3, causing the data voltage Vdata to be written into the gate of the driving transistor M11.

[0072] In the first anode reset stage, transistor M16 is turned on in response to the fourth scan signal S4, causing the second reference signal Vref2 to be transmitted to the anode of the OLED, thus resetting the anode of the OLED. Since the fourth scan signal S4 includes a dual-conduction pulse in the write frame F1, the first anode reset stage includes two anode reset sub-stages: the first anode reset sub-stage T31 and the second anode reset stage T32.

[0073] In the first light-emitting stage T4, both transistors M17 and M18 are turned on in response to the conduction pulse of the light-emitting control signal EM, causing the driving transistor M11 to generate a driving current according to the gate potential of the driving transistor M11, so as to drive the OLED light-emitting device to emit light.

[0074] Hold frame F2 includes:

[0075] In the second anode reset stage T5, transistor M16 turns on in response to the fourth scan signal S4, so that the second reference signal Vref2 is transmitted to the anode of the light-emitting device OLED, thereby realizing the reset of the anode of the light-emitting device OLED in the hold frame F2.

[0076] In the second light-emitting stage T6, both transistors M17 and M18 turn on in response to the light-emitting control signal EM, driving transistor M11 to generate a driving current again, driving the OLED light-emitting device to emit light.

[0077] In summary, the embodiments of the present invention provide a driving method for a pixel circuit based on a scanning signal in the form of a dual-conduction pulse for the write frame and a single-conduction pulse for the hold frame. This method can perform a reset of the OLED anode in each hold frame of each display cycle, thereby improving the flickering problem in low-frequency display modes such as always-on display.

[0078] See also Figure 2 Based on the above embodiments, optionally, the first reference signal Vref1 is maintained at a first potential V1 in the write frame F1 and is a floating potential in the hold frame F2. For example, the first potential V1 is a low potential, such as -3V. This setting allows the gate initialization stage T1 in the write frame F1 to proceed normally, while avoiding the influence of the potential of the first reference signal Vref1 itself on the gate potential of the driving transistor M11 in the hold frame F2, thus ensuring that the luminous brightness of the OLED in each second light-emitting stage T6 is the same as or similar to that in the first light-emitting stage T4.

[0079] The second reference signal Vref2 can always maintain the second potential V2 to ensure that the reset degree of the OLED anode is the same in both the first anode reset stage and the second anode reset stage T5. For example, the second potential V2 is a low potential, such as -3V. The first potential V1 and the second potential V2 can be the same or different, depending on actual requirements.

[0080] The above embodiments provide exemplary solutions for setting the fourth scan signal S4 separately, but are not intended to limit the present invention. In other embodiments, other scan signals can be multiplexed as the fourth scan signal S4 to simplify the wiring of the display panel.

[0081] In one embodiment, optionally, any one of the first scan signal S1, the second scan signal S2, and the third scan signal S3 connected to the pixel circuit in this row can be multiplexed as the fourth scan signal S4 connected to the pixel circuit in this row. Figure 4 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. See also Figure 4 For example, if the second scan signal S2 of this row is multiplexed as the fourth scan signal S4 of this row, then the first anode reset stage T31 coincides with the gate reset stage T1, and the second anode reset stage T32 coincides with the data write stage T2. For example, if other scan signals of this row are multiplexed as the fourth scan signal S4 of this row, then the occurrence time of the two anode reset stages changes accordingly.

[0082] Figure 5 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. See also Figure 5 In another embodiment, optionally, the first scan signal S1n+1 connected to the (n+1)th row pixel circuit can be multiplexed into the fourth scan signal S4n connected to the nth row pixel circuit, where n≥1. For example, if the first scan signals S1 connected to adjacent rows of pixel circuits are provided by adjacent shift registers, then the conduction pulses of the first scan signals S1 connected to adjacent rows of pixel circuits are shifted sequentially without overlap. Therefore, in this connection method, the fourth scan signal S4 connected to the same row of pixel circuits does not overlap with the conduction pulses of other scan signals in the same row, and the two anode reset stages are performed separately from other stages.

[0083] Based on the above embodiments, optionally, since the scanning signal output by the i-th level shift register overlaps with the scanning signal output by the (i+2)-th level shift register in the write frame F1, the i-th level shift register, the (i+2)-th level shift register, and the (i+4)-th level shift register can be configured to sequentially provide the first scanning signal S1, the second scanning signal S2, and the third scanning signal S3 to the same row of pixel circuits, so that the conduction pulses of the first scanning signal S1, the second scanning signal S2, and the third scanning signal S3 overlap sequentially in the write frame F1, where i is an integer greater than or equal to 1.

[0084] The above embodiments exemplify that each scan signal includes a dual-conduction pulse in the write frame F1, but are not intended to limit the invention. In other embodiments, optionally, each scan signal may also include multiple conduction pulses in the write frame F1; the following description uses a three-conduction pulse as an example.

[0085] Figure 6 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. See also Figure 6 For example, the initial conduction pulses of the four scan signals in the write frame F1 are sequentially spaced at the same time interval, for example, one pulse cycle apart. Therefore, there are two overlapping conduction pulses between adjacent scan signals. This inserts a drive transistor reset stage T0 between the gate reset stage T1 and the data write stage T2. Specifically, in the drive transistor reset stage T0, transistors M12, M13, M14, M15, and M19 are all turned on. The first reference signal Vref1 can be transmitted to the second terminal of the drive transistor M11, and the data voltage Vdata can be transmitted to the first terminal of the drive transistor M11, making the source-drain voltage difference of the drive transistor M11 Vdata-V1, generating a large current surge in the drive transistor M11, thereby accelerating the recovery of the threshold voltage of the drive transistor M11 and correcting the threshold voltage drift of the drive transistor M11. Furthermore, since the fourth scan signal S4 includes three conduction pulses, the first anode reset stage may also include a third anode reset sub-stage T33, whose driving process is the same as the other anode reset sub-stages and will not be described again.

[0086] Figure 7 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. See also Figure 7 In another implementation, optionally, the initial conduction pulses of each two adjacent scan signals in the written frame F1 can be spaced at different times. As long as there is at least one overlapping conduction pulse between the first scan signal S1 and the second scan signal S2, and at least one overlapping conduction pulse between the second scan signal S2 and the third scan signal S3, normal driving of the pixel circuit can be guaranteed. Figure 9 In the setup shown, there are two overlapping conduction pulses between the second scan signal S2 and the third scan signal S3, which allows the data writing stage to include a first data writing sub-stage T21 and a second data writing sub-stage T22, thereby extending the data writing time of the pixel circuit and improving the data writing effect.

[0087] To verify the effectiveness of the driving method provided in the embodiments of the present invention, the inventors based on... Figure 3 The structure of the mid-pixel circuit was simulated and verified. The comparison results of resetting the anode of the light-emitting device during the hold frame versus not resetting it can be found in [reference needed]. Figure 8 . Figure 8 In the diagram, the solid line represents the simulation results of the driving method provided in this embodiment, and the dashed line represents the simulation results of resetting the anode of the light-emitting device without holding the frame. According to... Figure 8 It can be seen that performing an anode reset in the hold frame, compared to not performing an anode reset in the hold frame, can reduce the difference gap by a certain amount of the minimum current in the hold frame. This indicates that, based on the driving method provided in this embodiment, by resetting the anode of the light-emitting device in the hold frame, the minimum current of the light-emitting device in the hold frame can be effectively reduced to the same level as that in the write frame, thereby reducing the brightness of the light-emitting device before the second light-emitting stage to the same brightness level as before the first light-emitting stage, effectively improving the flicker problem.

[0088] The present invention also provides a scanning circuit for providing the scanning signal required in the driving method of the pixel circuit in any embodiment of the present invention, so as to support the implementation of the above driving method. Figure 9 This is a schematic diagram of a scanning circuit provided in an embodiment of the present invention. See also... Figure 9 The scanning circuit includes an input signal generation module 110 and cascaded multi-stage shift registers 120. The input signal generation module 110 is electrically connected to the input terminal of the first-stage shift register 121 and is used to provide an input signal SIN to the first-stage shift register 121. The scanning signals output by each stage of the shift register 120 include at least two conduction pulses in the write frame and one conduction pulse in the hold frame. The scanning signals can be used as the first, second, third, or fourth scanning signals required by the pixel circuit. Specifically, as shown in the embodiments of the pixel circuit driving method described above, the scanning signals output by the four-stage shift register 120 can be selected as the first, second, third, or fourth scanning signals of the same row of pixel circuits, respectively. Alternatively, the scanning signals output by the three-stage shift register 120 can be selected as the first, second, and third scanning signals of the same row of pixel circuits, and any one of the three-stage scanning signals can be selected as the fourth scanning signal of the row of pixel circuits.

[0089] In this circuit, the first and second clock terminals of each shift register are alternately connected to the first clock signal SCK1 and the second clock signal SCK2. Specifically, the first clock terminal of the odd-level shift register 120 and the second clock terminal of the even-level shift register 120 are both connected to the first clock signal SCK1; the second clock terminal of the odd-level shift register 120 and the first clock terminal of the even-level shift register 120 are both connected to the second clock signal SCK2. Both the first clock signal SCK1 and the second clock signal SCK2 are clock signals that alternate between high and low potentials, and their on-state potentials are interleaved. The output process of this scanning circuit will be described in detail below.

[0090] Figure 10 This is a schematic diagram of the driving timing of a scanning circuit provided in an embodiment of the present invention, combined with... Figure 9 and Figure 10 Based on the above embodiments, optionally, the input signal SIN covers at least two conduction pulses of the first clock signal SCK1 in the write frame, and the input signal SIN covers one conduction pulse of the first clock signal SCK1 in the hold frame F2. The first-stage scan signal SCAN1 output by the first-stage shift register 121 is equivalent to the shifted output of the input signal SIN, and the remaining scan signals are equivalent to the shifted outputs of their predecessor scan signals, and the interval between the initial conduction pulses of adjacent scan signals is half a pulse period of the clock signal. Figure 10 As shown, the input signal SIN covers the two conduction pulses of the first clock signal SCK1 in the write frame, so that each scan signal includes two conduction pulses in the write frame F1.

[0091] Based on the above embodiments, optionally, by adjusting the waveform of the input signal SIN, the shift register 120 can be implemented using an existing shift register without adjusting the structure of the shift register 120. The following is in conjunction with... Figure 11 Taking the 8T2C architecture as an example, the structure of shift register 120 and its driving process are explained.

[0092] Figure 11 This is a schematic diagram of a shift register provided in an embodiment of the present invention. See also: Figure 11 For example, the shift register specifically includes: transistors M21, M22, M23, M24, M25, M26, M27, and M28, and capacitors C1 and C2. Figure 12 This is a schematic diagram of the driving timing of a shift register provided in an embodiment of the present invention.

[0093] Figure 12 This can be viewed as the driving timing of the shift register during frame writing, combined with... Figure 11 and Figure 12 Taking the first-stage shift register 121 as an example, the driving process of this shift register in the write frame includes:

[0094] In the first stage (T71), the first clock signal SCK1 and the input signal SIN are at low potentials, while the second clock signal SCK2 is at a high potential. Transistors M21, M22, and M28 are turned on. The low potential of the input signal SIN is transmitted to node N1 through transistor M21, turning on transistor M23. The low potential of the first clock signal SCK1 is transmitted to node N2 through transistor M23, and simultaneously, the low potential of the second potential signal VGL is transmitted to node N2 through transistor M22, turning on transistor M27. The high potential of the first potential signal VGH is output through transistor M27. The low potential of node N1 is transmitted to node N3 through transistor M28, turning on transistor M26. The high potential of the second clock signal SCK2 is output through transistor M26. Therefore, in this stage, the first-stage scan signal SCAN1 is at a high potential.

[0095] In the second stage (T72), the second clock signal SCK2 and the input signal SIN are at low levels, while the first clock signal SCK1 is at a high level. Transistor M21 is off, and the low level of the input signal SIN does not affect the potential of node N1. Transistor M22 is off, while transistor M28 remains on. Due to the storage effect of capacitor C1, node N3 maintains the low potential from the previous stage, causing transistor M26 to turn on; the low potential of node N3 is transmitted to node N1 through transistor M28, causing transistor M23 to turn on. The high potential of the first clock signal SCK1 is transmitted to node N2 through transistor M23, causing transistor M27 to turn off. The low potential of the second clock signal SCK2 is output through transistor M26, and the first-stage scan signal SCAN1 is at a low level.

[0096] In the third stage (T73), the first clock signal SCK1 and the input signal SIN are at low levels, while the second clock signal SCK2 is at a high level. The driving process for this stage can be found in the description of the first stage (T71). In this stage, the first-stage scan signal SCAN1 is at a high level.

[0097] In the fourth stage T74, the second clock signal SCK2 is at a low level, while the first clock signal SCK1 and the input signal SIN are at a high level. Since transistor M21 is off, the high level of the input signal SIN does not affect the potential of node N1. For the driving process of other parts, please refer to the description of the second stage T72, in which the first-stage scan signal SCAN1 is at a low level.

[0098] In stage T75, the first clock signal SCK1 is low, while the second clock signal SCK2 and the input signal SIN are high. Transistors M21, M22, and M28 are turned on. The high potential of the input signal SIN is transmitted to node N1 through transistor M21, causing transistor M23 to turn off; the high potential of node N1 is transmitted to node N3 through transistor M28, causing transistor M26 to turn off. The low potential of the second potential signal VGL is transmitted to node N2 through transistor M22, causing transistor M27 to turn on; the high potential of the first potential signal VGH is output through transistor M27, and the first-stage scan signal SCAN1 is high.

[0099] In stage T76, the second clock signal SCK2 is low, while the first clock signal SCK1 and the input signal SIN are both high. Transistors M21 and M22 are off, while transistors M25 and M28 are on. Due to the storage effect of capacitor C2, node N2 maintains the low potential from the previous stage, causing transistors M24 and M27 to conduct. The high potential of the first potential signal VGH is transmitted to node N3 through transistors M24, M25, and M28, causing transistor M26 to be off. The high potential of the first potential signal VGH is output through transistor M27, and the first-stage scan signal SCAN1 is high.

[0100] The subsequent stages repeat the fifth stage T75 and the sixth stage T76. The first-stage scan signal SCAN1 remains at a high level until the input signal SIN becomes low again.

[0101] This invention provides a method for generating a scan signal with dual conduction pulses in a write frame. For generating other numbers of conduction pulses, this can be achieved by adjusting the conduction pulse width of the input signal SIN. For example, in a hold frame, setting the conduction pulse of the input signal SIN to only cover one conduction pulse of the first clock signal SCK1 allows the shift register driving process to exclude the aforementioned third stage T73 and fourth stage T74, thus forming a scan signal containing a single conduction pulse. As another example, in a write frame, setting the conduction pulse of the input signal SIN to cover n conduction pulses of the first clock signal SCK1, where n≥3, then the aforementioned third stage T73 and fourth stage T74 are repeated n-2 times during the driving process, thereby forming a scan signal containing n conduction pulses. Exemplarily, when the scan signal needs to include dual conduction pulses in the write frame and a single conduction pulse in the hold frame, the conduction pulse width of the input signal SIN in the write frame can be set to three times the conduction pulse width in the hold frame.

[0102] The above embodiments exemplify the structure of the shift register 120. The structure of the input signal generation module 110 and the method for generating the input signal SIN will now be described.

[0103] Figure 13 This is a schematic diagram of the structure of an input signal generation module provided in an embodiment of the present invention. See also... Figure 13 In one embodiment, optionally, the input signal generation module 110 includes: a first transmission unit 111 and a second transmission unit 112. The control terminal of the first transmission unit 111 is connected to a first switch signal SW1, and the input terminal of the first transmission unit 111 is connected to a first input signal SIN1. The control terminal of the second transmission unit 112 is connected to a second switch signal SW2, and the input terminal of the second transmission unit 112 is connected to a second input signal SIN2. The output terminal of the first transmission unit 111 is electrically connected to the output terminal of the second transmission unit 112, and serves as the output terminal of the input signal generation module 110.

[0104] Based on the control of the conduction states of the two transmission units by two switching signals, and in conjunction with the waveform control of the first input signal SIN1 and the second input signal SIN2, input signals SIN with different conduction pulse widths in the write frame and the hold frame can be generated. The possible signal generation methods are described below.

[0105] Figure 14 This is a schematic diagram illustrating the correspondence between input signals and switch signals in an input signal generation module according to an embodiment of the present invention. See also... Figure 14 In one embodiment, optionally, the first input signal SIN1 includes a first pulse p1 located in write frame F1, the pulse width of the first pulse p1 covering at least two conduction pulses of the first clock signal SCK1. The second input signal SIN2 includes a second pulse p2 located in hold frame F2; the pulse width of the second pulse p2 covers one conduction pulse of the first clock signal SCK1. Furthermore, the first switch signal SW1 includes a fourth pulse p4 located in write frame F1, the pulse width of the fourth pulse p4 covering the first pulse p1; the second switch signal SW2 includes a fifth pulse p5 located in hold frame F2, the fifth pulse p5 coinciding with the second pulse p2.

[0106] This configuration ensures that when the first switch signal SW1 controls the first transmission unit 111 to be turned on, the first input signal SIN1 serves as the input signal SIN, and the first pulse p1 is the turn-on pulse of the input signal SIN in the write frame F1; while when the second switch signal SW2 controls the second transmission unit 112 to be turned on, the second input signal SIN2 serves as the input signal SIN, and the second pulse p2 is the turn-on pulse of the input signal SIN in the hold frame F2.

[0107] Based on the above embodiments, optionally, the second input signal SIN2 may further include a third pulse p3 located in the write frame F1, the pulse width of the third pulse p3 being the same as the pulse width of the second pulse p2. This ensures that the second input signal SIN2 includes the same pulse in each display frame, which is beneficial for the implementation of the second input signal SIN2. Furthermore, the second input signal SIN2 can remain at a cutoff potential in the write frame F1 to prevent the second transmission unit 112 from being turned on in the write frame F1, thus preventing the second input signal SIN2 from affecting the input signal SIN.

[0108] Alternatively, the second switch signal SW2 can be configured to correspond to a sixth pulse p6 with the third pulse p3. During the overlap of the sixth pulse p6 and the fourth pulse p4, both transmission units are turned on. Since the first input signal SIN1 and the second input signal SIN2 are both at low potentials at this time, the input signal SIN is also at a low potential, which does not affect the correct generation of the input signal SIN. Furthermore, the first input signal SIN can be multiplexed as the first switch signal SW1, and the second input signal SIN2 can be multiplexed as the second switch signal SW1, in order to reduce the number of signals and output ports that the driver chip needs to provide, and simplify the wiring of the display panel.

[0109] Figure 15 This is a schematic diagram illustrating the correspondence between input signals and switch signals in another input signal generation module provided in this embodiment of the invention. See also... Figure 15 In another implementation, the first input signal SIN1 and the second input signal SIN2 can still be the same as... Figure 14 The waveforms are identical, differing only in the settings of the two switching signals. In this embodiment, the first switching signal SW1 can be set to maintain an on-state potential in write frame F1 and an off-state potential in hold frame F2; and the second switching signal SW2 can be set to maintain an off-state potential in write frame F1 and an on-state potential in hold frame F2, so that the input signal SIN is the waveform of the first input signal SIN in the write frame and the waveform of the second input signal SIN2 in the hold frame F2. This setting reduces the potential transitions between the two switching signals, which is beneficial for the implementation of the two switching signals.

[0110] See also Figure 13 Based on the above embodiments, optionally, the first transmission unit 111 includes: a first transistor M1; the gate of the first transistor M1 serves as the control terminal of the first transmission unit 111, and is connected to a first switching signal SW1; the first electrode of the first transistor M1 serves as the input terminal of the first transmission unit 111, and is connected to a first input signal SIN1; the second electrode of the first transistor M1 serves as the output terminal of the first transmission unit 111. In this embodiment, the first transmission unit 111 includes a single transistor, making the structure of the first transmission unit 111 simple and easy to implement.

[0111] Based on the above embodiments, optionally, the second transmission unit 112 includes: a second transistor M2; the gate of the second transistor M2 serves as the control terminal of the second transmission unit 112, and is connected to a second switching signal SW2; the first terminal of the second transistor M2 serves as the input terminal of the second transmission unit 112, and is connected to a second input signal SIN2; the second terminal of the second transistor serves as the output terminal of the second transmission unit 112. In this embodiment, the second transmission unit 112 includes only one transistor, making the structure of the second transmission unit 112 simple and easy to implement.

[0112] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0113] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A driving method of a pixel circuit, characterized by, The pixel circuit comprises a driving module, a data writing module, a first compensation module, a second compensation module, a gate reset module, an anode reset module and a light emitting control module; a first end of the gate reset module is connected to a first reference signal, the first compensation module is connected between a second end of the gate reset module and a control end of the driving module, and the second compensation module is connected between the second end of the gate reset module and a second end of the driving module; the gate reset module is connected to a first scanning signal, the first compensation module is connected to a second scanning signal, the data writing module and the second compensation module are connected to a third scanning signal, and the anode reset module is connected to a fourth scanning signal. The driving method comprises a plurality of display periods, each display period comprising a writing frame and a holding frame. The first scanning signal, the second scanning signal, the third scanning signal and the fourth scanning signal each comprise at least two conduction pulses in the writing frame and one conduction pulse in the holding frame; wherein, in the writing frame, the conduction pulses of the first scanning signal, the second scanning signal and the third scanning signal are sequentially delayed and overlap.

2. The driving method of the pixel circuit according to claim 1, wherein The writing frame comprises: a gate reset stage, in which the gate reset module is turned on in response to the first scanning signal, and the first compensation module is turned on in response to the second scanning signal, so that the first reference signal is transmitted to the control end of the driving module; a data writing stage, in which the first compensation module is turned on in response to the second scanning signal, and the data writing module and the second compensation module are turned on in response to the third scanning signal, so that a data voltage is written to the control end of the driving module; a first anode reset stage, in which the anode reset module is turned on in response to the fourth scanning signal, so that a second reference signal is transmitted to the anode of the light emitting device; a first light emitting stage, in which the light emitting control module is turned on in response to a light emitting control signal, so that the driving module generates a driving current according to the potential of the control end of the driving module to drive the light emitting device to emit light; The holding frame comprises: a second anode reset stage, in which the anode reset module is turned on in response to the fourth scanning signal, so that a second reference signal is transmitted to the anode of the light emitting device; a second light emitting stage, in which the light emitting control module is turned on in response to a light emitting control signal, so that the driving module generates a driving current according to the potential of the control end of the driving module to drive the light emitting device to emit light.

3. The driving method of the pixel circuit according to claim 2, wherein The first reference signal is at a first potential in the writing frame and at a floating potential in the holding frame; The second reference signal always maintains a second potential.

4. The driving method of the pixel circuit according to claim 3, wherein The first potential is the same as the second potential.

5. The driving method of the pixel circuit according to claim 1, wherein The first scanning signal to which the pixel circuit in the next row is connected is multiplexed as the fourth scanning signal to which the pixel circuit in the current row is connected. Alternatively, any one of the first scanning signal, the second scanning signal and the third scanning signal to which the pixel circuit in the current row is connected is multiplexed as the fourth scanning signal to which the pixel circuit in the current row is connected.

6. The driving method of the pixel circuit according to claim 1, wherein The first scanning signal, the second scanning signal, the third scanning signal and the fourth scanning signal are provided by the same set of cascaded shift registers.

7. The driving method of the pixel circuit according to claim 6, wherein The i-th stage shift register, the i+2-th stage shift register and the i+4-th stage shift register sequentially provide a first scanning signal, a second scanning signal and a third scanning signal to the same row of pixel circuits, i is an integer greater than or equal to 1.

8. A scan circuit, characterized by Comprise: An input signal generation module and a plurality of cascaded shift registers; the input signal generation module is electrically connected with an input end of a first shift register, and is configured to provide an input signal to the first shift register; The scanning signal output by the shift register comprises at least two on-pulses in a writing frame and one on-pulse in a holding frame; the scanning signal is used as the first scanning signal, the second scanning signal, the third scanning signal or the fourth scanning signal in the driving method of the pixel circuit according to any one of claims 1-5.

9. The scan circuit of claim 8, wherein, The first clock end of the odd-numbered stage shift register and the second clock end of the even-numbered stage shift register are both connected to a first clock signal; the second clock end of the odd-numbered stage shift register and the first clock end of the even-numbered stage shift register are both connected to a second clock signal; The on-pulse width of the input signal in the writing frame covers at least two on-pulses of the first clock signal, and the on-pulse width of the input signal in the holding frame covers one on-pulse of the first clock signal.

10. The scan circuit of claim 9, wherein, The input signal generation module comprises a first transmission unit and a second transmission unit; The control end of the first transmission unit is connected to a first switch signal, the input end of the first transmission unit is connected to a first input signal, the control end of the second transmission unit is connected to a second switch signal, and the input end of the second transmission unit is connected to a second input signal; the output end of the first transmission unit is electrically connected with the output end of the second transmission unit, and serves as the output end of the input signal generation module.

11. The scan circuit of claim 10, wherein, The first transmission unit comprises a first transistor; the gate of the first transistor serves as the control end of the first transmission unit, the first pole of the first transistor serves as the input end of the first transmission unit, and the second pole of the first transistor serves as the output end of the first transmission unit; The second transmission unit comprises a second transistor; the gate of the second transistor serves as the control end of the second transmission unit, the first pole of the second transistor serves as the input end of the second transmission unit, and the second pole of the second transistor serves as the output end of the second transmission unit.

12. The scan circuit of claim 10, wherein, The first input signal comprises a first pulse in the writing frame, and the pulse width of the first pulse covers at least two on-pulses of the first clock signal; The second input signal comprises a second pulse in the holding frame; The pulse width of the second pulse covers one on-pulse of the first clock signal.

13. The scan circuit of claim 10, wherein, The second input signal further comprises a third pulse in the writing frame, and the pulse width of the third pulse is the same as that of the second pulse.

14. The scan circuit of claim 12, wherein, The first switch signal comprises a fourth pulse in the writing frame, and the pulse width of the fourth pulse covers that of the first pulse; the second switch signal comprises a fifth pulse in the holding frame, and the fifth pulse is coincident with the second pulse; Or, The first switch signal maintains a conduction potential in the write frame and maintains a cut-off potential in the retention frame; and the second switch signal maintains the cut-off potential in the write frame and maintains the conduction potential in the retention frame.

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