Method of manufacturing a semiconductor device

Abstract

The application provides a semiconductor device manufacturing method, which is applied to the semiconductor field. Specifically, after forming a metal layer with a certain thickness on the surface of a semiconductor substrate and performing a silicification process, a predetermined amount of oxygen with adjustable concentration is introduced, so that the bottom layer of the metal layer reacts with the semiconductor substrate to be converted into a metal silicide layer, and the surface layer of the metal layer reacts with the oxygen to form a metal oxide layer with a certain thickness. Therefore, on the basis of the existing process, without increasing additional steps and additional costs, the metal layer is consumed to the maximum extent, so that the thickness of the formed metal silicide can be flexibly controlled, a metal silicide with a thinner thickness is obtained, and finally the leakage problem of the SOI process with a particularly thin top semiconductor layer is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] SOI (Silicon-On-Insulator) is a rapidly developing integrated circuit process technology with advantages such as low leakage and radiation resistance. The key feature of the SOI process is the presence of a silicon dioxide insulating layer beneath the surface silicon. In recent years, SOI materials, with their unique buried insulating layer structure, can reduce the parasitic capacitance and leakage current of the substrate, and have been widely used in many fields such as low-voltage, low-power, high-temperature, and radiation-resistant devices. The goal and direction of the semiconductor industry has always been to produce smaller and higher-performance devices. As ultra-large-scale integrated circuit technology advances to the 22nm node and below, higher requirements are placed on the feature size of integrated circuits.

[0003] Typically, MOS devices utilize silicon-on-insulator (SOI) technology to achieve lower power and higher speed. However, because the leakage current of MOS devices varies with the ion concentration in the substrate and the gate voltage applied during device manufacturing, in some SOI processes with particularly thin surface silicon, if the thickness of the metal silicide formed during the subsequent process of forming the MOS device's metal silicide is too thick, the upper half of the device will function as a normal MOS transistor, while the lower half will function as a resistor, resulting in leakage current that varies with gate voltage.

[0004] At present, in order to solve the problem of too thick metal silicide, the existing technology usually uses a machine to thin the metal cobalt layer, and the thickness of the corresponding metal silicide layer is also reduced accordingly. However, due to the limited process capabilities of the machines in the existing technology, the thickness of the metal cobalt cannot be further thinned, and the thickness of the metal silicide cannot be obtained. In addition, the use of this thinning method cannot avoid the problem of poor film thickness uniformity caused by thinning the metal cobalt. Especially in the SOI process, the aforementioned thinning method cannot obtain the required thinner metal silicide layer, which leads to unstable contact resistance and serious leakage current of the MOS device, and ultimately causes product failure. Summary of the Invention

[0005] An object of the present invention is to provide a method for manufacturing a semiconductor device to solve at least one of the above technical problems.

[0006] To solve at least one of the above technical problems, the present invention provides a method for manufacturing a semiconductor device, the method comprising:

[0007] S1, providing a semiconductor substrate, wherein at least one discrete gate structure is formed on a surface of the semiconductor substrate, and a drain region and a source region are further provided in the semiconductor substrate on both sides of each gate structure;

[0008] S2, forming a metal layer, wherein the metal layer covers the surface of the gate structure and extends to cover the surface of the semiconductor substrate corresponding to the drain region and the source region;

[0009] S3, performing a first heat treatment on the semiconductor substrate while simultaneously introducing a predetermined amount of oxygen with an adjustable concentration, so that a portion of the surface of the metal layer facing the semiconductor substrate is converted into a metal silicide layer, while a surface of the metal layer facing away from the semiconductor substrate is converted into a metal oxide layer;

[0010] S4, etching the metal oxide layer and the remaining unconverted metal layer to expose the metal silicide layer formed on the top surfaces of the gate structure, the drain region and the source region;

[0011] S5, performing a second heat treatment on the semiconductor substrate.

[0012] Furthermore, the semiconductor substrate may be a silicon-on-insulator substrate having a bottom semiconductor layer, an insulating buried layer, and a top semiconductor layer stacked in sequence from bottom to top.

[0013] Furthermore, the material of the bottom semiconductor layer and the top semiconductor layer may include silicon, and the material of the buried insulating layer may include silicon dioxide.

[0014] Furthermore, the thickness of the top semiconductor layer may be less than

[0015] Furthermore, a sidewall structure may be formed on the surface of the top semiconductor layer, and the sidewall structure covers the sidewall of the gate structure; the metal layer formed in step S2 may also cover the surface of the sidewall structure.

[0016] Furthermore, the etching process for etching the metal oxide layer and the remaining unconverted metal layer in step S4 may be a wet etching process, and the etching solution of the wet etching process may include sulfuric acid.

[0017] Furthermore, the material of the metal layer formed in step S2 may include metal cobalt, and the thickness of the formed metal layer may be in the range of:

[0018] Furthermore, the process of forming the metal layer in step S2 may be a physical vapor deposition process.

[0019] Furthermore, the process of performing the first heat treatment on the semiconductor substrate in step S3 may be a rapid temperature rise annealing process, and the temperature range of the rapid temperature rise annealing process may be: 1000°C to 1100°C.

[0020] Furthermore, the concentration range of the oxygen introduced in step S3 may be 3 L / min to 16 L / min.

[0021] Furthermore, the thickness of the metal silicide layer formed in step S3 may be less than

[0022] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0023] In the manufacturing method of the semiconductor device provided by the present invention, after a metal layer of a certain thickness is formed on the surface of the semiconductor substrate and a silicidation process is performed on it, a predetermined amount of oxygen with an adjustable concentration is introduced so that the bottom layer of the metal layer reacts with the semiconductor substrate to be converted into a metal silicide layer, while the surface layer of the metal layer reacts with the oxygen to form a metal oxide layer of a certain thickness. In this way, on the basis of the existing process and without adding additional steps and additional costs, the metal layer is consumed to the greatest extent, thereby reducing the thickness of the metal silicide layer formed on the top surface of the gate structure and on the top surfaces of the drain region and the source region. That is, based on the process capabilities of the existing machine, by controlling the concentration of the oxygen introduced, the thickness of the formed metal silicide can be flexibly controlled, thereby obtaining a thinner metal silicide.

[0024] In addition, the thickness of the metal silicide can be adjusted at will to meet various process requirements by controlling the concentration of the oxygen introduced. Since the consumption of the excess metal layer is achieved through chemical reaction, the formed metal silicide layer has good thickness stability, which solves the problem of unstable contact resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a flow chart of a method for manufacturing a semiconductor device provided by the present invention;

[0026] Figure 2a to Figure 2d is a schematic structural diagram of a semiconductor device during the manufacturing process according to an embodiment of the present invention;

[0027] The accompanying drawings are numerals as follows:

[0028] 100-bottom semiconductor layer; 110-insulating buried layer;

[0029] 120-top semiconductor layer; 130-sidewall structure;

[0030] 140-metal layer; 251-gate structure;

[0031] 140a-metal silicide layer; 140b-metal oxide layer;

[0032] S-source region; D-drain;

[0033] 140' - Remaining unconverted metal layer. DETAILED DESCRIPTION

[0034] As described in the background art, to address the problem of excessive thickness of the metal silicide formed in MOS devices, existing technologies typically employ a machine to thin the metal silicide, thereby reducing the thickness of the resulting metal silicide layer accordingly. However, due to the limited processing capabilities of existing machines, the thickness of the metal cobalt cannot be further thinned, and thus, a thinner metal silicide cannot be achieved. Furthermore, this thinning method cannot avoid the problem of poor film thickness uniformity caused by thinning the metal cobalt, resulting in unstable contact resistance and severe leakage current in the MOS device, ultimately causing product failure.

[0035] To this end, the present invention provides a method for manufacturing a semiconductor device to solve at least one of the above technical problems.

[0036] refer to Figure 1 , Figure 1 A flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. Specifically, the method for manufacturing a semiconductor device includes the following steps:

[0037] Step S1 : providing a semiconductor substrate, wherein at least one discrete gate structure is formed on the surface of the semiconductor substrate, and a drain region and a source region are further provided in the semiconductor substrate on both sides of each gate structure.

[0038] Step S2 : forming a metal layer, wherein the metal layer covers the surface of the gate structure and extends to cover the surface of the semiconductor substrate corresponding to the drain region and the source region.

[0039] In step S3, the semiconductor substrate is subjected to a first heat treatment, and a predetermined amount of oxygen with an adjustable concentration is introduced at the same time, so that a portion of the metal layer facing the surface of the semiconductor substrate is converted into a metal silicide layer, while the surface of the metal layer facing away from the semiconductor substrate is converted into a metal oxide layer.

[0040] Step S4 , etching the metal oxide layer and the remaining unconverted metal layer to expose the metal silicide layer formed on the top surfaces of the gate structure, the drain region, and the source region.

[0041] Step S5: performing a second heat treatment on the semiconductor substrate.

[0042] That is, in the manufacturing method of the semiconductor device provided by the present invention, after a metal layer of a certain thickness is formed on the surface of the semiconductor substrate and a silicidation process is performed on it, a predetermined amount of oxygen with an adjustable concentration is introduced so that the bottom layer of the metal layer reacts with the semiconductor substrate to be converted into a metal silicide layer, while the surface layer of the metal layer reacts with the oxygen to form a metal oxide layer of a certain thickness. In this way, on the basis of the existing process and without adding additional steps and additional costs, the metal layer is consumed to the maximum extent, thereby reducing the thickness of the metal silicide layer formed on the top surface of the gate structure and on the top surfaces of the drain region and the source region. That is, based on the process capabilities of the existing machine, by controlling the concentration of the oxygen introduced, the thickness of the formed metal silicide can be flexibly controlled, thereby obtaining a metal silicide with a thinner thickness.

[0043] Furthermore, due to the limited process capabilities of existing machines, especially in SOI processes, it is impossible to obtain a thinner metal silicide thickness, and it is even more impossible to avoid the problem of poor film thickness uniformity caused by thinning the metal cobalt. In the SOI process, the thickness of metal silicide can only be controlled at An excessively thick metal silicide layer can lead to severe junction leakage and thus cause product failure.

[0044] To this end, the present invention also provides a method for manufacturing a semiconductor device. The main difference from the previous embodiment is that the semiconductor substrate used in this embodiment is a silicon-on-insulator substrate, which has a bottom semiconductor layer, an insulating buried layer and a top semiconductor layer stacked in sequence from bottom to top.

[0045] As an example, the material of the bottom semiconductor layer and the top semiconductor layer may include silicon, and the material of the buried insulating layer may include silicon dioxide.

[0046] As an example, the thickness of the top semiconductor layer may be less than

[0047] This manufacturing method is based on the process capability of existing machines and has achieved a significant reduction in the thickness of metal silicide. The thickness of metal silicide can be adjusted at will to meet various process requirements without adding additional steps and costs. It has achieved good stability and completely solved the problem of extremely thin surface silicon ( )'s leakage problem in SOI process.

[0048] The following is a further detailed description of the semiconductor device manufacturing method proposed by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0049] Figure 2a to Figure 2d FIG. 1 is a schematic structural diagram of a semiconductor device during a manufacturing process according to an embodiment of the present invention.

[0050] In step S1, refer to Figure 2a As shown, a semiconductor substrate is provided, comprising a bottom semiconductor layer 100, an insulating buried layer 110, and a top semiconductor layer 120 stacked sequentially from bottom to top. A plurality of discrete gate structures 251 are formed on the surface of the top semiconductor layer 120. A drain region D and a source region S are also provided within the top semiconductor layer 120, located on either side of each gate structure 251. The semiconductor substrate is used to provide an operating platform for subsequent processes to generate MOS devices. Exemplarily, the semiconductor substrate may be a silicon-on-insulator substrate, and the materials of the bottom semiconductor layer 100 and the top semiconductor layer 120 may be selected from single crystal silicon, polycrystalline silicon, or amorphous silicon. Of course, the materials of the bottom semiconductor layer 100 and the top semiconductor layer 120 may also be selected from compounds such as silicon, germanium, gallium arsenide, or silicon germanium. Exemplarily, in an embodiment of the present invention, the materials of the bottom semiconductor layer 100 and the top semiconductor layer 120 may include silicon, and the material of the insulating buried layer 110 may include silicon dioxide. Furthermore, a spacer structure 130 is formed on the surface of the top semiconductor layer 120 , and the spacer structure 130 covers the sidewall of the gate structure 251 .

[0051] In this embodiment, a silicon-on-insulator substrate may be provided first, and then a gate oxide layer (not shown), a polysilicon layer (not shown), and a patterned photoresist layer (not shown) may be deposited on the surface of the silicon-on-insulator substrate. The polysilicon layer may be etched using the patterned photoresist layer as a mask to form a gate structure. Subsequently, a spacer material layer may be deposited on the surface of the top semiconductor layer 120 and etched to form a spacer structure. Figure 2a The sidewall structure 130 is shown.

[0052] Wherein, the thickness of the top semiconductor layer 120 is less than Since the top semiconductor layer 120 in the present invention is relatively thin, in the subsequent process of forming MOS devices using existing processes, the deposited metal layer may be too thick and the thickness of the converted metal silicide may be too thick, which may lead to problems such as unstable contact resistance and serious leakage current of the MOS device.

[0053] It is understandable that, in the embodiment of the present invention, for the sake of simplicity, not all steps and layers in the process of forming the MOS device are fully illustrated. Figure 2a The illustrated gate structure 251 does not show the gate oxide layer located above the top semiconductor layer 120 and below the polysilicon layer. Furthermore, to simplify the diagrams, the drawings used in the embodiments of the present invention each illustrate only one gate structure 251. In other embodiments, multiple discrete gate structures may be formed on the semiconductor substrate, and adjacent gate structures may be isolated by shallow trench isolation structures. This is conventional technology and will not be further elaborated in the present invention.

[0054] In step S2, refer to Figure 2b As shown, a metal layer 140 is formed, which covers the surface of the gate structure 251 and extends to cover the surface of the top semiconductor layer 120 corresponding to the drain region D and the source region S. In addition, the metal layer 140 also covers the surface of the spacer structure 130.

[0055] In this embodiment, after step S1, a metal layer 140 having the same thickness as the metal layer required for forming a metal silicide layer in a MOS device in an existing process can be formed on the top semiconductor layer 120 using an existing physical vapor deposition process, and then the following steps S3 to S5 are performed. The material of the metal layer 140 includes metallic cobalt, and the thickness of the formed metal layer 140 can range from: For example, in the existing 8-inch mainstream wafer process, the thickness of the deposited metal layer 140 can be

[0056] It should be noted that, when forming a thickness of After the metal cobalt film layer is formed, the thickness of the corresponding metal silicide is about Therefore, in order to solve the leakage problem of SOI metal silicide, it is usually chosen to reduce the thickness of the metal cobalt film to The thickness of the metal silicide generated by the thinned metal cobalt film is about Limited by the process capability of the 8-inch cobalt metal film physical vapor deposition (PVD) machine, the thickness of the cobalt metal film cannot be further reduced. For some SOI processes with extremely thin surface silicon (<500A), the thickness of the metal silicide The thickness is still too high, which leads to serious junction leakage and further causes product failure. The method provided by the present invention is a solution to this problem.

[0057] In step S3, refer to Figure 2cAs shown, the semiconductor substrate is subjected to a first heat treatment, and a predetermined amount of oxygen with an adjustable concentration is introduced at the same time, so that a portion of the surface of the metal layer 140 facing the top semiconductor layer 120 is converted into a metal silicide layer 140a, while the surface of the metal layer 140 facing away from the top semiconductor layer 140 is converted into a metal oxide layer 140b.

[0058] In this embodiment, the semiconductor substrate can be subjected to an existing rapid temperature rise annealing process, and the temperature range of the rapid temperature rise annealing process is: 1000°C ~ 1100°C, so that the metal layer 140 located on the top surface of the gate structure 251, the drain region D and the source region S and in contact therewith reacts with the polysilicon of the gate structure 251 and the silicon material of the drain region D and the source region S under the action of high temperature to form the following Figure 2c At the same time, in the embodiment of the present invention, while the semiconductor substrate is subjected to the existing rapid temperature annealing process, a certain amount of oxygen with adjustable concentration is introduced according to actual needs to form the metal silicide layer 140a. Figure 2c At the same time as the metal silicide layer 140a shown in FIG. 1 , the surface metal layer of the metal layer 140 facing away from the top semiconductor layer 140 reacts chemically with the oxygen introduced at high temperature to form a Figure 2c The metal oxide layer 140b shown. In addition, in actual operation, the relationship between oxygen concentration and metal silicide can be determined by experiment, and then the appropriate point required by the process can be selected based on the relationship fitted by the experimental results. For example, in an embodiment of the present invention, the concentration range of the oxygen introduced can be: 3L / min to 16L / min. The thickness of the formed metal silicide layer 140a is less than

[0059] In step S4, refer to Figure 2d As shown, the metal oxide layer 140 b and the remaining unconverted metal layer 140 ′ are etched to expose the metal silicide layer 140 a formed on the top surfaces of the gate structure 251 , the drain region D, and the source region S.

[0060] In this embodiment, a dry etching process or a wet etching process can be used to remove the metal oxide layer 140b and the remaining unconverted metal layer 140' to expose the metal silicide layer 140a formed on the top surface of the gate structure 251, the drain region D, and the source region S. For example, in this embodiment of the present invention, the etching process for removing the metal oxide layer 140b and the remaining unconverted metal layer 140' in step S4 can be a wet etching process, and the etching solution of the wet etching process includes sulfuric acid. Since sulfuric acid is a commonly used etching solution for removing photoresist in semiconductor processing and is used multiple times throughout the entire process flow, it does not significantly react with existing structural components such as silicon substrates, polysilicon materials, silicon dioxide materials, and silicon nitride materials. Therefore, in this embodiment of the present invention, using sulfuric acid to etch the metal oxide layer 140b and the remaining unconverted metal layer 140' can remove both, while also avoiding the simultaneous etching of the metal silicide layer 140a and other existing device structures that need to be retained.

[0061] In step S5, continue to refer to Figure 2d As shown, the semiconductor substrate is subjected to a second heat treatment.

[0062] In this embodiment, after etching the metal oxide layer 140b and the remaining unconverted metal layer 140' in step S4, the semiconductor substrate including the gate structure 251 and the metal silicide layer 140a can be subjected to a second heat treatment (high temperature treatment) so that the metal silicide layer 140a exposed in the previous step forms a silicide with lower resistance after the second heat treatment, thereby reducing the contact resistance of the MOS device formed by the manufacturing method of the present invention.

[0063] In summary, in the manufacturing method of the semiconductor device provided by the present invention, after a metal layer of a certain thickness is formed on the surface of the semiconductor substrate and a silicidation process is performed on it, a predetermined amount of oxygen with an adjustable concentration is introduced so that the bottom layer of the metal layer reacts with the semiconductor substrate to be converted into a metal silicide layer, while the surface layer of the metal layer reacts with the oxygen to form a metal oxide layer of a certain thickness. In this way, on the basis of the existing process and without adding additional steps and additional costs, the metal layer is consumed to the maximum extent, thereby reducing the thickness of the metal silicide layer formed on the top surface of the gate structure and on the top surfaces of the drain region and the source region. That is, based on the process capabilities of the existing machine, by controlling the concentration of the oxygen introduced, the thickness of the formed metal silicide can be flexibly controlled, thereby obtaining a thinner metal silicide, and ultimately solving the leakage problem of the SOI process with a particularly thin silicon top semiconductor layer.

[0064] In addition, the thickness of the metal silicide can be adjusted at will to meet various process requirements by controlling the concentration of the oxygen introduced. Since the consumption of the excess metal layer is achieved through chemical reaction, the formed metal silicide layer has good thickness stability, which solves the problem of unstable contact resistance.

[0065] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of protection of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the present invention.

[0066] In addition, it should be understood that, although the terms "first", "second", etc. may be used herein to describe different elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of exemplary embodiments of the present invention, the first element, component, region, layer or part discussed below may also be referred to as the second element, component, region, layer or part.

[0067] For ease of description, spatially relative terms such as "below," "above," "below," "above," "upper," and "lower" may be used herein to describe the spatial positional relationship of an element or feature to other elements or features as shown in the figures. It should be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the drawings is inverted, an element described as "below other elements or features" or "below other elements or features" will be subsequently positioned as "above other elements or features" or "above other elements or features." Thus, the exemplary term "below" may include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly.

[0068] The terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0069] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: S1, providing a semiconductor substrate, wherein at least one discrete gate structure is formed on a surface of the semiconductor substrate, and a drain region and a source region are further provided in the semiconductor substrate on both sides of the gate structure; S2, forming a metal layer, wherein the metal layer covers the surface of the gate structure and extends to cover the surface of the semiconductor substrate corresponding to the drain region and the source region; S3, performing a first heat treatment on the semiconductor substrate while simultaneously introducing a predetermined amount of oxygen with an adjustable concentration, so that a portion of the surface of the metal layer facing the semiconductor substrate is converted into a metal silicide layer, while a surface of the metal layer facing away from the semiconductor substrate is converted into a metal oxide layer; S4, etching the metal oxide layer and the remaining unconverted metal layer to expose the metal silicide layer formed on the top surfaces of the gate structure, the drain region and the source region; S5, performing a second heat treatment on the semiconductor substrate; The semiconductor substrate is a silicon-on-insulator substrate, and the silicon-on-insulator substrate comprises a bottom semiconductor layer, an insulating buried layer, and a top semiconductor layer stacked sequentially from bottom to top; The material of the metal layer formed in step S2 includes metal cobalt, and the thickness of the formed metal layer is in the range of: In step S3, the process of performing the first heat treatment on the semiconductor substrate is a rapid temperature rise annealing process, and the temperature range of the rapid temperature rise annealing process is: 1000° C. to 1100° C.; The concentration range of the oxygen introduced in step S3 is: 3 L / min to 16 L / min.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The bottom semiconductor layer and the top semiconductor layer are made of silicon, and the buried insulating layer is made of silicon dioxide.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The thickness of the top semiconductor layer is less than 4. The method for manufacturing a semiconductor device according to claim 1, wherein: The etching process for etching the metal oxide layer and the remaining unconverted metal layer in step S4 is a wet etching process, and the etching solution of the wet etching process includes sulfuric acid.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The process of forming the metal layer in step S2 is a physical vapor deposition process.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The thickness of the metal silicide layer formed in step S3 is less than

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