Method of manufacturing a semiconductor device

Abstract

The application provides a semiconductor substrate manufacturing method, in which, during STI manufacturing, the height of the isolation groove in the dense area and the empty area after CMP is higher than that of the active area by thickening the silicon nitride, a first bottom anti-reflection layer is formed before the polysilicon etching process, and then the first bottom anti-reflection layer is etched back and planarized to reduce the height difference between the active area in the empty area and the isolation groove, so that the damage to the active area or the residual polysilicon caused by the too large thickness difference of the bottom anti-reflection layer during the polysilicon etching process is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a manufacturing method of semiconductor device. BACKGROUND

[0002] Shallow trench isolation (STI) is a common process for isolation between active areas of transistors fabricated on a substrate. In the process of fabricating STI, a thin layer of silicon nitride is first formed on the surface of the silicon wafer. This layer of silicon nitride serves as a strong mask material throughout the process of forming the shallow trench isolation, which helps to protect the active area during the deposition of the shallow trench isolation oxide. In addition, the silicon nitride can act as a polishing stop layer during the chemical mechanical polishing (CMP) step in the STI process.

[0003] However, using the silicon nitride (SiN) of the active area as the polishing stop layer for the CMP of STI leads to different active area (AA) pattern densities and different step heights between the active area and the isolation area. Typically, the STI in the dense area is higher than the AA, while the AA in the isolated area (ISO) is higher than the STI. As the area of the isolated area STI (AA pattern density < 1%) increases, the step height decreases and tends to be saturated, as shown in FIG. 1. Figure 1

[0004] The difference in the step height between the active area and the isolation area causes the thickness of the BARC (Bottom Anti-Reflective Coating) to be uneven during the subsequent polysilicon etching, as shown in FIG. 2. This results in the BARC in the isolated area (ISO) being too thin, and the etching process being unable to provide sufficient protection for the HM (Hard Mask), which causes over-etching and damages the active area, as shown in FIG. 3. In the dense area, the STI (silicon oxide, OX) is higher than the AA, and the polysilicon (Poly) has a high etching selectivity for the OX during the polysilicon etching, so the surface of the STI is not damaged. If the etching amount is reduced, the polysilicon etching in the dense area will not be complete, and polysilicon residues will be easily left behind, as shown in FIG. 4, which causes short circuiting and failure of the device. Figure 2 Figure 3 Figure 4 SUMMARY

[0005] The present application aims to provide a manufacturing method of semiconductor device, which avoids the damage to the active area or the polysilicon residues caused by the large difference in the thickness of the BARC during the polysilicon etching process.

[0006] To achieve the above-mentioned purpose, the present application provides a manufacturing method of semiconductor device, which comprises the following steps.

[0007] ​​​​A substrate is provided, which includes a first region and a second region;

[0008] An isolation trench process is performed on the substrate to form active regions, wherein the pattern density of the active regions in the first region is less than that of the active regions in the second region, and the isolation trenches in the first region and the second region are both higher than the active regions;

[0009] A first bottom anti-reflective layer is formed on the substrate, and the first bottom anti-reflective layer and part of the isolation trenches are etched back, so that the isolation trenches in the first region are flush with the active regions, and the isolation trenches in the second region are higher than the active regions;

[0010] A polysilicon layer, a hard mask layer and a second bottom anti-reflective layer are sequentially formed on the substrate, and a polysilicon etching process is performed.

[0011] Optionally, the isolation trench process is performed on the substrate to form active regions, which includes:

[0012] A silicon nitride layer is formed on the substrate;

[0013] The substrate is etched to form a trench;

[0014] The trench is filled with isolation oxide;

[0015] A chemical mechanical polishing process is performed on the substrate,

[0016] The remaining silicon nitride layer is removed to form an isolation trench;

[0017] The silicon nitride layer acts as a polishing stop layer, and by controlling the thickness of the silicon nitride layer, the isolation trenches in the first region and the second region are both higher than the active regions.

[0018] Optionally, the thickness of the silicon nitride layer is

[0019] Optionally, the first bottom anti-reflective layer formed in the first region and the second region both has a flat surface, and the thickness of the first bottom anti-reflective layer is

[0020] Optionally, before etching back the first bottom anti-reflective layer and part of the isolation trenches, the first bottom anti-reflective layer is further subjected to a plasma curing process.

[0021] Optionally, during the plasma curing process of the first bottom anti-reflective layer, the process gas used is HBr, the flow rate is 50sccm-150sccm, the power is 800W-1200W, and the processing time is 8s-12s.

[0022] Optionally, the first bottom anti-reflective layer and part of the isolation trench are etched back by a plasma etching process, comprising:

[0023] The first bottom anti-reflective layer and part of the isolation trench are etched back by a first process parameter setting;

[0024] The remaining first bottom anti-reflective layer is removed by a second process parameter setting.

[0025] Optionally, the first process parameter setting comprises controlling the ratio of C and F in the process gas to ensure high selectivity for etching the active region.

[0026] Optionally, the ratio of C and F comprises 1:1-1:2.

[0027] Optionally, the first process parameter setting comprises: the process gas is a mixed gas of CF4, CH3F and He, wherein the flow rate of CF4 is 10-20 sccm, the flow rate of CH3F is 10-20 sccm, the flow rate of He is 200-300 sccm, the power is 500-800 W, the bias power is 50-100 W, and the process time is 20-35 s.

[0028] Optionally, the second process parameter setting comprises: the process gas is O2, the flow rate of O2 is 180-220 sccm, the power is 1150-1250 W, and the process time is 55-65 s.

[0029] In summary, the method for manufacturing a semiconductor substrate provided in the embodiment makes the isolation trench in the dense area and the open area higher than the active region by thickening the silicon nitride during the STI manufacturing process, forms a first bottom anti-reflective layer before the polysilicon etching process, and reduces the height difference between the active region and the isolation trench in the open area by etching back and planarizing the first bottom anti-reflective layer, thereby avoiding the damage to the active region or the residual polysilicon caused by the insufficient blocking ability of the mask layer in the open active region due to the too large difference in the thickness of the bottom anti-reflective layer during the polysilicon etching process. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 A trend chart of the height difference of the active region and the isolation trench (Step height) with the STI area in the open area;

[0031] Figure 2 A cross-sectional view of each film layer in the vertical AA direction before the polysilicon etching;

[0032] Figure 3 A cross-sectional view of the vertical AA direction after the polysilicon etching;

[0033] Figure 4 is a sectional view of the vertical AA direction after polysilicon etching of another embodiment of the present application;

[0034] Figure 5 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0035] Figures 6A to 6F is a structural schematic diagram of each step corresponding to the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0036] Figure 7A is a final effect diagram of the vertical AA direction after polysilicon etching of the empty area;

[0037] Figure 7B is a final effect diagram of the vertical AA direction after polysilicon etching of the dense area;

[0038] In the drawings, reference numerals:

[0039] 100 - substrate; 100a - first area; 100b - second area; 110 - active area; 120 - isolation trench; 101 - silicon nitride layer; 120a - trench; 102 - first bottom anti-reflective layer. DETAILED DESCRIPTION

[0040] In order to make the content of the present application more clear and easy to understand, the content of the present application is further described below in combination with the drawings of the specification. Of course, the present application is not limited to this specific embodiment, and general substitutions well known to those skilled in the art are also covered within the protection scope of the present application.

[0041] Secondly, the present application is described in detail by using a schematic diagram. In the detailed description of the present application, the schematic diagram is partially enlarged without following the general proportion for the sake of convenience of description, and this should not be taken as a limitation of the present application.

[0042] Figure 5 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application, as shown in the figure, the method for manufacturing a semiconductor device according to the present embodiment includes the following steps: Figure 5

[0043] Step S01: providing a substrate, the substrate includes a first area and a second area;

[0044] Step S02: performing an isolation trench process on the substrate to form an active area, wherein the pattern density of the active area of the first area is less than the pattern density of the active area of the second area, and the isolation trenches of the first area and the second area are higher than the active area;

[0045] ​Step S03: forming a first bottom anti-reflective layer on the substrate, etching back the first bottom anti-reflective layer and part of the isolation trenches, so that the isolation trenches in the first region are flush with the active region, and the isolation trenches in the second region are higher than the active region; and

[0046] Step S04: sequentially forming a polysilicon layer, a hard mask layer and a second bottom anti-reflective layer on the substrate, and performing a polysilicon etching process.

[0047] Figures 6A to 6F The structure diagram of each step corresponding to the manufacturing method of the semiconductor device in an embodiment of the present application. Please refer to Figure 5 for details. Figures 6A to 6F The manufacturing method of the semiconductor device is described in detail.

[0048] Referring to Figure 6A , step S01 is performed to provide a substrate 100, which includes a first region 100a and a second region 100b. Specifically, first, a substrate 100 is provided, which can be monocrystalline silicon (Si), monocrystalline germanium (Ge), silicon-germanium (GeSi) or silicon carbide (SiC), or can be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or can also be other materials, such as gallium arsenide and other III-V compound semiconductors. In the present embodiment, the substrate 100 is only taken as an example of using a silicon substrate, which is only an example and the present application is not limited thereto.

[0049] Referring to Figures 6A to 6D , step S02 is performed to perform an isolation trench process on the substrate 100 to form an active region 110, wherein the pattern density of the active region 110 in the first region 100a is less than the pattern density of the active region 110 in the second region 100b, and the isolation trenches 120 in the first region 100a and the second region 100b are both higher than the active region 110.

[0050] In the present embodiment, the isolation trench process is a shallow trench isolation process. The second region 100b is a core device region, and the first region 100a is a peripheral circuit region or a region for forming other semiconductor devices. The size of the isolation trench 120 formed in the first region 100a is greater than the size of the isolation trench 120 formed in the second region 100b, that is, the pattern density of the active region 110 in the first region 100a is less than the pattern density of the active region 110 in the second region 100b. That is, the first region 100a is an empty region (ISO) and the second region 100b is a dense region (Dense).

[0051] To make the isolation trenches 120 in the first region 100a and the second region 100b both higher than the active region 110, in the embodiment, the following isolation trench process is adopted:

[0052] First, a silicon nitride layer 101 is formed on the substrate 100, as shown in FIG. 1B; then, the substrate 100 is etched to form a trench 120a, as shown in FIG. 1C; then, the trench 120a is filled with isolation oxide, for example, silicon oxide; then, the substrate 100 is subjected to a chemical mechanical polishing (CMP) process, as shown in FIG. 1D; then, the remaining silicon nitride layer is removed to form the isolation trench 110, as shown in FIG. 1E. Figure 6A Figure 6B Figure 6C Figure 6D

[0053] The silicon nitride layer 101 serves as a polishing stop layer in the chemical mechanical polishing (CMP) process, and by controlling the thickness of the silicon nitride layer 101, the isolation trenches 120 in the first region 100a and the second region 100b are both made higher than the active region 110. In the embodiment, the silicon nitride layer 101 is thickened based on the existing process. For example, in the embodiment, the thickness of the silicon nitride layer 101 is thickened by The silicon nitride layer 101 is, for example, for example,

[0054] It should be noted that the height of the isolation trench 120 in the embodiment refers to the height of the isolation oxide filled in the trench after the isolation trench is finally formed. In addition, before the silicon nitride layer 101 is formed on the substrate 100 in the process of forming the isolation trench, an oxide layer (not shown in the figure) is also formed on the substrate 100. The oxide layer serves as an isolation layer on the surface of the substrate to protect the active region from chemical contamination in the subsequent process of removing the silicon nitride layer.

[0055] Referring to FIG. 2B, step S03 is performed to form a first bottom anti-reflective layer 102 on the substrate 100, and the first bottom anti-reflective layer 102 and part of the isolation trench 120 are etched back, so that the isolation trench 120 in the first region 100a is flush with the active region 110, and the isolation trench 120 in the second region 100b is higher than the active region 110. Figures 6E to 6F Specifically, first, as shown in FIG. 2B, step S03 is performed to form a first bottom anti-reflective layer 102 on the substrate 100, and the first bottom anti-reflective layer 102 and part of the isolation trench 120 are etched back, so that the isolation trench 120 in the first region 100a is flush with the active region 110, and the isolation trench 120 in the second region 100b is higher than the active region 110.

[0056] Figure 6E ​​​​​As shown, a first bottom anti-reflective coating (BARC) 102 is formed on the substrate 100. Since the isolation trench process is preceded by the thickening of the silicon nitride layer, the first region 100a and the second region 100b form the first bottom anti-reflective coating 102 with a flat surface, which prepares for the subsequent etching back of the first bottom anti-reflective coating (BARC) 102 and the planarization of the wafer surface before the Poly coating. In this embodiment, the thickness of the first bottom anti-reflective coating 102 is 1000A. For example, the thickness of the first bottom anti-reflective coating 102 is 1000A.

[0057] Next, the first bottom anti-reflective coating 102 is subjected to a plasma curing process to make it more resistant to etching and to further strengthen the protection of the low AA. During the plasma curing process of the first bottom anti-reflective coating 102, the process gas used is HBr, the flow rate is 50sccm-150sccm, the power is 800W-1200W, and the processing time is 8s-12s.

[0058] Next, the first bottom anti-reflective coating 102 and part of the isolation trench 120 are etched back, so that the isolation trench 120 in the first region 100a is flush with the active region 110, and the isolation trench 120 in the second region 100b is higher than the active region 110. By etching, the first bottom anti-reflective coating (BARC) 102 is opened, and the etching is preferentially performed on the raised STI region, while the low AA is still protected by the BARC. The etching of the isolation trench makes the AA in the first region 100a flush with the STI, and the step height of the second region 100b remains the same as before the thickening of the silicon nitride layer 102, as shown in Figure 6F .

[0059] In this embodiment, the first bottom anti-reflective coating 102 and part of the isolation trench 120 are etched back using a plasma etching process, which specifically includes:

[0060] The first bottom anti-reflective coating 102 and part of the isolation trench 120 are etched back using the first process parameter setting;

[0061] The remaining first bottom anti-reflective coating 102 is removed using the second process parameter setting.

[0062] The first process parameter setting includes controlling the ratio of C (carbon) and F (fluorine) in the process gas to ensure a high selectivity ratio for etching the active region, using a high CF ratio for gas etching to ensure a high selectivity ratio for AA, and further to prevent etching damage. For example, the ratio of C and F includes 1:1-1:2.

[0063] For example, the first process parameter setting includes: the process gas is a mixed gas of CF4, CH3F and He, wherein the flow rate of CF4 is 10-20sccm, the flow rate of CH3F is 10-20sccm, the flow rate of He is 200-300sccm, the power is 500-800W, the bias power is 50-100W, and the process time is 20-35s. The second process parameter setting includes: the process gas is O2, the flow rate of O2 is 180-220sccm, the power is 1150-1250W, and the process time is 55-65s.

[0064] Reference Figure 2 As shown, step S04 is performed to sequentially form a polysilicon layer Poly, a hard mask layer HM and a second bottom anti-reflective layer BARC on the substrate, and perform a polysilicon etching process. The above-mentioned thickening of the silicon nitride layer and the elimination of the step height between the STI and the AA by the etching back of the first bottom anti-reflective layer make the substrate surface flat before the Poly is coated with glue, expand the polysilicon etching process window, and thus make the BARC coating uniform, so that the active area is neither damaged nor left with polysilicon residues in the sparse and dense regions,

[0065] In summary, the method for manufacturing a semiconductor substrate provided by the embodiment makes the isolation trenches in the sparse and dense regions after CMP higher than the active area by thickening the silicon nitride layer during the STI manufacturing process, forms a first bottom anti-reflective layer before the polysilicon etching process, and reduces the height difference between the active area and the isolation trenches in the sparse region by etching back and flattening the first bottom anti-reflective layer, thereby avoiding the damage to the active area or the polysilicon residues caused by the insufficient blocking ability of the bottom anti-reflective layer in the polysilicon etching process due to the too large difference in the coating thickness of the bottom anti-reflective layer.

[0066] The above description is only a description of the preferred embodiments of the present application and does not limit the scope of the present application in any way. Any modification or change made by a person of ordinary skill in the art based on the above disclosure is within the protection scope of the claims.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The application relates to a semiconductor device manufacturing method. Providing a substrate, which comprises a first region and a second region; Forming active regions on the substrate by an isolation groove process, wherein the pattern density of the active regions in the first region is less than that in the second region, and the isolation grooves in the first region and the second region are higher than the active regions; Forming a first bottom anti-reflection layer on the substrate, and etching back the first bottom anti-reflection layer and part of the isolation grooves, so that the isolation grooves in the first region are flush with the active regions, and the isolation grooves in the second region are higher than the active regions; Forming a polysilicon layer, a hard mask layer and a second bottom anti-reflection layer on the substrate in sequence, and performing a polysilicon etching process.

2. The method of manufacturing a semiconductor device according to claim 1, wherein Forming active regions on the substrate by an isolation groove process, comprising: Forming a silicon nitride layer on the substrate; Etching the substrate to form grooves; Filling the grooves with isolation oxide; Performing a chemical mechanical polishing process on the substrate, Removing the remaining silicon nitride layer to form isolation grooves; The silicon nitride layer serves as a polishing stop layer, and by controlling the thickness of the silicon nitride layer, the isolation grooves in the first region and the second region are higher than the active regions.

3. The method of manufacturing a semiconductor device according to claim 2, wherein The thickness of the silicon nitride layer is 800-1200 angstrom.

4. The method of manufacturing a semiconductor device according to Claim 1, wherein The first bottom anti-reflection layer formed in the first region and the second region has a flat surface, and the thickness of the first bottom anti-reflection layer is 600-1000 angstrom.

5. The method of fabricating a semiconductor device according to Claim 1, wherein Before etching back the first bottom anti-reflection layer and part of the isolation grooves, the first bottom anti-reflection layer is further subjected to plasma solidification treatment.

6. The method of manufacturing a semiconductor device according to claim 5, wherein During the plasma solidification treatment of the first bottom anti-reflection layer, the process gas is HBr, the flow rate is 50-150 sccm, the power is 800-1200 W, and the treatment time is 8-12 s.

7. The method of fabricating a semiconductor device according to Claim 1, wherein The etching back of the first bottom anti-reflection layer and part of the isolation grooves by using plasma etching process comprises: Etching back the first bottom anti-reflection layer and part of the isolation grooves by using first process parameter settings; Removing the remaining first bottom anti-reflection layer by using second process parameter settings.

8. The semiconductor device manufacturing method according to claim 7, wherein The first process parameter settings comprise controlling the ratio of C and F in the process gas to ensure high selectivity of etching the active regions.

9. The method of manufacturing a semiconductor device according to Claim 8, wherein The ratio of C and F is 1:1-1:

2.

10. The method of fabricating a semiconductor device according to Claim 7, wherein The first process parameter settings comprise that the process gas is a mixed gas of CF4, CH3F and He, the flow rate of CF4 is 10-20 sccm, the flow rate of CH3F is 10-20 sccm, the flow rate of He is 200-300 sccm, the power is 500-800 W, the bias power is 50-100 W, and the process time is 20-35 s.

11. The method of manufacturing a semiconductor device according to Claim 10, wherein The second process parameter settings comprise that the process gas is O2, the flow rate of O2 is 180-220 sccm, the power is 1150-1250 W, and the process time is 55-65 s.

Images