A bidirectional thyristor electrostatic protection device with embedded PMOS and a manufacturing method thereof

Abstract

The application discloses a bidirectional silicon controlled rectifier electrostatic protection device embedded with PMOS, which comprises a P-type substrate, an N-type buried layer arranged in the substrate, an N-type deep well arranged above the N-type buried layer, a first P well, a second P well and a first N well arranged in the N-type deep well, and a polycrystalline silicon gate connected with a cathode in the first N well and the second P well to guide current, wherein the polycrystalline silicon gate connected with the cathode can generate an electric field force vertically upward to promote the movement of carriers in the P well, thereby reducing the on-resistance; the P+ in the first N well is short-circuited with the N+ in the first P well, so that a discharge path of ESD current is added on the basis of the traditional bidirectional silicon controlled rectifier electrostatic protection device, and the positive feedback effect of the SCR discharge path can be effectively inhibited; the silicon controlled rectifier electrostatic discharge device has the characteristics of low trigger voltage and high ESD resistance, and can realize high protection level while effectively avoiding the latch-up effect.

Description

TECHNICAL FIELD

[0001] The application relates to the field of electrostatic protection, in particular to a bidirectional thyristor electrostatic protection device with embedded PMOS and a manufacturing method thereof. BACKGROUND

[0002] With the progress of semiconductor process technology, ESD is one of the key factors affecting the reliability of integrated circuit chips. ESD causes the world's electronic industry to suffer billions of dollars in losses in IC yield and early field failure every year. The chip failure caused by ESD accounts for more than 12% of the total chip failure. The ESD design window is a problem that product engineers need to consider when designing ESD protection, including trigger voltage V t1 , trigger current I t1 , holding voltage V h , holding current I h , failure voltage V t2 , failure current I t2 , and on-resistance R on . The trigger voltage of the ESD protection device is less than the maximum voltage of the protected port of the core circuit, that is, the drain-source breakdown voltage, and the trigger voltage is usually 10% to 20% lower than the maximum voltage. The holding voltage of the ESD protection device is higher than 1.1 to 1.2 times the normal working voltage of the core circuit, so as to protect the core circuit from being unable to turn off and forming a latch due to the ESD protection device always being on. The failure current I t2 of the ESD protection device is one of the important parameters for measuring the robustness of the ESD protection device, indicating the maximum current that the ESD protection device can withstand. In order to effectively protect the core circuit, the clamping voltage of the ESD protection device should be less than the maximum voltage of the protected port when the failure current I t2 is reached. The on-resistance R on of the ESD protection device is the resistance characteristic after the device enters the holding point, which is related to the holding voltage V h , the holding current I h , the failure voltage V t2 , and the failure current I t2 . According to Ohm's law, the on-resistance R on is represented as the ratio of the difference between the failure voltage V t2 and the holding voltage V h to the difference between the failure current I t2 and the holding current I h . The human body model HBM regards the equivalent resistance of the human body as 1.5 kΩ, and the HBM protection level is 1500 times I t2 .

[0003] The failure modes caused by ESD are hard failure, soft failure and latent failure. The causes of these failures can be divided into electrical failure and thermal failure. The thermal failure refers to that when the ESD pulse comes, several amperes to several tens of amperes of current is generated in the local chip, the duration is short but a large amount of heat is generated to make the local metal connection melt or cause the chip to generate hot spots, thereby causing secondary breakdown. The electrical failure refers to that the electric field strength formed by the voltage applied to the gate oxide layer is greater than the dielectric strength, so that the surface is broken down or the dielectric is broken down. As the threat of ESD to the chip is more and more serious, the physical mechanism research is more and more valued.

[0004] Compared with other ESD devices, the traditional thyristor device has a double-conductance modulation mechanism, high unit area discharge efficiency, small unit parasitic capacitance and best robustness. However, due to the high trigger voltage and low holding voltage, latch-up is easily caused, which needs to be considered in the design. The bidirectional thyristor device is improved on the basis of the traditional thyristor and can be considered as an integration of some anti-parallel connected ordinary thyristors. The working principle is the same as that of the traditional unidirectional thyristor, and the voltage can be clamped in the positive and negative directions, respectively.

[0005] The cross-sectional view of the traditional bidirectional SCR static protection device is shown in Figure 1 , and the equivalent circuit diagram is shown in Figure 2 . When the ESD pulse is applied to the anode of the bidirectional SCR, the N-type deep well and the third P+ implantation region form a reverse-biased PN junction. When the pulse voltage is higher than the avalanche breakdown voltage of the PN junction, a large amount of avalanche current is generated in the device, and the current flow path is from the second P-well parasitic resistance to the other end, i.e. the cathode. When the voltage across the parasitic well resistance is higher than the forward conduction voltage of the collector-base junction of the vertical NPN transistor (formed by the second P-well and the second N+ implantation), the transistor is turned on. After the transistor is turned on, the base current is provided for the horizontal PNP transistor, and the horizontal PNP transistor is also turned on to provide the base current for the vertical NPN transistor, forming a positive feedback loop. Therefore, even without avalanche current, the static electricity can be discharged due to the conduction of the transistor. The bidirectional SCR is a symmetrical structure, and when the cathode appears the ESD pulse, the PN junction avalanche breakdown of the N-type deep well and the second P+ implantation region causes the PNP transistor and the NPN transistor to be turned on in sequence to discharge the static electricity. However, the SCR has a high trigger voltage and a low holding voltage, which is easy to exceed the design window and cause latch-up, so the holding voltage needs to be improved. However, the method of improving the holding voltage will reduce the robustness of the device, so the robustness needs to be considered. SUMMARY

[0006] In order to solve the above technical problems, the application provides a bidirectional thyristor static protection device with embedded PMOS and a manufacturing method thereof.

[0007] The technical scheme for solving the above problems of the application is:

[0008] In a first aspect, the application provides a bidirectional thyristor static protection device with embedded PMOS, comprising a P-type substrate; an N-type buried layer is arranged in the substrate; an N-type deep well is arranged above the N-type buried layer; a first N well, a first P well and a second P well are arranged on the N-type deep well; the first P well, the first N well and the second P well are sequentially arranged from left to right on the N-type deep well; a first P+ implantation, a first N+ implantation, a second P+ implantation and a second N+ implantation are sequentially arranged from left to right on the first P well; a third P+ implantation is arranged on the first N well; a fourth P+ implantation and a third N+ implantation are sequentially arranged from left to right on the second P well; and a first gate is arranged between the first N well and the second P well.

[0009] The first P+ implantation and the second P+ implantation in the first P well are connected together and serve as an anode of the device; the third N+ implantation in the second P well is connected together with the first gate and serves as a cathode of the device; the first N+ implantation in the first P well and the fourth P+ implantation in the second P well are connected together by a metal wire and are not connected to a potential; and the second N+ implantation in the first P well and the third P+ implantation in the first N well are connected together by a metal wire and are not connected to a potential.

[0010] Preferably, there are seven field oxide isolation regions; the first field oxide isolation region is between the left side of the first P+ implantation region and the left side edge of the P-type substrate, the second field oxide isolation region is between the first P+ implantation region and the first N+ implantation region, the third field oxide isolation region is between the first N+ implantation region and the second P+ implantation region, the fourth field oxide isolation region is between the second P+ implantation region and the second N+ implantation region, the fifth field oxide isolation region is between the second N+ implantation region and the third P+ implantation region, the sixth field oxide isolation region is between the fourth P+ implantation region and the third N+ implantation region, and the seventh field oxide isolation region is between the third N+ implantation region and the right side edge of the P-type substrate.

[0011] Preferably, the first field oxide isolation region is located on the surface of the left side edge of the P-type substrate; the second field oxide isolation region, the third field oxide isolation region, the fourth field oxide isolation region and the fifth field oxide isolation region are located on the surface of the first P well; the sixth field oxide isolation region is located on the surface of the second P well; and the seventh field oxide isolation region is located on the surface of the right side edge of the P-type substrate.

[0012] Preferably, when the ESD pulse reaches the anode of the device, the cathode of the device is connected to a low potential, the trigger current of the device flows from the anode, sequentially through the first P+ implant in the first P-well, the second P+ implant, the first N+ implant in the first N-well, and the fourth P+ implant in the second P-well, the third N+ implant, and finally out of the cathode. The first P-well / first N-well / first P-well forms a parasitic PNP transistor, and the third N+ implant in the first N-well / second P-well / second P-well forms a parasitic NPN transistor. When the PNP and NPN are turned on, a forward SCR path is formed, and the breakdown surface is between the first N-well and the second P-well.

[0013] Preferably, when the ESD pulse reaches the cathode of the device, the anode of the device is connected to a low potential, the third N+ implant in the second P-well / second P-well / first N-well forms a parasitic NPN transistor, and the second P-well / first N-well / first P-well forms a parasitic PNP transistor. When the PNP and NPN are turned on, a reverse SCR path is formed, and the breakdown surface is between the first N-well and the first P-well.

[0014] Preferably, when the ESD pulse reaches the anode of the device, the cathode of the device is connected to a low potential, the third P+ implant in the first N-well and the fourth P+ implant in the second P-well form a PMOS with the polysilicon gate, which generates a vertical upward electric field force on the cathode polysilicon gate, promotes the movement of carriers in the second P-well, reduces the resistivity of the local area, effectively reduces the on-resistance of the device, and the direction of the electric field force is the same as the direction of the SCR structure discharge current path, so as to promote the formation of the SCR path.

[0015] Preferably, the first P+ implant, the second P+ implant, the first N+ implant in the first P-well, and the fourth P+ implant, the third N+ implant in the second P-well form two forward diodes, which trigger the SCR through the series connection of the diodes, and reduce the trigger voltage of the device.

[0016] Preferably, the PMOS formed by the third P+ implant in the first N-well and the fourth P+ implant in the second P-well can form a path for the second N+ implant in the first P-well and the fourth P+ implant in the second P-well, thereby reducing the current gain coefficient β and improving the holding voltage of the device.

[0017] In a second aspect, an embodiment of the present application provides a manufacturing method of a bidirectional electrostatic protection device embedded with a PMOS, comprising the following steps:

[0018] Step one: forming an N-type buried layer in a P-type substrate;

[0019] Step two: generating an N-type deep well above the N-type buried layer;

[0020] Step three: generating a first P well, a second P well and a second N well in the first N deep well;

[0021] Step four: generating a first P+ injection, a first N+ injection, a second P+ injection and a second N+ injection in the first P well from left to right in sequence, generating a third P+ injection in the first N well, generating a fourth P+ injection and a third N+ injection in the second P well from left to right in sequence, and generating a first gate between the first N well and the second P well;

[0022] Step five: forming a first field oxide isolation region between the left side of the first P+ injection region and the left side edge of the P type substrate, a second field oxide isolation region between the first P+ injection region and the first N+ injection region, a third field oxide isolation region between the first N+ injection region and the second P+ injection region, a fourth field oxide isolation region between the second P+ injection region and the second N+ injection region, a fifth field oxide isolation region between the second N+ injection region and the third P+ injection region, a sixth field oxide isolation region between the fourth P+ injection region and the third N+ injection region, and a seventh field oxide isolation region between the third N+ injection region and the right side edge of the P type substrate;

[0023] Step six: performing annealing treatment on all injection regions to eliminate impurity migration in the injection regions;

[0024] Step seven: connecting the first P+ injection and the second P+ injection in the first P well together and taking them as an anode of the device, connecting the third N+ injection in the second P well and the first gate together and taking them as a cathode of the device, connecting the first N+ injection in the first P well and the fourth P+ injection in the second P well together without connecting an electric potential, and connecting the second N+ injection in the first P well and the third P+ injection in the first N well together without connecting an electric potential.

[0025] Preferably, before forming the N buried layer in the P type substrate, the method further comprises the following steps of:

[0026] forming a silicon dioxide thin film on the P type substrate, then depositing a silicon nitride layer, spin-coating a photoresist layer on the wafer, performing exposure and development on the photoresist layer with a mask to form an isolation shallow trench, etching the silicon dioxide, the silicon nitride and the isolation shallow trench, removing the photoresist layer, depositing a silicon dioxide layer, and then performing chemical mechanical polishing until the silicon nitride layer is removed.

[0027] The present application has the following advantages:

[0028] 1. Two forward diodes are formed by the first P+ injection, the second P+ injection, the first N+ injection in the first P well and the fourth P+ injection, the third N+ injection in the second P well, and the diodes are connected in series to trigger the SCR, thereby reducing the trigger voltage of the device.

[0029] 2. In order to better play the performance of the bidirectional thyristor, the third P+ implantation in the first N well and the fourth P+ implantation in the second P well and the polysilicon gate form a PMOS, the cathode polysilicon gate generates a vertical upward electric field force, promotes the movement of the carrier in the second P well, reduces the resistivity of the local area, effectively reduces the on-resistance of the device, and the direction of the electric field force is the same as the direction of the SCR structure discharge current path, so as to promote the formation of the SCR path.

[0030] 3. The PMOS formed by the third P+ implantation in the first N well and the fourth P+ implantation in the second P well and the polysilicon gate can make the second N+ implantation in the first P well and the fourth P+ implantation in the second P well form a path, thereby reducing the current gain coefficient β and improving the holding voltage of the device. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 is a sectional view of a conventional bidirectional SCR static protection device;

[0032] Figure 2 is an equivalent circuit diagram of a conventional bidirectional SCR static protection device;

[0033] Figure 3 is a sectional view of an embodiment of the application;

[0034] Figure 4 is an equivalent circuit diagram of an embodiment of the application;

[0035] Figure 5 is a total current density distribution simulation diagram of a bidirectional thyristor static protection device with embedded PMOS provided by an embodiment of the application. DETAILED DESCRIPTION

[0036] The application will be further described below in combination with the drawings and embodiments.

[0037] As Figure 3As shown, a bidirectional thyristor electrostatic protection device with embedded PMOS includes a P-type substrate 101; the substrate is provided with an N-type buried layer 201; the N-type buried layer 201 is provided with an N-type deep well 301 above; the N-type deep well 301 is sequentially provided with a first P well 401, a first N well 402 and a second P well 403 from left to right; the first P well 401 is sequentially provided with a first P+ implantation 501, a first N+ implantation 502, a second P+ implantation 503 and a second N+ implantation 504 from left to right; the first N well 402 is provided with a third P+ implantation 505; the second P well 403 is sequentially provided with a fourth P+ implantation 506 and a third N+ implantation 507 from left to right; the first gate 701 is between the first N well 402 and the second P well 403; the first P+ implantation 501 and the second P+ implantation 503 in the first P well 401 are connected together and serve as an anode of the device; the third N+ implantation 507 in the second P well 403 and the first gate 701 are connected together and serve as a cathode of the device; the first N+ implantation 502 in the first P well 401 and the fourth P+ implantation 506 in the second P well 403 are connected together by a metal line and are not connected to a potential; the second N+ implantation 504 in the first P well 401 and the third P+ implantation 505 in the first N well 402 are connected together by a metal line and are not connected to a potential; in this way, the device can discharge part of the current in the SCR path through the path formed by the third P+ implantation in the first N well, the fourth P+ implantation in the second P well and the PMOS formed by the polysilicon gate, which will suppress the positive feedback effect in the original SCR path and thus improve the holding voltage.

[0038] In an embodiment, the bidirectional thyristor electrostatic protection device with embedded PMOS has seven field oxide isolation regions; a first field oxide isolation region 601 is between the first P+ implantation region 501 and the left edge of the P-type substrate 101, a second field oxide isolation region 602 is between the first P+ implantation region 501 and the first N+ implantation region 502, a third field oxide isolation region 603 is between the first N+ implantation region 502 and the second P+ implantation region 503, a fourth field oxide isolation region 604 is between the second P+ implantation region 503 and the second N+ implantation region 504, a fifth field oxide isolation region 605 is between the second N+ implantation region 504 and the third P+ implantation region 505, a sixth field oxide isolation region 606 is between the fourth P+ implantation region 506 and the third N+ implantation region 507, and a seventh field oxide isolation region 607 is between the third N+ implantation region 507 and the right edge of the P-type substrate 101.

[0039] In one embodiment, the first field oxygen isolation region 601 is located on the left edge surface of the P-type substrate 101; the second field oxygen isolation region 602, the third field oxygen isolation region 603, the fourth field oxygen isolation region 604, and the fifth field oxygen isolation region 605 are located on the surface of the first P-well 401; the sixth field oxygen isolation region 606 is located on the surface of the second P-well 403; and the seventh field oxygen isolation region 607 is located on the right edge surface of the P-type substrate 101.

[0040] In one implementation, such as Figure 4 As shown, when the ESD pulse reaches the anode of the device and the cathode is connected to a low potential, the trigger current enters from the anode, passes sequentially through the first P+ injection 501, the second P+ injection 503, the first N+ injection 502 in the first P-well 401, and the fourth P+ injection 506 and the third N+ injection 507 in the second P-well 403, and finally flows out from the cathode. The first P-well 401 / first N-well 402 / first P-well 403 constitute a parasitic transistor PNP, and the first N-well 402 / second P-well 403 / third N+ injection 507 in the second P-well 403 constitute a parasitic transistor NPN. When the PNP and NPN are turned on, a forward SCR path is formed, and its breakdown surface is between the first N-well 402 and the second P-well 403.

[0041] When the ESD pulse reaches the cathode of the device and the anode of the device is connected to a low potential, the third N+ injection 507 in the second P-well 403 / the second P-well 403 / the first N-well 402 forms a parasitic transistor NPN, and the second P-well 403 / the first N-well 402 / the first P-well 401 forms a parasitic transistor PNP. When the PNP and NPN are turned on, they form a reverse SCR path, and its breakdown surface is between the first N-well 402 and the first P-well 401.

[0042] When the ESD pulse reaches the anode of the device and the cathode is grounded, the first P+ injection 501, the second P+ injection 503, the first N+ injection 502 in the first P-well 401, and the fourth P+ injection 506 and the third N+ injection 507 in the second P-well 403 form two forward diodes. These diodes trigger the SCR, reducing the device's trigger voltage. The third P+ injection 505 in the first N-well 402 and the fourth P+ injection 506 in the second P-well 403, together with the polysilicon gate 701, form a PMOS. This allows the second N+ injection 504 in the first P-well 401 and the fourth P+ injection 506 in the second P-well 403 to form a path, thereby reducing the current gain coefficient β and increasing the device's sustaining voltage.

[0043] The device can meet the requirements of ESD design window in different application scenarios, by controlling the width of S1 in N well 402, when the S1 channel length is appropriately increased, the ESD resistance of the device is improved, the width of S2 in the second P well 403 is controlled, the S2 in the cathode polysilicon gate generates a vertical upward electric field force, which promotes the movement of carriers in the second P well, reduces the resistivity of the local area, effectively reduces the on-resistance of the device, and the direction of the electric field force is the same as the direction of the SCR structure discharge current path, which can promote the formation of the SCR path.

[0044] The embodiment of the present application also provides a manufacturing method of the embedded PMOS bidirectional thyristor static protection device, comprising the following steps:

[0045] Step one: forming an N-type buried layer 201 in a P-type substrate 101;

[0046] Step two: generating an N-type deep well 301 above the N-type buried layer 201;

[0047] Step three: generating a first P well 401, a first N well 402 and a second P well 403 in the first N-type deep well 301;

[0048] Step four: generating a first P+ implantation 501, a first N+ implantation 502, a second P+ implantation 503 and a second N+ implantation 504 on the first P well 401 from left to right; generating a third P+ implantation 505 on the first N well 402; generating a fourth P+ implantation 506 and a third N+ implantation 507 on the second P well 403 from left to right; and generating a first gate 701 between the first N well 402 and the second P well 403;

[0049] Step five: generating a first field oxide isolation region 601 between the first P+ implantation region 501 and the left edge of the P-type substrate 101, a second field oxide isolation region 602 between the first P+ implantation region 501 and the first N+ implantation region 502, a third field oxide isolation region 603 between the first N+ implantation region 502 and the second P+ implantation region 503, a fourth field oxide isolation region 604 between the second P+ implantation region 503 and the second N+ implantation region 504, a fifth field oxide isolation region 605 between the second N+ implantation region 504 and the third P+ implantation region 505, a sixth field oxide isolation region 606 between the fourth P+ implantation region 506 and the third N+ implantation region 507, and a seventh field oxide isolation region 607 between the third N+ implantation region 507 and the right edge of the P-type substrate 101;

[0050] Step six: performing annealing treatment on all implantation regions to eliminate the migration of impurities in the implantation regions;

[0051] Step seven: the first P+ injection 501, the second P+ injection 503 in the first P well 401 are connected together and used as the anode of the device; the third N+ injection 507 in the second P well 403 is connected with the first gate 701 together and used as the cathode of the device; the first N+ injection 502 in the first P well 401 and the fourth P+ injection 506 in the second P well 403 are connected together through a metal wire and not connected with potential; the second N+ injection 504 in the first P well 401 and the third P+ injection 505 in the first N well 402 are connected together through a metal wire and not connected with potential.

[0052] The manufacturing method of the bidirectional thyristor electrostatic protection device with embedded PMOS is simple in process and convenient in operation. In order to better play the performance of the bidirectional thyristor, the PMOS structure introduced in the application generates a new surface path to weaken the positive feedback effect of the SCR path, thereby inhibiting the latch-up effect and effectively improving the protection performance and failure level of the device. The device in the embodiment of the application adopts a 0.25 μm BCDMOS process.

[0053] The above only describes the preferred embodiments of the application and is not used to limit the protection scope of the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall be included in the protection scope of the application.

Claims

1. A bidirectional silicon-controlled electrostatic discharge (SSD) device with embedded PMOS, characterized in that: Including P-type substrates; The substrate has an N-type buried layer; Above the N-type buried layer is an N-type deep well; The N-type deep well is provided with a first N-well, a first P-well, and a second P-well; The N-type deep well is provided with a first P-well, a first N-well, and a second P-well from left to right; the first P-well is provided with a first P+ injection, a first N+ injection, a second P+ injection, and a second N+ injection from left to right; The first N-well is provided with a third P+ injection; the second P-well is provided with a fourth P+ injection and a third N+ injection from left to right. The first gate is laterally connected across the junction region of the first N-well and the second P-well, and is connected to the cathode; The first P+ injection and the second P+ injection electrodes in the first P-well are connected together and serve as the anode of the device. The third N+ injection in the second P-well is connected to the first gate to serve as the cathode of the device; The first N+ injection in the first P-well and the fourth P+ injection in the second P-well are connected together by a metal wire, without being connected to a potential, forming the first shunt path; The second N+ injection in the first P-well and the third P+ injection in the first N-well are connected together by a metal wire, without being connected to a potential, forming a second shunt path; The third P+ injection is located in the first N-well and the fourth P+ injection is located in the second P-well, which together with the first gate form a PMOS structure.

2. The bidirectional thyristor electrostatic discharge (ESD) device with embedded PMOS according to claim 1, characterized in that: There are seven field oxygen isolation regions; the first field oxygen isolation region is between the left side of the first P+ implantation region and the left edge of the P-type substrate; the second field oxygen isolation region is between the first P+ implantation region and the first N+ implantation region; the third field oxygen isolation region is between the first N+ implantation region and the second P+ implantation region; the fourth field oxygen isolation region is between the second P+ implantation region and the second N+ implantation region; the fifth field oxygen isolation region is between the second N+ implantation region and the third P+ implantation region; the sixth field oxygen isolation region is between the fourth P+ implantation region and the third N+ implantation region; and the seventh field oxygen isolation region is between the third N+ implantation region and the right edge of the P-type substrate.

3. The bidirectional thyristor electrostatic discharge (ESD) device with embedded PMOS according to claim 2, characterized in that: The first field oxygen isolation region is located on the left edge surface of the P-type substrate; the second, third, fourth, and fifth field oxygen isolation regions are located on the surface of the first P-well; the sixth field oxygen isolation region is located on the surface of the second P-well; and the seventh field oxygen isolation region is located on the right edge surface of the P-type substrate.

4. The bidirectional thyristor electrostatic discharge (ESD) device with embedded PMOS according to claim 1, characterized in that: When the ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its trigger current will enter from the anode, pass through the first P+ injection, the second P+ injection, the first N+ injection in the first P-well, and the fourth P+ injection and the third N+ injection in the second P-well in sequence, and finally flow out from the cathode. The first P-well / first N-well / first P-well constitutes a parasitic transistor PNP. The third N+ injection in the first N-well / second P-well / second P-well constitutes a parasitic transistor NPN. When the PNP and NPN are turned on, they form a forward SCR path, and their breakdown surface is between the first N-well and the second P-well.

5. The bidirectional thyristor electrostatic discharge (ESD) device with embedded PMOS according to claim 1, characterized in that: When the ESD pulse reaches the cathode of the device and the anode of the device is connected to a low potential, the third N+ injection in the second P well / the second P well / the first N well form a parasitic transistor NPN, and the second P well / the first N well / the first P well form a parasitic transistor PNP. When the PNP and NPN are turned on, they form a reverse SCR path, and its breakdown surface is between the first N well and the first P well.

6. The bidirectional thyristor electrostatic discharge (ESD) device with embedded PMOS according to claim 1, characterized in that: When the ESD pulse reaches the anode of the device and the cathode is grounded, the third P+ injection in the first N-well and the fourth P+ injection in the second P-well, together with the polysilicon gate, form a PMOS. The polysilicon gate connected to the cathode generates a vertically upward electric field, which promotes the movement of charge carriers in the second P-well, reduces the resistivity of the local area, effectively reduces the on-resistance of the device, and the direction of the electric field is the same as the direction of the discharge current path of the SCR structure, thus promoting the formation of the SCR path.

7. The bidirectional thyristor electrostatic discharge (ESD) device with embedded PMOS according to claim 1, characterized in that: The first P+ injection, the second P+ injection, the first N+ injection in the first P-well, and the fourth P+ injection and the third N+ injection in the second P-well form two forward diodes, which trigger the SCR through the series diodes, thereby reducing the trigger voltage of the device.

8. The bidirectional thyristor electrostatic discharge (ESD) device with embedded PMOS according to claim 1, characterized in that: The PMOS formed by the third P+ injection in the first N-well, the fourth P+ injection in the second P-well, and the polysilicon gate allows the second N+ injection in the first P-well and the fourth P+ injection in the second P-well to form a path, thereby reducing the current gain coefficient β and increasing the device's sustaining voltage.

9. A method for fabricating a bidirectional PMOS-embedded silicon-controlled electrostatic discharge (SSD) device according to any one of claims 1-8, comprising the following steps: Step 1: Form an N-type buried layer in a P-type substrate; Step 2: Generate an N-type deep well above the N-type buried layer; Step 3: Generate the first P-well, the second P-well, and the second N-well within the first type N deep well; Step 4: Generate the first P+ injection, the first N+ injection, the second P+ injection, and the second N+ injection sequentially from left to right on the first P-well; A third P+ injection is generated on the first N-well; A fourth P+ implant and a third N+ implant are generated sequentially from left to right on the second P-well; a first gate is generated between the first N-well and the second P-well. Step 5: Form a first field oxygen isolation region between the left side of the first P+ implantation region and the left edge of the P-type substrate; form a second field oxygen isolation region between the first P+ implantation region and the first N+ implantation region; form a third field oxygen isolation region between the first N+ implantation region and the second P+ implantation region; form a fourth field oxygen isolation region between the second P+ implantation region and the second N+ implantation region; form a fifth field oxygen isolation region between the second N+ implantation region and the third P+ implantation region; form a sixth field oxygen isolation region between the fourth P+ implantation region and the third N+ implantation region; and form a seventh field oxygen isolation region between the third N+ implantation region and the right edge of the P-type substrate. Step 6: Anneal all injection zones to eliminate the migration of impurities within the injection zones; Step 7: Connect the first P+ implant and the second P+ implant in the first P well together as the anode of the device, and connect the third N+ implant in the second P well together with the first gate as the cathode of the device. The first N+ injection in the first P-well is connected to the fourth P+ injection in the second P-well, but they are not connected to a potential. The second N+ injection in the first P-well is connected to the third P+ injection in the first N-well, but they are not connected to a potential.

10. A method for fabricating a bidirectional thyristor electrostatic discharge (ESD) device with embedded PMOS according to claim 9, characterized in that, Before step one, the following steps are also included: growing a silicon dioxide thin film on a P-type substrate, followed by depositing a silicon nitride layer; spin-coating a photoresist layer onto a wafer, exposing and developing it with a mask to form a shallow isolation trench; etching the silicon dioxide, silicon nitride, and shallow isolation trench to remove the photoresist layer, depositing a silicon dioxide layer, and then performing chemical polishing until the silicon nitride layer is removed.

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