Semiconductor device and method of forming the same

Abstract

A semiconductor device and a forming method thereof, the method can include: providing a semiconductor substrate; forming a first N-type material layer and at least two layers of isolation material layers covering the semiconductor substrate; etching the isolation material layers and the first N-type material layer to obtain an etching groove, and exposing an ion implantation region of a surface of the semiconductor substrate; implanting N-type doping ions to the ion implantation region; forming a first epitaxial layer on a surface of the ion implantation region; forming a second epitaxial layer on a surface of the first epitaxial layer; and forming an N-type material structure covering the second epitaxial layer. The present application can form a self-aligned structure, which is conducive to improving the performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for forming the same. Background Technology

[0002] In the fabrication of modern compound semiconductor devices, various techniques are employed to improve the high-frequency or high-power characteristics of the devices. For example, in order to reduce the characteristic frequency (fT) and maximum characteristic frequency (fmax) in high-frequency radio frequency (RF) devices, it is necessary to reduce various parasitic resistances and capacitances in the devices.

[0003] Taking the heterojunction bipolar transistor (HBT) in high-frequency radio frequency (RF) devices as an example, it adopts a vertical mesa structure, and the distance between the base, emitter and collector is relatively close, resulting in a large parasitic capacitance.

[0004] In the existing technology, there is a problem of insufficient alignment accuracy in the process of forming the base (B), emitter (E) and collector (C). This can easily lead to incorrect proximity between the base, emitter and collector due to alignment differences. On the one hand, this limits the further reduction of the size of semiconductor devices, and on the other hand, it causes the capacitance of the EB junction between the emitter and collector to be too high, which limits the high frequency characteristics of HBT. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor device and a method for forming the same, which can form a self-aligned structure and is beneficial to improving the performance of the semiconductor device.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor device, comprising: providing a semiconductor substrate; forming a first N-type material layer and at least two isolation material layers covering the semiconductor substrate; etching the isolation material layers and the first N-type material layer to obtain etching trenches and exposing an ion implantation region on the surface of the semiconductor substrate; implanting N-type doped ions into the ion implantation region; forming a first epitaxial layer on the surface of the ion implantation region; forming a second epitaxial layer on the surface of the first epitaxial layer; and forming an N-type material structure, the N-type material structure covering the second epitaxial layer.

[0007] Optionally, the semiconductor device is an HBT device; implanting N-type doped ions into the ion implantation region includes: implanting N-type doped ions into the ion implantation region to form the collector doped region of the HBT device; wherein, the N-type material structure is used to form the emitter of the HBT device.

[0008] Optionally, each isolation material layer comprises a stack of isolation layers and etch stop layers; forming a first N-type material layer and at least two isolation material layers covering the semiconductor substrate, etching the isolation material layer and the first N-type material layer to obtain an etch trench and expose the ion implantation region on the surface of the semiconductor substrate, comprising: using a patterned first mask layer to etch the isolation material layer and the first N-type material layer to obtain the etch trench; forming a sacrificial isolation layer covering the isolation material layer and the sidewall surface of the etch trench; and removing the sacrificial isolation layer from the surface of the isolation material layer.

[0009] Optionally, before etching the isolation material layer and the first N-type material layer using a patterned first mask layer, the method further includes: sequentially forming a bottom etch stop layer, the first N-type material layer, and at least two layers of the isolation material layer on the surface of the semiconductor substrate.

[0010] Optionally, the method further includes: removing the underlying etch stop layer on the surface of the ion implantation region to expose the ion implantation region.

[0011] Optionally, one or more of the following conditions must be met: the material of the isolation layer and / or the sacrificial isolation layer is selected from silicon nitride; the material of the etch stop layer and / or the bottom etch stop layer is selected from silicon oxide.

[0012] Optionally, forming a first epitaxial layer on the surface of the ion implantation region includes: forming an N-type epitaxial material layer on the surface of the ion implantation region using a first epitaxial layer formation process.

[0013] Optionally, the material of the N-type epitaxial material layer is selected from: N-type polycrystalline silicon, N-type EPI, and N-type monocrystalline silicon.

[0014] Optionally, forming a second epitaxial layer on the surface of the first epitaxial layer includes: forming a P-type epitaxial material layer on the surface of the first epitaxial layer using a second epitaxial layer forming process.

[0015] Optionally, the material of the P-type epitaxial layer is selected from: P-type silicon germanide.

[0016] Optionally, before forming the second epitaxial layer on the surface of the first epitaxial layer, the method further includes: removing at least one layer of insulating material to expose the surface of the insulating material layer adjacent to the first N-type material layer.

[0017] Optionally, after forming the second epitaxial layer on the surface of the first epitaxial layer and before forming the N-type material structure, the method further includes: forming a protective layer that covers the surface of the second epitaxial layer, the sidewall surface of the etched trench, and the surface of the isolation material layer adjacent to the first N-type material layer; etching the protective layer with the second epitaxial layer as an etching stop layer to retain the protective layer on the sidewall surface of the etched trench and expose the isolation material layer adjacent to the first N-type material layer.

[0018] Optionally, the material of the protective layer is selected from: a stack of silicon oxide and silicon nitride, silicon oxide, and silicon nitride.

[0019] Optionally, forming the N-type material structure includes: forming a second N-type material layer, the second N-type material layer covering the second epitaxial layer; using a patterned second mask layer to etch the second N-type material layer to obtain an N-type material block; wherein the width of the N-type material block is greater than the width of the bottom surface of the etched trench.

[0020] Optionally, forming the N-type material structure further includes: continuing to use the second mask layer to etch the isolation material layer to obtain a first N-type structure block; using a third mask layer to etch the first N-type material layer to form a second N-type structure block; wherein the second N-type structure block and the first N-type structure block are isolated by the second epitaxial layer and the first isolation material layer in the first N-type structure block.

[0021] Optionally, the materials of the first N-type material layer and / or the second N-type material layer are selected from: N-type polycrystalline silicon, N-type EPI, and N-type monocrystalline silicon.

[0022] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device, comprising: a semiconductor substrate; a first N-type material layer and at least two isolation material layers covering the semiconductor substrate; an etched trench located on the first N-type material layer and at least two isolation material layers, exposing an ion-implanted region on the surface of the semiconductor substrate, wherein the ion-implanted region is doped with N-type dopant ions; a first epitaxial layer located on the surface of the ion-implanted region; a second epitaxial layer located on the surface of the first epitaxial layer; and an N-type material structure covering the second epitaxial layer.

[0023] Optionally, the semiconductor device is an HBT device; wherein the ion implantation region is used to form the collector doped region of the HBT device; and the N-type material structure is used to form the emitter of the HBT device.

[0024] Optionally, the semiconductor device further includes a protective layer located on the sidewall surface of the etched trench.

[0025] Optionally, the material of the protective layer is selected from: a stack of silicon oxide and silicon nitride, silicon oxide, and silicon nitride.

[0026] Optionally, the N-type material structure includes an N-type material block; wherein the width of the N-type material block is greater than the width of the bottom surface of the etched trench.

[0027] Optionally, the N-type material structure further includes: a first N-type structural block, formed using the same mask layer as the N-type material block; and a second N-type structural block; wherein the second N-type structural block and the first N-type structural block are separated by the second epitaxial layer and the first isolation material layer in the first N-type structural block.

[0028] Optionally, one or more of the following conditions are met: the first epitaxial layer is selected from: an N-type epitaxial material layer; the second epitaxial layer is selected from: a P-type epitaxial material layer; the material of the first N-type material layer and / or the second N-type material layer is selected from: N-type polycrystalline silicon, N-type EPI, or N-type monocrystalline silicon.

[0029] Optionally, one or more of the following conditions must be met: the material of the N-type epitaxial material layer is selected from: N-type polycrystalline silicon, N-type EPI, and N-type monocrystalline silicon; the material of the P-type epitaxial material layer is selected from: P-type silicon germanide.

[0030] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0031] In this embodiment of the invention, by forming etching trenches, then forming ion implantation regions based on the etching trenches, and subsequently forming a first epitaxial layer and a second epitaxial layer based on the etching trenches, and forming an N-type material structure on the surface of the second epitaxial layer, a self-aligned structure is achieved between the ion implantation region, the first epitaxial layer, the second epitaxial layer, and the N-type material structure. Compared to the prior art which uses multiple mask layers and photolithography processes, resulting in alignment errors, the solution of this embodiment eliminates alignment errors based on the self-aligned structure, which is beneficial for meeting the size reduction requirements of semiconductor devices. Furthermore, using a first epitaxial layer and a second epitaxial layer located on the surface of the first epitaxial layer can increase the distance between the ion implantation region and the N-type material structure, effectively reducing the parasitic capacitance between the ion implantation region and the N-type material structure, which is beneficial for the high-frequency characteristics of semiconductor devices. Furthermore, in this embodiment, only a single mask layer and one photolithography process are used to form the etching trenches, and a self-aligned process is subsequently used to form the self-aligned structure. Compared to the prior art which requires multiple mask layers and photolithography processes, the above solution can effectively reduce production costs and improve production efficiency.

[0032] Furthermore, the semiconductor device is an HBT device. The ion-implanted region is used to form the collector-doped region of the HBT device, and the N-type material structure is used to form the emitter of the HBT device. This achieves self-alignment between the collector and emitter of the HBT device, eliminating alignment error issues and facilitating the miniaturization of the HBT device. Furthermore, by employing a first epitaxial layer and a second epitaxial layer located on the surface of the first epitaxial layer, the parasitic capacitance of the CB junction between the emitter and collector is effectively reduced, which is beneficial to the high-frequency characteristics of the HBT and promotes improvements in characteristic frequency fT, maximum characteristic frequency fmax, and maximum power gain cutoff frequency.

[0033] Furthermore, by forming a bottom etch stop layer, it can serve as a stop layer when forming etch trenches to control the etch depth, and it can also serve as a protective layer for the semiconductor substrate, allowing N-type doped ions to be implanted into the ion implantation region to effectively protect the surface of the semiconductor substrate.

[0034] Furthermore, based on the formation of the N-type ion implantation region, by forming an N-type epitaxial material layer as the first epitaxial layer, a P-type epitaxial material layer as the second epitaxial layer, and an N-type material structure, an NPN structure can be formed, further enhancing the performance of BJT devices, including HBT devices.

[0035] Furthermore, a first N-type structural block and a second N-type structural block are formed, wherein the second N-type structural block and the first N-type structural block are isolated by the second epitaxial layer and the first isolation material layer in the first N-type structural block. This can effectively isolate the first N-type structural block (e.g., the emitter in an HBT device) and the second N-type structural block (e.g., the base in an HBT device), effectively reducing the parasitic capacitance between the first N-type structural block and the second N-type structural block, which is beneficial to the high-frequency characteristics of the semiconductor device.

[0036] Furthermore, forming a protective layer on the sidewall surface of the etched trench can further effectively isolate the first N-type structural block (e.g., the emitter in an HBT device) and the second N-type structural block (e.g., the base in an HBT device), effectively reducing the parasitic capacitance between the first N-type structural block and the second N-type structural block, which is beneficial to further improve the high-frequency characteristics of the semiconductor device. Attached Figure Description

[0037] Figure 1 This is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention;

[0038] Figures 2 to 12 This is a schematic diagram of the cross-sectional structure of the device corresponding to each step in a method for forming a semiconductor device according to an embodiment of the present invention.

[0039] Figure label:

[0040] Semiconductor substrate 100; isolation structure 101; bottom etch stop layer 121; first N-type material layer 110; first isolation material layer 111; first isolation layer 1111; first etch stop layer 1112; second isolation material layer 112; second isolation layer 1121; second etch stop layer 1122; top dielectric layer 113; etch trench 141; ion implantation region 122; first epitaxial layer 131; second epitaxial layer 132; protective layer 133; second N-type material layer 151; second mask layer 161; N-type material block 152; first N-type structural block 153. Detailed Implementation

[0041] In the existing technology, taking HBT as an example, there is a problem of insufficient alignment accuracy in the process of forming the base (B), emitter (E) and collector (C). This can easily lead to incorrect proximity between the base, emitter and collector due to alignment differences. On the one hand, this limits the further reduction of the size of semiconductor devices, and on the other hand, it causes the capacitance of the EB junction between the emitter and collector to be too high, which limits the high frequency characteristics of HBT.

[0042] Specifically, in one prior art, a collector material layer, a base material layer, and an emitter material layer can be sequentially formed on a semiconductor substrate. Then, a patterned emitter mask layer is used to etch the emitter material layer to obtain the emitter, and a patterned base mask layer is used to etch the base material layer to obtain the base.

[0043] The inventors of this invention discovered through research that in the prior art, two mask layers and two photolithography processes are required to form the emitter and base, which can easily lead to alignment errors between the collector, base and emitter, making it difficult to achieve the size reduction requirements of semiconductor devices.

[0044] In this embodiment of the invention, by forming etching trenches, then forming ion implantation regions based on the etching trenches, and subsequently forming a first epitaxial layer and a second epitaxial layer based on the etching trenches, and forming an N-type material structure on the surface of the second epitaxial layer, a self-aligned structure is achieved between the ion implantation region, the first epitaxial layer, the second epitaxial layer, and the N-type material structure. Compared to the prior art which uses multiple mask layers and photolithography processes, resulting in alignment errors, the solution of this embodiment eliminates alignment errors based on the self-aligned structure, which is beneficial for meeting the size reduction requirements of semiconductor devices. Furthermore, using a first epitaxial layer and a second epitaxial layer located on the surface of the first epitaxial layer can increase the distance between the ion implantation region and the N-type material structure, effectively reducing the parasitic capacitance between the ion implantation region and the N-type material structure, which is beneficial for the high-frequency characteristics of semiconductor devices. Furthermore, in this embodiment, only a single mask layer and one photolithography process are used to form the etching trenches, and a self-aligned process is subsequently used to form the self-aligned structure. Compared to the prior art which requires multiple mask layers and photolithography processes, the above solution can effectively reduce production costs and improve production efficiency.

[0045] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0046] Reference Figure 1 , Figure 1 This is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention. The method for forming the semiconductor device may include steps S11 to S16:

[0047] Step S11: Provide a semiconductor substrate;

[0048] Step S12: Form a first N-type material layer and at least two isolation material layers covering the semiconductor substrate, etch the isolation material layer and the first N-type material layer to obtain an etch trench, and expose the ion implantation region on the surface of the semiconductor substrate;

[0049] Step S13: Implant N-type doped ions into the ion implantation region;

[0050] Step S14: Form a first epitaxial layer on the surface of the ion implantation region;

[0051] Step S15: Form a second epitaxial layer on the surface of the first epitaxial layer;

[0052] Step S16: Form an N-type material structure, wherein the N-type material structure covers the second epitaxial layer.

[0053] The following combination Figures 2 to 12 The method for forming the above-mentioned semiconductor device will be described.

[0054] Figures 2 to 12 This is a schematic diagram of the cross-sectional structure of the device corresponding to each step in a method for forming a semiconductor device according to an embodiment of the present invention.

[0055] Reference Figure 2 A semiconductor substrate 100 is provided, and an isolation structure 101 is formed in the semiconductor substrate 100, forming a first N-type material layer 110 and at least two isolation material layers covering the semiconductor substrate 100.

[0056] Furthermore, before forming the first N-type material layer 110, a bottom etching stop layer 121 can be formed on the surface of the semiconductor substrate 100.

[0057] Furthermore, after forming at least two layers of insulating material, a top dielectric layer 113 may be formed on the surface of the at least two layers of insulating material.

[0058] In specific implementations, the semiconductor substrate 100 may be a silicon substrate, or the material of the semiconductor substrate 100 may also be suitable materials such as germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium. The semiconductor substrate 100 may also be a silicon substrate on an insulator surface or a germanium substrate on an insulator surface, or a substrate with an epitaxy layer (Epilayer) grown on it.

[0059] Specifically, at least two layers of insulating material are used. Figure 2 The first isolation material layer 111 and the second isolation material layer 112 are used to represent this.

[0060] The first isolation material layer 111 may include a stack of the first isolation layer 1111 and the first etch stop layer 1112, and the second isolation material layer 112 may include a stack of the second isolation layer 1121 and the second etch stop layer 1122.

[0061] Furthermore, the materials of the first isolation layer 1111 and the second isolation layer 1121 can be selected from silicon nitride, such as Si3N4.

[0062] The materials of the first etch stop layer 1112 and the second etch stop layer 1122 can be selected from silicon oxide, such as SiO2.

[0063] Reference Figure 3 The isolation material layer (which may include, for example, a first isolation material layer 111 and a second isolation material layer 112) and the first N-type material layer 110 are etched to obtain an etched trench 141 and expose the ion implantation region on the surface of the semiconductor substrate 100.

[0064] Specifically, a patterned first mask layer (not shown) can be used to etch the isolation material layer and the first N-type material layer 110 to obtain the etched trench 141.

[0065] It should be noted that if a bottom etch stop layer 121 is formed in advance, the bottom etch stop layer 121 can be used as the etch stop layer.

[0066] The material of the bottom etch stop layer 121 can be selected from silicon oxide, such as SiO2.

[0067] The inventors of this invention discovered through research that in the prior art, using two mask layers and two photolithography processes to form the ion implantation region (corresponding to the collector of the HBT device) and the second epitaxial layer respectively can easily lead to alignment errors.

[0068] In this embodiment, only a single mask layer (i.e., the patterned first mask layer) and one photolithography process are used to form the etching trench 141. Subsequently, a self-aligned process is used to form a self-aligned structure. Compared with the prior art, which requires multiple mask layers and photolithography processes, the above solution can effectively reduce production costs and improve production efficiency.

[0069] Reference Figure 4 A sacrificial isolation layer (not shown) is formed, which covers the isolation material layer and the sidewall surface of the etch trench 141. The sacrificial isolation layer on the surface of the isolation material layer is removed, and then the bottom etch stop layer 121 on the surface of the ion implantation region is removed to expose the ion implantation region.

[0070] The material of the sacrificial isolation layer can be selected from silicon nitride, such as Si3N4.

[0071] Understandably, the remaining sacrificial isolation layer is located on the trench sidewall surface of the etched trench 141 to protect the trench sidewall of the etched trench 141.

[0072] In this embodiment of the invention, by forming a bottom etching stop layer 121, it can be used as a stop layer when forming etching trenches to control the etching depth, and the bottom etching stop layer 121 can also be used as a protective layer for the semiconductor substrate 100 to implant N-type doped ions into the ion implantation region 122 to effectively protect the surface of the semiconductor substrate 100.

[0073] Reference Figure 5 N-type doped ions are injected into the ion implantation region 122.

[0074] Specifically, the N-type can be, for example, P, As, or Sb.

[0075] In a non-limiting embodiment, the semiconductor device may be an HBT device. The step of implanting N-type doped ions into the ion implantation region 122 may include: implanting N-type doped ions into the ion implantation region 122 to form the collector doped region of the HBT device.

[0076] Reference Figure 6 A first epitaxial layer 131 is formed on the surface of the ion implantation region 122.

[0077] Furthermore, the step of forming a first epitaxial layer 131 on the surface of the ion implantation region 122 may include: forming an N-type epitaxial material layer on the surface of the ion implantation region using a first epitaxial layer forming process.

[0078] Furthermore, the material of the N-type epitaxial material layer can be selected from: N-type polycrystalline silicon, N-type EPI, and N-type monocrystalline silicon.

[0079] In this embodiment of the invention, N-type polysilicon can be used to form the first epitaxial layer 131 to obtain better electrical performance.

[0080] In a non-limiting embodiment, an epitaxial growth technique can be used in an N-type ion doping environment to form an N-type epitaxial material layer on the surface of the ion implantation region 122, thereby obtaining a first epitaxial layer 131.

[0081] Reference Figure 7 A second epitaxial layer 132 is formed on the surface of the first epitaxial layer 131.

[0082] It should be noted that, before forming the second epitaxial layer 132, a step of removing the sacrificial isolation layer from the sidewall surface of the doped trench 141 may also be included.

[0083] Furthermore, before forming the second epitaxial layer 132, the process may include removing at least one layer of insulating material to expose the surface of the insulating material layer adjacent to the first N-type material layer 110.

[0084] In practice, by setting multiple layers of isolation material and removing the isolation material layers sequentially after each etching or other material removal step, the flatness of the process surface can be maintained while protecting the semiconductor substrate and the completed device, thereby improving the consistency of the wafer process.

[0085] Furthermore, the step of forming a second epitaxial layer 132 on the surface of the first epitaxial layer 131 may include: forming a P-type epitaxial material layer on the surface of the first epitaxial layer 131 using a second epitaxial layer 132 forming process.

[0086] Furthermore, the material of the P-type epitaxial material layer can be selected from: P-type silicon germanide.

[0087] In one non-limiting embodiment, a silicon germanide (SiGe) material layer can be deposited in a P-type ion environment to form a P-type epitaxial material layer, thereby obtaining a second epitaxial layer 132.

[0088] Reference Figure 8 A protective layer 133 is formed, which covers the surface of the second epitaxial layer 132, the sidewall surface of the etched trench, and the surface of the isolation material layer (the first isolation material layer 111 in the figure) adjacent to the first N-type material layer. The protective layer 133 is etched with the second epitaxial layer 132 as the etching stop layer to retain the protective layer 133 on the sidewall surface of the etched trench and expose the isolation material adjacent to the first N-type material layer.

[0089] Furthermore, the material of the protective layer 133 can be selected from: a stack of silicon oxide and silicon nitride, silicon oxide, and silicon nitride.

[0090] In this embodiment of the invention, a protective layer 133 is formed on the sidewall surface of the etched trench, which can further effectively isolate the first N-type structural block (e.g., the emitter in an HBT device) and the second N-type structural block (e.g., the base in an HBT device), effectively reducing the parasitic capacitance between the first N-type structural block and the second N-type structural block, which is beneficial to further improve the high-frequency characteristics of the semiconductor device.

[0091] Reference Figure 9 A second N-type material layer 151 is formed, which covers the second epitaxial layer 132 to form a patterned second mask layer 161.

[0092] In this embodiment of the invention, based on the formation of the N-type ion implantation region 122, an NPN structure can be formed by forming an N-type epitaxial material layer as the first epitaxial layer 131, a P-type epitaxial material layer as the second epitaxial layer 132, and an N-type material structure, thereby further enhancing the performance of BJT devices, including HBT devices.

[0093] Reference Figure 10 The second N-type material layer 151 is etched using a patterned second mask layer 161 to obtain an N-type material block 152, wherein the width of the N-type material block 152 is greater than the width of the bottom surface of the etched trench.

[0094] The width can be in the direction parallel to the carrier movement within the semiconductor substrate.

[0095] Reference Figure 11The second mask layer 161 is then used to etch the isolation material layer (such as the first isolation material layer 111) to obtain the first N-type structure block 153.

[0096] As a non-limiting example, taking the semiconductor device as an HBT device, the first N-type structure block 153 is used to form the emitter.

[0097] In this embodiment of the invention, by forming an etching trench 141, then forming an ion implantation region 122 based on the etching trench, and further forming a first epitaxial layer 131 and a second epitaxial layer 132 based on the etching trench 141, and forming an N-type material structure on the surface of the second epitaxial layer 132, a self-aligned structure is achieved between the ion implantation region 122, the first epitaxial layer 131, the second epitaxial layer 132, and the N-type material structure. Compared with the prior art, which uses multiple mask layers and photolithography processes, resulting in alignment errors, the solution of this embodiment of the invention eliminates alignment errors based on the self-aligned structure, which is beneficial for meeting the size reduction requirements of semiconductor devices. Furthermore, by using the first epitaxial layer 131 and the second epitaxial layer 132 located on the surface of the first epitaxial layer 131, the distance between the ion implantation region 122 and the N-type material structure (such as the first N-type structure block 153) can be increased, effectively reducing the parasitic capacitance between the ion implantation region 122 and the N-type material structure (such as the first N-type structure block 153), which is beneficial for the high-frequency characteristics of the semiconductor device. Furthermore, in this embodiment, only a single mask layer (i.e., the patterned first mask layer) and one photolithography process are used to form the etching trench 141. Subsequently, a self-aligned process is used to form a self-aligned structure. Compared with the prior art, which requires multiple mask layers and photolithography processes, the above solution can effectively reduce production costs and improve production efficiency.

[0098] Reference Figure 12 A third mask layer is used to etch the first N-type material layer 110 to form a second N-type structure block, wherein the second N-type structure block and the first N-type structure block 153 are separated by the second epitaxial layer 132 and the first isolation material layer 111 in the first N-type structure block 153.

[0099] As a non-limiting example, taking an HBT device as an example of a semiconductor device, the second N-type structure block is used to form the base and can be located on both sides of the emitter as shown in the figure.

[0100] Furthermore, the materials of the first N-type material layer and / or the second N-type material layer can be selected from: N-type polycrystalline silicon, N-type EPI, and N-type monocrystalline silicon.

[0101] In this embodiment of the invention, a first N-type structural block 153 and a second N-type structural block are formed. The second N-type structural block and the first N-type structural block 153 are isolated by the second epitaxial layer 132 and the first isolation material layer 111 in the first N-type structural block 153. This can effectively isolate the first N-type structural block (e.g., the emitter in an HBT device) 153 and the second N-type structural block (e.g., the base in an HBT device), effectively reducing the parasitic capacitance between the first N-type structural block 153 and the second N-type structural block, which is beneficial to the high-frequency characteristics of the semiconductor device.

[0102] It should be noted that if the semiconductor device formation method is used to form an HBT device, a buried layer can be formed in the semiconductor substrate 100, and the doping ion type of the buried layer is consistent with the doping type of the ion implantation region 122, thereby realizing a collector containing multiple electrical connection regions.

[0103] In this embodiment of the invention, when the semiconductor device is an HBT device, the ion implantation region 122 can be used to form the collector-doped region of the HBT device, and the N-type material structure is used to form the emitter of the HBT device, thereby achieving self-alignment between the collector and emitter of the HBT device. There is no alignment error problem between the collector and emitter, which is beneficial for meeting the size reduction requirements of the HBT device. Furthermore, by employing a first epitaxial layer 131 and a second epitaxial layer 132 located on the surface of the first epitaxial layer 131, the parasitic capacitance of the CB junction between the emitter and collector can be effectively reduced, which is beneficial for the high-frequency characteristics of the HBT and promotes improvements in characteristic frequency fT, maximum characteristic frequency fmax, and maximum power gain cutoff frequency.

[0104] It should be noted that, in the embodiments of the present invention, in addition to HBT devices, it can also be used for RF-CMOS devices, BJT devices other than HBT, and other suitable RF devices other than BJT.

[0105] In this embodiment of the invention, a semiconductor device is also disclosed, with reference to... Figure 12 It may include: a semiconductor substrate 100; a first N-type material layer 110 and at least two insulating material layers covering the semiconductor substrate 100; and etched trenches 141 (see reference). Figure 4 An ion implantation region 122 is located on the first N-type material layer 110 and at least two isolation material layers, and exposes the surface of the semiconductor substrate 100, wherein the ion implantation region 122 is doped with N-type doped ions; a first epitaxial layer 131 is located on the surface of the ion implantation region 122; a second epitaxial layer 132 is located on the surface of the first epitaxial layer 131; and an N-type material structure covers the second epitaxial layer 132.

[0106] Furthermore, the semiconductor device is an HBT device; wherein, the ion implantation region 122 is used to form the collector doped region of the HBT device; and the N-type material structure is used to form the emitter of the HBT device.

[0107] Furthermore, the semiconductor device also includes a protective layer 133 located on the sidewall surface of the etched trench 141.

[0108] Furthermore, the material of the protective layer 133 can be selected from: a stack of silicon oxide and silicon nitride, silicon oxide, and silicon nitride.

[0109] As a non-restrictive example, Figure 12 The protective layer 133 shown is a stack of silicon oxide and silicon nitride, which can provide more comprehensive protection and reduce stress.

[0110] Furthermore, the N-type material structure includes an N-type material block 152; wherein the width of the N-type material block 152 is greater than the width of the bottom surface of the etched trench 141.

[0111] Furthermore, the N-type material structure further includes: a first N-type structural block 153, which is formed using the same mask layer as the N-type material block; and a second N-type structural block; wherein the second N-type structural block and the first N-type structural block 153 are separated by the second epitaxial layer 132 and the first isolation material layer 111 in the first N-type structural block 153.

[0112] The N-type material structure may include, for example, a first N-type structural block 153 and a second N-type structural block. Taking an HBT device as an example, the first N-type structural block 153 can be the emitter, and the second N-type structural block can be the base.

[0113] Further, one or more of the following conditions are met: the first epitaxial layer 131 is selected from: an N-type epitaxial material layer; the second epitaxial layer 132 is selected from: a P-type epitaxial material layer; the materials of the first N-type material layer and / or the second N-type material layer are selected from: N-type polycrystalline silicon, N-type EPI, and N-type monocrystalline silicon.

[0114] Furthermore, one or more of the following conditions must be met: the material of the N-type epitaxial material layer is selected from: N-type polycrystalline silicon, N-type EPI, and N-type monocrystalline silicon; the material of the P-type epitaxial material layer is selected from: P-type silicon germanide.

[0115] For the principles, specific implementation, and beneficial effects of this semiconductor device, please refer to the previous description of the semiconductor device formation method; it will not be repeated here.

[0116] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0117] In the embodiments of this application, "multiple" refers to two or more.

[0118] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0119] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, include: Provide semiconductor substrates; A first N-type material layer and at least two isolation material layers are formed covering the semiconductor substrate. The isolation material layer and the first N-type material layer are etched to obtain an etch trench and expose the ion implantation region on the surface of the semiconductor substrate. N-type doped ions are implanted into the ion implantation region; A first epitaxial layer is formed on the surface of the ion implantation region; A second epitaxial layer is formed on the surface of the first epitaxial layer; Forming an N-type material structure, wherein the N-type material structure covers the second epitaxial layer, the formation of the N-type material structure includes: A second N-type material layer is formed, and the second N-type material layer covers the second epitaxial layer; A patterned second mask layer is used to etch the second N-type material layer to obtain an N-type material block; wherein the width of the N-type material block is greater than the width of the bottom surface of the etched trench; The second mask layer is then used to etch the isolation material layer to obtain the first N-type structure block; A third mask layer is used to etch the first N-type material layer to form a second N-type structure block; wherein the second N-type structure block and the first N-type structure block are separated by the second epitaxial layer and the isolation material layer in the first N-type structure block.

2. The method for forming a semiconductor device according to claim 1, characterized in that, The semiconductor device is an HBT device; Implanting N-type doped ions into the ion implantation region includes: N-type doped ions are implanted into the ion implantation region to form the collector doped region of the HBT device; The N-type material structure is used to form the emitter of the HBT device.

3. The method for forming a semiconductor device according to claim 1, characterized in that, Each layer of isolation material comprises a stack of isolation layers and etch stop layers; Forming a first N-type material layer and at least two isolation material layers covering the semiconductor substrate, etching the isolation material layers and the first N-type material layer to obtain etching trenches, and exposing the ion implantation region on the surface of the semiconductor substrate, including: The first patterned mask layer is used to etch the isolation material layer and the first N-type material layer to obtain the etched trench; A sacrificial isolation layer is formed, which covers the isolation material layer and the sidewall surface of the etched trench; Remove the sacrificial isolation layer from the surface of the isolation material layer.

4. The method for forming a semiconductor device according to claim 3, characterized in that, Before etching the isolation material layer and the first N-type material layer using a patterned first mask layer, the method further includes: An etch stop layer, a first N-type material layer, and at least two isolation material layers are sequentially formed on the surface of the semiconductor substrate.

5. The method for forming a semiconductor device according to claim 4, characterized in that, The method further includes: Remove the bottom etch stop layer on the surface of the ion implantation region to expose the ion implantation region.

6. The method for forming a semiconductor device according to any one of claims 3 to 5, characterized in that, Meet one or more of the following: The material of the isolation layer and / or the sacrificial isolation layer is selected from: silicon nitride; The material of the etching stop layer and / or the bottom etching stop layer is selected from silicon oxide.

7. The method for forming a semiconductor device according to claim 1, characterized in that, A first epitaxial layer is formed on the surface of the ion implantation region, comprising: An N-type epitaxial material layer is formed on the surface of the ion implantation region using a first epitaxial layer formation process.

8. The method for forming a semiconductor device according to claim 7, characterized in that, The material of the N-type epitaxial layer is selected from: N-type polycrystalline silicon and N-type monocrystalline silicon.

9. The method for forming a semiconductor device according to claim 1, characterized in that, A second epitaxial layer is formed on the surface of the first epitaxial layer, including: A second epitaxial layer formation process is used to form a P-type epitaxial material layer on the surface of the first epitaxial layer.

10. The method for forming a semiconductor device according to claim 9, characterized in that, The material of the P-type epitaxial layer is selected from: P-type silicon germanide.

11. The method for forming a semiconductor device according to claim 1, characterized in that, Before forming a second epitaxial layer on the surface of the first epitaxial layer, the method further includes: At least one layer of insulating material is removed to expose the surface of the insulating material layer adjacent to the first N-type material layer.

12. The method for forming a semiconductor device according to claim 11, characterized in that, After forming a second epitaxial layer on the surface of the first epitaxial layer, and before forming an N-type material structure, the method further includes: A protective layer is formed, which covers the surface of the second epitaxial layer, the sidewall surface of the etched trench, and the surface of the isolation material layer adjacent to the first N-type material layer; Using the second epitaxial layer as the etching stop layer, the protective layer is etched to retain the protective layer on the sidewall surface of the etched trench and expose the isolation material layer adjacent to the first N-type material layer.

13. The method for forming a semiconductor device according to claim 12, characterized in that, The material of the protective layer is selected from: a stack of silicon oxide and silicon nitride, silicon oxide, and silicon nitride.

14. The method for forming a semiconductor device according to claim 1, characterized in that, The materials of the first N-type material layer and / or the second N-type material layer are selected from: N-type polycrystalline silicon and N-type monocrystalline silicon.

15. A semiconductor device, characterized in that, include: Semiconductor substrate; A first N-type material layer and at least two isolation material layers cover the semiconductor substrate; An etched trench is located between the first N-type material layer and at least two isolation material layers, and exposes an ion implantation region on the surface of the semiconductor substrate, wherein the ion implantation region is doped with N-type dopant ions; The first epitaxial layer is located on the surface of the ion implantation region; The second epitaxial layer is located on the surface of the first epitaxial layer; An N-type material structure covering the second epitaxial layer, the N-type material structure comprising: N-type material block; wherein the width of the N-type material block is greater than the width of the bottom surface of the etched trench; The N-type material structure also includes: The first N-type structural block is formed using the same mask layer as the N-type material block; The second N-type structural block; wherein the second N-type structural block and the first N-type structural block are separated by the second epitaxial layer and the first isolation material layer in the first N-type structural block.

16. The semiconductor device according to claim 15, characterized in that, The semiconductor device is an HBT device; The ion implantation region is used to form the collector doped region of the HBT device; The N-type material structure is used to form the emitter of the HBT device.

17. The semiconductor device according to claim 15, characterized in that, Also includes: A protective layer is located on the sidewall surface of the etched trench.

18. The semiconductor device according to claim 17, characterized in that, The material of the protective layer is selected from: a stack of silicon oxide and silicon nitride, silicon oxide, and silicon nitride.

19. The semiconductor device according to claim 15, characterized in that, Meet one or more of the following: The first epitaxial layer is selected from: an N-type epitaxial material layer; The second epitaxial layer is selected from: a P-type epitaxial material layer; The material of the first N-type material layer is selected from: N-type polycrystalline silicon and N-type monocrystalline silicon.

20. The semiconductor device according to claim 19, characterized in that, Meet one or more of the following: The material of the N-type epitaxial material layer is selected from: N-type polycrystalline silicon and N-type monocrystalline silicon; The material of the P-type epitaxial layer is selected from: P-type silicon germanide.

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