Method for forming sj-igbt structure, sj-igbt structure

Abstract

An SJ-IGBT structure and a forming method thereof, the method comprising: providing a semiconductor substrate; forming P-type pillars in the semiconductor substrate; etching the semiconductor substrate and the P-type pillars to form gate trenches, the gate trenches comprising isolation gate trenches, a bottom surface of each isolation gate trench exposing an etched entire top surface of one or more P-type pillars; forming gate structures in the gate trenches; wherein the semiconductor substrate has a P-type body doped region, a first distance between a bottom surface of the isolation gate trenches and a surface of the semiconductor substrate is greater than a second distance between a bottom surface of the P-type body doped region and the surface of the semiconductor substrate, and less than a third distance between a bottom surface of the P-type pillars and the surface of the semiconductor substrate. The application can reduce production cost, improve production efficiency, and reduce process limitations.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming an SJ-IGBT structure and the SJ-IGBT structure. Background Technology

[0002] In the existing technology, the Insulated Gate Bipolar Transistor (IGBT) is a composite fully controllable voltage-driven power semiconductor device that can include both a Bipolar Junction Transistor (BJT) and an Insulated Gate Semiconductor Field-Effect Transistor (MOSFET). It combines the advantages of MOSFETs, such as high input impedance, simple driving, and high switching speed, with the advantages of BJTs, such as high current density, low saturation voltage drop, and strong current handling capability.

[0003] Superjunctions (SJs) can be located within the drift region of IGBTs and include alternating N-type and P-type pillars. They can reduce forward conduction power consumption, improve forward conduction performance, and increase power density.

[0004] In one existing SJ-IGBT structure, there may be a P-type doped region above the drift region, and the P-type doped region and the P-type pillar may have contact areas or even overlap areas, which can cause carriers (such as holes) to be extracted when the device is forward-biased, affecting the device performance.

[0005] However, existing methods for improving the SJ-IGBT structure are complex, resulting in high production costs, and impose significant limitations on the formation sequence of the SJ-IGBT structure. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a method for forming an SJ-IGBT structure and an SJ-IGBT structure that can reduce production costs, improve production efficiency, and reduce process limitations.

[0007] To address the aforementioned technical problems, this invention provides a method for forming an SJ-IGBT structure, comprising: providing a semiconductor substrate; forming P-type pillars within the semiconductor substrate; etching the semiconductor substrate and the P-type pillars to form a gate trench, the gate trench including an isolation gate trench, the bottom surface of each isolation gate trench exposing the entire etched top surface of one or more P-type pillars; forming a gate structure within the gate trench; wherein the semiconductor substrate has a P-type body doped region, a first distance between the bottom surface of the isolation gate trench and the surface of the semiconductor substrate is greater than a second distance between the bottom surface of the P-type body doped region and the surface of the semiconductor substrate, and less than a third distance between the bottom surface of the P-type pillar and the surface of the semiconductor substrate.

[0008] Optionally, the isolation fence trench corresponds one-to-one with the P-shaped pillar; wherein the bottom surface of each isolation fence trench exposes the entire etched top surface of the corresponding P-shaped pillar, and the bottom surface contour of the isolation fence trench is larger than the top surface contour of the P-shaped pillar.

[0009] Optionally, etching the semiconductor substrate and the P-type pillar to form a gate trench includes: forming a patterned mask layer on the surface of the semiconductor substrate, wherein the etchable contour of the patterned mask layer on the top surface of the P-type pillar covers the top surface of the P-type pillar, and the etchable contour of the patterned mask layer on the top surface of the P-type pillar is larger than the top surface contour of the P-type pillar; and using the patterned mask layer to etch the semiconductor substrate and the P-type pillar.

[0010] Optionally, forming a gate structure within the gate trench includes: forming a gate oxide layer on the bottom surface and sidewall surface within the isolation gate trench; forming a gate conductive layer on the surface of the gate oxide layer, wherein the gate conductive layer fills the isolation gate trench, or the gate conductive layer covers the bottom surface and sidewall surface of the isolation gate trench but does not fill the isolation gate trench; and performing back etching on the gate conductive layer to obtain an isolation gate structure located within the isolation gate trench.

[0011] Optionally, if the gate conductive layer fills the isolation gate trench, the top surface of the etched-back gate conductive layer is flush with the surface of the semiconductor substrate; if the gate conductive layer covers the bottom surface and sidewall surface of the isolation gate trench but does not fill the isolation gate trench, all or part of the etched-back gate conductive layer is located on the sidewall surface of the isolation gate trench and the thickness of the etched-back gate conductive layer is less than the thickness of the isolation gate trench.

[0012] Optionally, the method further includes: after forming a gate structure in the gate trench, forming a dielectric layer, the dielectric layer covering the P-type body doped region, the gate structure, and the P-type pillar; wherein, if the gate conductive layer covers the bottom surface and sidewall surface of the isolation gate trench but does not fill the isolation gate trench, the dielectric layer fills the remaining space in the isolation gate trench.

[0013] Optionally, the method for forming the SJ-IGBT structure further includes: before forming a P-type pillar in the semiconductor substrate, performing P-type body region ion implantation in the semiconductor substrate to form a P-type body doped region.

[0014] Optionally, the method for forming the SJ-IGBT structure further includes: after forming a P-type pillar in the semiconductor substrate, and before etching the semiconductor substrate and the P-type pillar to form a gate trench, performing P-type body ion implantation in the semiconductor substrate to form a P-type body doped region.

[0015] Optionally, the method for forming the SJ-IGBT structure further includes: after forming the gate structure in the gate trench and before forming the dielectric layer, performing P-type body ion implantation into the semiconductor substrate to form a P-type body doped region.

[0016] To address the aforementioned technical problems, this invention provides an SJ-IGBT structure, comprising: a semiconductor substrate; P-type pillars located within the semiconductor substrate; a gate trench located within the semiconductor substrate, the gate trench including an isolation gate trench, the bottom surface of each isolation gate trench exposing the entire etched top surface of one or more P-type pillars; and a gate structure formed within the gate trench; wherein the semiconductor substrate has a P-type body doped region, a first distance between the bottom surface of the isolation gate trench and the surface of the semiconductor substrate is greater than a second distance between the bottom surface of the P-type body doped region and the surface of the semiconductor substrate, and less than a third distance between the bottom surface of the P-type pillars and the surface of the semiconductor substrate.

[0017] Optionally, the isolation fence trench corresponds one-to-one with the P-shaped pillar; wherein the bottom surface of each isolation fence trench exposes the entire etched top surface of the corresponding P-shaped pillar, and the bottom surface contour of the isolation fence trench is larger than the top surface contour of the P-shaped pillar.

[0018] Optionally, the gate structure includes: a gate oxide layer located on the bottom surface and sidewall surface within the isolation gate trench; a gate conductive layer located on the surface of the gate oxide layer, wherein the top surface of the gate conductive layer is flush with the surface of the semiconductor substrate; or, all or part of the gate conductive layer is located on the sidewall surface of the isolation gate trench and the thickness of the gate conductive layer is less than the thickness of the isolation gate trench.

[0019] Optionally, the SJ-IGBT structure further includes a P-type body doped region located within the semiconductor substrate; wherein the P-type body doped region is formed before the formation of P-type pillars within the semiconductor substrate.

[0020] Optionally, the SJ-IGBT structure further includes a P-type body doped region located within the semiconductor substrate; wherein the P-type body doped region is formed after a P-type pillar is formed within the semiconductor substrate and before the semiconductor substrate and the P-type pillar are etched to form a gate trench.

[0021] Optionally, the SJ-IGBT structure further includes a P-type body doped region located within the semiconductor substrate; wherein the P-type body doped region is formed after the gate structure is formed in the gate trench and before the dielectric layer is formed.

[0022] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0023] In this embodiment of the invention, by forming gate trenches, including isolation gate trenches, the bottom surface of each isolation gate trench exposes the entire etched top surface of one or more P-type pillars. This allows the bottom surface of the isolation gate structure formed within the isolation gate trench to be lower than the P-type body doped region and higher than the P-type pillars, effectively isolating the P-type body doped region and the P-type pillars, thus disconnecting the electrical connection between them. This effectively mitigates the problem of carrier (such as holes) extraction during device forward conduction, enhancing device performance. Furthermore, the isolation gate structure can be formed based on conventional control gate structure masks and their manufacturing processes, eliminating the need for additional masks. Compared to existing technologies that require an additional isolation material layer, leading to increased production costs, the technical solution of this embodiment reduces production costs and improves production efficiency. Moreover, since both the P-type body doped region and the gate structure are located within the semiconductor substrate, the formation order of the P-type body doped region is not restricted, thus not limiting process improvements and parameter adjustments, which is beneficial for device performance optimization.

[0024] Furthermore, the isolation gate trench corresponds one-to-one with the P-type pillar; the bottom surface of each isolation gate trench exposes the entire etched top surface of the corresponding P-type pillar, and the bottom surface contour of the isolation gate trench is larger than the top surface contour of the P-type pillar. This can be considered as the projection of the bottom contour of the isolation gate trench onto the semiconductor substrate surface surrounding the projection of the cross-sectional contour of the P-type pillar onto the semiconductor substrate surface. The length and width of the bottom contour of the isolation gate trench are greater than the length and width of the cross-sectional contour of the P-type pillar, thereby achieving complete isolation of each isolation gate structure from the corresponding P-type pillar.

[0025] Furthermore, by having the patterned mask layer cover the top surface of the P-shaped column with the etchable outline, and the etchable outline of the patterned mask layer on the top surface of the P-shaped column is larger than the top surface outline of the P-shaped column, the technical solution of this embodiment can be achieved simply by adjusting the existing mask, effectively controlling the improvement cost.

[0026] Furthermore, a gate conductive layer is formed on the surface of the gate oxide layer, wherein the gate conductive layer fills the isolation gate trench, or the gate conductive layer covers the bottom surface and sidewall surface of the isolation gate trench without filling the isolation gate trench. The gate conductive layer or the dielectric layer formed in the subsequent process can be used to isolate the P-type body doped region and the P-type pillar. Since the steps of forming the gate conductive layer and forming the dielectric layer are both improvements based on the existing SJ-IGBT structure formation process, the improvement cost can be further effectively controlled.

[0027] Furthermore, the P-type body doped region, P-type pillar, and gate structure in the SJ-IGBT structure can be formed using various process sequences. The formation sequence of the P-type body doped region is not strictly limited, which effectively improves process flexibility, facilitates process improvement and process parameter adjustment, and helps to optimize device performance. Attached Figure Description

[0028] Figures 1 to 5 This is a schematic diagram of the device cross-sectional structure corresponding to some steps in a method for forming an SJ-IGBT structure in the prior art;

[0029] Figure 6 This is a flowchart of a method for forming an SJ-IGBT structure according to an embodiment of the present invention;

[0030] Figures 7 to 11 This is a schematic diagram of the device cross-sectional structure corresponding to each step in the method for forming an SJ-IGBT structure in an embodiment of the present invention;

[0031] Figure 12 This is a cross-sectional structural diagram of another SJ-IGBT structure in an embodiment of the present invention;

[0032] Figure 13 This is a cross-sectional structural diagram of another SJ-IGBT structure in an embodiment of the present invention.

[0033] Figure label:

[0034] Semiconductor substrate 100; protective layer 101; P-type pillar trench 111; P-type pillar 110; N-type epitaxial isolation layer 120; P-type body doped region 130; gate structure 140; semiconductor substrate 200; P-type pillar 210; gate trench 220; isolation gate trench 221; control gate trench 222; gate structure 230; isolation gate structure 231; control gate structure 232; P-type body doped region 240; dielectric layer 250; plug structure 260; metal layer 270; capping layer 271; plug structure 360. Detailed Implementation

[0035] In existing SJ-IGBT structures, a P-type doped region may exist above the drift region, and this P-type doped region and the P-type pillar may have contact areas or even overlap. This can lead to the extraction of charge carriers (such as holes) during forward conduction, affecting device performance. However, existing methods for improving the SJ-IGBT structure are complex, resulting in high production costs, and impose significant limitations on the formation sequence of the SJ-IGBT structure.

[0036] Figures 1 to 5 This is a schematic diagram of the device cross-sectional structure corresponding to some steps in a method for forming an SJ-IGBT structure in the prior art.

[0037] Reference Figure 1 A semiconductor substrate 100 is provided, and a patterned protective layer 101 is formed on the surface of the semiconductor substrate 100. The semiconductor substrate 100 is etched using the patterned protective layer 101 as a mask to obtain a P-type pillar trench 111.

[0038] Reference Figure 2 A P-shaped column 110 is formed within the P-shaped column groove 111.

[0039] It is understandable that in order to form an alternating arrangement of N-type pillars and P-type pillars SJ, an N-type doped region can be pre-formed in the semiconductor substrate 100, and a P-type pillar 110 can be formed within the N-type doped region.

[0040] Reference Figure 3 An N-type epitaxial isolation layer 120 is formed on the surface of a semiconductor substrate.

[0041] The inventors of this invention discovered through research that, in existing methods for improving the SJ-IGBT structure, adding an additional insulating material layer (i.e. Figure 3 The technical solution shown (N-type epitaxial isolation layer 120) leads to increased production costs and affects production efficiency.

[0042] Reference Figure 4 P-type body ion implantation is performed into the N-type epitaxial isolation layer 120 to form a P-type body doped region 130.

[0043] Reference Figure 5 A gate structure 140 is formed, and the gate structure 140 penetrates the N-type epitaxial isolation layer 120.

[0044] Understandably, in subsequent processes, dielectric layers, plug structures, metal layers, passivation layers, etc., can be formed to complete the entire SJ-IGBT structure. The subsequent operations in the existing technology will not be elaborated here.

[0045] The inventors of this invention further discovered through research that in existing methods for improving the SJ-IGBT structure, the technical solution of adding an additional N-type epitaxial isolation layer 120 imposes restrictions on the formation sequence of the P-type body doped region 130 and the gate structure 140, since the P-type body doped region 130 is located within the N-type epitaxial isolation layer 120 and the gate structure 140 penetrates through the N-type epitaxial isolation layer 120. It requires strict adherence to the process sequence of "first forming the N-type epitaxial isolation layer 120, then forming the P-type body doped region 130, and finally forming the gate structure 140." The gate structure 140, which is of higher importance, must be formed in the last step. This significantly limits process improvement and process parameter adjustment, hindering device performance optimization.

[0046] In this embodiment of the invention, by forming gate trenches, including isolation gate trenches, the bottom surface of each isolation gate trench exposes the entire etched top surface of one or more P-type pillars. This allows the bottom surface of the isolation gate structure formed within the isolation gate trench to be lower than the P-type body doped region and higher than the P-type pillars, effectively isolating the P-type body doped region and the P-type pillars, thus disconnecting the electrical connection between them. This effectively mitigates the problem of carrier (such as holes) extraction during device forward conduction, enhancing device performance. Furthermore, the isolation gate structure can be formed based on conventional control gate structure masks and their manufacturing processes, eliminating the need for additional masks. Compared to existing technologies that require an additional isolation material layer, leading to increased production costs, the technical solution of this embodiment reduces production costs and improves production efficiency. Moreover, since both the P-type body doped region and the gate structure are located within the semiconductor substrate, the formation order of the P-type body doped region is not restricted, thus not limiting process improvements and parameter adjustments, which is beneficial for device performance optimization.

[0047] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0048] Reference Figure 6 , Figure 6 This is a flowchart illustrating a method for forming an SJ-IGBT structure according to an embodiment of the present invention. The method for forming the SJ-IGBT structure may include steps S61 to S64:

[0049] Step S61: Provide a semiconductor substrate;

[0050] Step S62: Form a P-type pillar within the semiconductor substrate;

[0051] Step S63: Etch the semiconductor substrate and the P-type pillars to form a gate trench, the gate trench including an isolation gate trench, the bottom surface of each isolation gate trench exposing the entire etched top surface of one or more P-type pillars;

[0052] Step S64: Form a gate structure within the gate trench.

[0053] The semiconductor substrate has a P-type body doped region. The first distance between the bottom surface of the isolation gate trench and the surface of the semiconductor substrate is greater than the second distance between the bottom surface of the P-type body doped region and the surface of the semiconductor substrate, and less than the third distance between the bottom surface of the P-type pillar and the surface of the semiconductor substrate.

[0054] The following is combined Figures 7 to 11The steps described above will be explained.

[0055] Figures 7 to 11 This is a schematic diagram of the device cross-sectional structure corresponding to each step in the method for forming an SJ-IGBT structure in an embodiment of the present invention.

[0056] Reference Figure 7 A semiconductor substrate 200 is provided, in which P-type pillars 210 are formed.

[0057] The semiconductor substrate 200 may be a silicon substrate, or the material of the semiconductor substrate 200 may include germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium. The semiconductor substrate 200 may also be a silicon substrate on an insulator or a germanium substrate on an insulator, or a substrate with an epitaxy layer (Epi layer) grown on it.

[0058] In this embodiment of the invention, the semiconductor substrate 200 is used to form an SJ-IGBT structure, and therefore various suitable substrate doping methods that can be used to form an SJ-IGBT structure can be adopted.

[0059] As a non-limiting example, a buffer zone and a drift region located above the buffer zone can be formed in the semiconductor substrate 200. The buffer zone can be, for example, heavily N-type doped, and the drift region can be, for example, lightly N-type doped, formed, for example, by epitaxial growth or by doping. It should be noted that the SJ with alternating N-type and P-type pillars can be obtained by forming P-type pillars within the drift region in a subsequent process.

[0060] Specifically, a patterned protective layer (not shown) can be formed on the surface of the semiconductor substrate 200. Using the patterned protective layer as a mask, the semiconductor substrate 200 is etched to obtain a P-type pillar trench (not shown), and a P-type pillar 210 is formed in the P-type pillar trench.

[0061] Non-limiting, an epitaxial filling process can be used, and P-type doping can be performed during the formation process to form P-type pillar material in the P-type pillar trench, and then a planarization (Chemical Mechanical Polishing, CMP) process can be used to form P-type pillar 210.

[0062] Reference Figure 8 The semiconductor substrate 200 and the P-type pillar 210 are etched to form the gate trench 220.

[0063] The gate trench 220 may include an isolation gate trench 221, the bottom surface of each isolation gate trench 221 exposing the entire top surface of one or more P-shaped pillars 210 after etching.

[0064] It should be noted that the bottom surface of each isolation gate trench 221 exposes the entire etched top surface of one or more P-type pillars 210. This means that the bottom surface profile of each isolation gate trench 221 is larger than the top surface profile of one or more P-type pillars 210. This can be considered as the projection of the bottom profile of each isolation gate trench 221 onto the surface of the semiconductor substrate 200 surrounding the projection of the cross-sectional profile of one or more P-type pillars 210 onto the surface of the semiconductor substrate 200. Furthermore, it can be considered as the length and width of the bottom profile of each isolation gate trench 221 being greater than the length and width of the cross-sectional profile of one or more P-type pillars 210. In this case, after the isolation gate structure is formed within each isolation gate trench 221, one or more P-type pillars 210 can be effectively isolated from structures located above the P-type pillars 210 (such as P-type body doped regions).

[0065] It should be noted that the gate trench 220 may also include a control gate trench 222 for forming the control gate structure conventionally present in SJ-IGBT structures.

[0066] Wherein, the first distance D1 between the bottom surface of the isolation gate trench 221 and the surface of the semiconductor substrate 200 is smaller than the third distance D3 between the bottom surface of the P-type pillar 210 and the surface of the semiconductor substrate 200, so that after the isolation gate trench 221 is formed, a portion of the P-type pillar 210 can still be retained.

[0067] Further, the step of etching the semiconductor substrate 200 and the P-type pillar 210 to form the gate trench 220 may include: forming a patterned mask layer (not shown) on the surface of the semiconductor substrate 200, wherein the patterned mask layer covers the top surface of the P-type pillar 210 with an etchable contour, and the etchable contour of the patterned mask layer on the top surface of the P-type pillar 210 is larger than the top surface contour of the P-type pillar 210; and using the patterned mask layer to etch the semiconductor substrate 200 and the P-type pillar 210.

[0068] In this embodiment of the invention, the patterned mask layer covers the top surface of the P-shaped pillar 210 with the etchable outline on the top surface of the P-shaped pillar 210, and the etchable outline of the patterned mask layer on the top surface of the P-shaped pillar 210 is larger than the top surface outline of the P-shaped pillar 210. The technical solution of this embodiment of the invention can be achieved by simply adjusting the existing mask, effectively controlling the improvement cost.

[0069] Furthermore, the isolation trench 221 can correspond one-to-one with the P-shaped pillar 210; wherein, the bottom surface of each isolation trench 221 exposes the entire etched top surface of the corresponding P-shaped pillar 210, and the bottom surface contour of the isolation trench 221 is larger than the top surface contour of the P-shaped pillar 210.

[0070] Specifically, the bottom surface of each isolation gate trench 221 exposes the entire etched top surface of the corresponding P-type pillar 210, and the bottom surface contour of the isolation gate trench 221 is larger than the top surface contour of the P-type pillar 210. This can be considered as the projection of the bottom contour of the isolation gate trench 221 onto the surface of the semiconductor substrate 200 surrounding the projection of the cross-sectional contour of the corresponding P-type pillar 210 onto the surface of the semiconductor substrate 200. The length and width of the bottom contour of the isolation gate trench 221 are greater than the length and width of the cross-sectional contour of the corresponding P-type pillar 210, thereby achieving complete isolation of each isolation gate structure for the corresponding P-type pillar. For example, it can effectively isolate the P-type pillar 210 from the structure located above the P-type pillar 210 (such as the P-type body doped region).

[0071] Reference Figure 9 A gate structure 230 is formed within the gate trench 220.

[0072] The gate structure 230 may include an isolation gate structure 231 formed within the isolation gate trench 221.

[0073] It should be noted that the gate structure 230 may also include a control gate structure 232 formed within the control gate trench 222.

[0074] In this embodiment of the invention, the isolation gate structure 231 can be formed using the same process while forming the control gate structure 232 that is conventionally present in the SJ-IGBT structure, without the need to add an additional mask and its photolithography process, thus effectively controlling the improvement cost.

[0075] Further, the step of forming the gate structure 230 within the gate trench 220 may include: forming a gate oxide layer (not shown) on the bottom surface and sidewall surface within the isolation gate trench 221; forming a gate conductive layer (not shown) on the surface of the gate oxide layer, wherein the gate conductive layer fills the isolation gate trench 221, or the gate conductive layer covers the bottom surface and sidewall surface of the isolation gate trench 221 but does not fill the isolation gate trench 221; and performing back etching on the gate conductive layer to obtain the isolation gate structure 231 located within the isolation gate trench 221.

[0076] Specifically, the gate conductive layer can fill the isolation gate trench 221, or it can be located on the side wall surface and bottom surface of the isolation gate trench 221, but not fill the isolation gate trench 221.

[0077] Furthermore, if the gate conductive layer fills the isolation gate trench 221, the top surface of the etched-back gate conductive layer is flush with the surface of the semiconductor substrate 200; if the gate conductive layer covers the bottom surface and sidewall surface of the isolation gate trench 221, but does not fill the isolation gate trench 221, then all or part of the etched-back gate conductive layer is located on the sidewall surface of the isolation gate trench 221, and the thickness of the etched-back gate conductive layer is less than the thickness of the isolation gate trench 221.

[0078] Specifically, the gate conductive layer in the etched isolation gate structure 231 can fill the isolation gate trench 221, or it can be located on the side wall surface of the isolation gate trench 221, or it can be located on the side wall surface and bottom surface of the isolation gate trench 221, but it does not fill the isolation gate trench 221.

[0079] In this embodiment of the invention, a gate conductive layer is formed on the surface of the gate oxide layer. The gate conductive layer fills the isolation gate trench 231, or the gate conductive layer covers the bottom surface and sidewall surface of the isolation gate trench 231, but does not fill the isolation gate trench 231. The gate conductive layer or the dielectric layer formed in the subsequent process can be used to isolate the P-type body doped region and the P-type pillar. Since the steps of forming the gate conductive layer and forming the dielectric layer are both improvements based on the existing SJ-IGBT structure formation process, the improvement cost can be further effectively controlled.

[0080] In specific implementations, depending on the formation process of the SJ-IGBT device, after forming the gate structure 240, a source doped region can be formed in the semiconductor substrate 200 on both sides of the control gate structure 232.

[0081] Reference Figure 10P-type body ion implantation is performed into the semiconductor substrate 200 to form a P-type body doped region 240.

[0082] In specific implementation, conventional ion implantation processes and their process parameters can be used to form the P-type bulk doped region 240. The embodiments of the present invention do not limit the specific process parameters.

[0083] Wherein, the first distance D1 between the bottom surface of the isolation gate trench 221 and the surface of the semiconductor substrate 200 is greater than the second distance D2 between the bottom surface of the P-type body doped region 240 and the surface of the semiconductor substrate 200, thereby allowing the isolation gate structure 231 to penetrate the P-type body doped region 240 and isolate the P-type body doped region 240 from the P-type pillar 210.

[0084] It should be noted that the p-type bulk doped region 240 can be as follows: Figures 7 to 11 The process flow shown, which is formed after the gate structure 230 is formed in the gate trench 220 and before the dielectric layer is formed, can also be formed in other process steps.

[0085] In another specific embodiment of the present invention, a P-type body doped region 240 may be formed in the semiconductor substrate 200 before the P-type pillar 210 is formed in the semiconductor substrate 200.

[0086] Specifically, it is possible Figure 7 Prior to the process steps shown, a semiconductor substrate 200 is provided, and a P-type body doped region 240 is formed within the semiconductor substrate 200.

[0087] In another specific embodiment of the present invention, a P-type body doped region 240 may be formed in the semiconductor substrate 200 after the P-type pillar 210 is formed in the semiconductor substrate 200 and before the semiconductor substrate 200 and the P-type pillar 210 are etched to form a gate trench 220.

[0088] Specifically, it is possible Figures 7 to 8 Between the process steps shown, a P-type body doped region 240 is formed within the semiconductor substrate 200.

[0089] In this embodiment of the invention, the P-type body doped region 240, P-type pillar 210 and gate structure 230 in the SJ-IGBT structure can be formed using a variety of process sequences. The formation sequence of the P-type body doped region 240 is not strictly limited, which effectively improves process flexibility, facilitates process improvement and process parameter adjustment, and helps to improve device performance optimization.

[0090] Reference Figure 11A dielectric layer 250 is formed, which covers the P-type body doped region 240, the gate structure 230, and the P-type pillar 210.

[0091] It should be pointed out that, in Figure 11 When the gate conductive layer of the isolation gate structure 231 shown fills the isolation gate trench 221, the top surface of the isolation gate structure 231 is flush with the surface of the control gate structure 232.

[0092] In specific implementations, the dielectric layer 250 can be selected from: a stacked structure of silicon oxide and silicon nitride, a silicon oxide layer, or a silicon nitride layer. The silicon oxide can be, for example, SiO2, and the silicon nitride can be, for example, Si3N4.

[0093] In this embodiment of the invention, by forming a gate trench 220, which includes an isolation gate trench 221, the bottom surface of each isolation gate trench 221 exposes the etched top surface of one or more P-type pillars 210. This allows the bottom surface of the isolation gate structure 231 formed within the isolation gate trench 221 to be lower than the P-type body doped region 240 and higher than the P-type pillars 210, effectively isolating the P-type body doped region 240 and the P-type pillars 210. This disconnects the electrical connection between the P-type body doped region 240 and the P-type pillars 210, effectively mitigating the problem of carriers (such as holes) being extracted during forward conduction of the device, enhancing device performance. Furthermore, the isolation gate structure 231 can be formed based on a conventional mask for forming the control gate structure 232 and its manufacturing process, eliminating the need for an additional mask. Compared to the prior art, which requires an additional isolation material layer, leading to increased production costs, the technical solution of this embodiment of the invention can reduce production costs and improve production efficiency. Furthermore, by adopting the above scheme, since both the P-type body doped region 240 and the gate structure 230 are located within the semiconductor substrate 200, the formation order of the P-type body doped region 240 is not restricted, and there is no limitation on process improvement and process parameter adjustment, which is beneficial to device performance optimization.

[0094] Then, a plug structure (Contact, CT)260 can be formed.

[0095] Specifically, the dielectric layer 250 can be etched to form a plug hole (not shown), and then a plug structure 260 can be formed in the plug hole.

[0096] The plug structure 260 can be formed at the location of the source doped region, or at other suitable locations.

[0097] Then a metal layer 270 can be formed on the surface of the dielectric layer 250, and a capping layer 271 can be formed on the surface of the metal layer 270.

[0098] The metal layer 270 can be electrically connected to the plug structure 260, and the plug material in the plug structure 260 that is not covered by the metal layer 270 can be removed during the metal etching process.

[0099] The cover layer 271 is used to protect the metal layer 270, and may include, for example, a passivation layer or a polymer material layer.

[0100] It should be noted that, in the embodiments of the present invention, the back side of the semiconductor substrate 200 may also be processed as needed, such as performing back thinning, forming a field stop layer, forming a shallow doped P-type anode layer on the back side, performing back metallization, etc. The embodiments of the present invention do not impose specific limitations on the processing method and process of the back side.

[0101] Reference Figure 12 , Figure 12 This is a cross-sectional structural diagram of another SJ-IGBT structure in an embodiment of the present invention. The following is a comparison with... Figure 12 Another SJ-IGBT structure shown is similar to Figure 11 The different aspects of the SJ-IGBT structure shown will be explained.

[0102] exist Figure 12 In another SJ-IGBT structure shown, the gate conductive layer of the isolation gate structure 231 covers the bottom surface and sidewall surface of the isolation gate trench, but does not fill the isolation gate trench. In this case, the dielectric layer 250 fills the remaining space in the isolation gate trench.

[0103] Specifically, if the gate conductive layer in the isolation gate trench does not fill the isolation gate trench, the space in the isolation gate trench will only be larger after the gate conductive layer is etched back. The isolation gate trench can be filled with the dielectric layer 250, and the isolation gate structure 231 can still be used to isolate the P-type body doped region 240 and the P-type pillar 210 without additional processes, thus further effectively controlling the improvement cost.

[0104] Reference Figure 13 , Figure 13 This is a cross-sectional structural diagram of another SJ-IGBT structure in an embodiment of the present invention. The following describes... Figure 13 Another SJ-IGBT structure shown is Figure 11 The different aspects of the SJ-IGBT structure shown will be explained.

[0105] exist Figure 13In another SJ-IGBT structure shown, source doped regions can be formed in both the control gate structure 232 and the semiconductor substrate 200 on both sides of the isolation gate 231. The plug structure 360 ​​formed thereafter can be formed at the location of the source doped region or at other suitable locations.

[0106] In this embodiment of the invention, an SJ-IGBT structure is also disclosed, referring to... Figure 11 The device may include: a semiconductor substrate 200; P-type pillars 210 located within the semiconductor substrate 200; a gate trench 220 located within the semiconductor substrate 200, the gate trench 220 including isolation gate trenches 221, the bottom surface of each isolation gate trench 221 exposing the etched top surfaces of one or more P-type pillars 210; and a gate structure 230 formed within the gate trench 220. The semiconductor substrate 200 has a P-type body doped region 240, and a first distance D1 between the bottom surface of the isolation gate trench 221 and the surface of the semiconductor substrate 200 is greater than a second distance D2 between the bottom surface of the P-type body doped region 240 and the surface of the semiconductor substrate 200, and less than a third distance D3 between the bottom surface of the P-type pillars 210 and the surface of the semiconductor substrate 200.

[0107] In this embodiment of the invention, by forming a gate trench 220, which includes an isolation gate trench 221, the bottom surface of each isolation gate trench 221 exposes the etched top surface of one or more P-type pillars 210. This allows the bottom surface of the isolation gate structure 231 formed within the isolation gate trench 221 to be lower than the P-type body doped region 240 and higher than the P-type pillars 210, effectively isolating the P-type body doped region 240 and the P-type pillars 210. This disconnects the electrical connection between the P-type body doped region 240 and the P-type pillars 210, effectively mitigating the problem of carriers (such as holes) being extracted during forward conduction of the device, enhancing device performance. Furthermore, the isolation gate structure 231 can be formed based on a conventional mask for forming the control gate structure 232 and its manufacturing process, eliminating the need for an additional mask. Compared to the prior art, which requires an additional isolation material layer, leading to increased production costs, the technical solution of this embodiment of the invention can reduce production costs and improve production efficiency. Furthermore, by adopting the above scheme, since both the P-type body doped region 240 and the gate structure 230 are located within the semiconductor substrate 200, the formation order of the P-type body doped region 240 is not restricted, and there is no limitation on process improvement and process parameter adjustment, which is beneficial to device performance optimization.

[0108] Furthermore, the isolation trench 221 corresponds one-to-one with the P-shaped pillar 210; wherein, the bottom surface of each isolation trench 221 exposes the entire etched top surface of the corresponding P-shaped pillar 210, and the bottom surface contour of the isolation trench 221 is larger than the top surface contour of the P-shaped pillar 210.

[0109] Further, the gate structure 230 includes: a gate oxide layer (not shown) located on the bottom surface and sidewall surfaces within the isolation gate trench 221; and a gate conductive layer (not shown) located on the surface of the gate oxide layer, the top surface of which is flush with the surface of the semiconductor substrate 200, or all or part of which is located on the sidewall surface of the isolation gate trench 221 and the thickness of which is less than the thickness of the isolation gate trench 221 (refer to reference). Figure 11 and Figure 12 ).

[0110] Furthermore, the SJ-IGBT structure further includes a P-type body doped region 240 located within the semiconductor substrate 200; wherein the P-type body doped region 240 is formed before the P-type pillars 210 are formed within the semiconductor substrate 200.

[0111] Furthermore, the SJ-IGBT structure further includes a P-type body doped region 240 located within the semiconductor substrate 200; wherein the P-type body doped region 240 is formed after the P-type pillar 210 is formed within the semiconductor substrate 200 and before the semiconductor substrate 200 and the P-type pillar 210 are etched to form the gate trench 220.

[0112] Furthermore, the SJ-IGBT structure further includes a P-type body doped region 240 located within the semiconductor substrate 200; wherein the P-type body doped region 240 is formed after the gate structure 230 is formed in the gate trench 220 and before the dielectric layer 250 is formed.

[0113] For the principles, specific implementation, and beneficial effects of the SJ-IGBT device, please refer to the previous description of the formation method of the SJ-IGBT device; it will not be repeated here.

[0114] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0115] In the embodiments of this application, "multiple" refers to two or more.

[0116] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0117] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming an SJ-IGBT structure, characterized in that, include: Provide semiconductor substrates; P-type pillars are formed within the semiconductor substrate; The semiconductor substrate and the P-type pillars are etched to form gate trenches, the gate trenches including isolation gate trenches, the isolation gate trenches corresponding one-to-one with the P-type pillars, the bottom surface of each isolation gate trench exposes the entire top surface of a P-type pillar after etching, and the bottom surface profile of the isolation gate trench is larger than the top surface profile of the P-type pillar. A gate structure is formed within the gate trench; The semiconductor substrate has a P-type body doped region. The first distance between the bottom surface of the isolation gate trench and the surface of the semiconductor substrate is greater than the second distance between the bottom surface of the P-type body doped region and the surface of the semiconductor substrate, and less than the third distance between the bottom surface of the P-type pillar and the surface of the semiconductor substrate.

2. The method for forming the SJ-IGBT structure according to claim 1, characterized in that, Etching the semiconductor substrate and the P-type pillars to form gate trenches includes: A patterned mask layer is formed on the surface of the semiconductor substrate, wherein the patterned mask layer covers the top surface of the P-shaped pillar with an etchable contour, and the etchable contour of the patterned mask layer on the top surface of the P-shaped pillar is larger than the top surface contour of the P-shaped pillar. The patterned mask layer is used to etch the semiconductor substrate and the P-type pillars.

3. The method for forming the SJ-IGBT structure according to claim 1, characterized in that, A gate structure is formed within the gate trench, including: A gate oxide layer is formed on the bottom surface and sidewall surface within the isolation gate trench; A gate conductive layer is formed on the surface of the gate oxide layer, wherein the gate conductive layer fills the isolation gate trench, or the gate conductive layer covers the bottom surface and sidewall surface of the isolation gate trench, but does not fill the isolation gate trench; The gate conductive layer is etched back to obtain an isolation gate structure located within the isolation gate trench.

4. The method for forming the SJ-IGBT structure according to claim 3, characterized in that, If the gate conductive layer fills the isolation gate trench, the top surface of the etched gate conductive layer is flush with the surface of the semiconductor substrate. If the gate conductive layer covers the bottom surface and sidewall surface of the isolation gate trench, but does not fill the isolation gate trench, then all or part of the etched-back gate conductive layer is located on the sidewall surface of the isolation gate trench, and the thickness of the etched-back gate conductive layer is less than the thickness of the isolation gate trench.

5. The method for forming the SJ-IGBT structure according to claim 3, characterized in that, The method further includes: After forming the gate structure in the gate trench, a dielectric layer is formed, which covers the P-type body doped region, the gate structure, and the P-type pillar. If the gate conductive layer covers the bottom surface and sidewall surface of the isolation gate trench but does not fill the isolation gate trench, then the dielectric layer fills the remaining space in the isolation gate trench.

6. The method for forming the SJ-IGBT structure according to claim 1, characterized in that, Also includes: Before forming P-type pillars in the semiconductor substrate, P-type body ion implantation is performed in the semiconductor substrate to form a P-type body doped region.

7. The method for forming the SJ-IGBT structure according to claim 1, characterized in that, Also includes: After forming P-type pillars in the semiconductor substrate, and before etching the semiconductor substrate and the P-type pillars to form gate trenches, P-type body ion implantation is performed in the semiconductor substrate to form a P-type body doped region.

8. The method for forming the SJ-IGBT structure according to claim 1, characterized in that, Also includes: After the gate structure is formed in the gate trench and before the dielectric layer is formed, P-type body ion implantation is performed in the semiconductor substrate to form a P-type body doped region.

9. An SJ-IGBT structure, characterized in that, include: Semiconductor substrate; P-type pillars are located within the semiconductor substrate; A gate trench is located within the semiconductor substrate. The gate trench includes an isolation gate trench, which corresponds one-to-one with the P-type pillar. The bottom surface of each isolation gate trench exposes the entire etched top surface of a P-type pillar, and the bottom surface profile of the isolation gate trench is larger than the top surface profile of the P-type pillar. A gate structure is formed within the gate trench; The semiconductor substrate has a P-type body doped region. The first distance between the bottom surface of the isolation gate trench and the surface of the semiconductor substrate is greater than the second distance between the bottom surface of the P-type body doped region and the surface of the semiconductor substrate, and less than the third distance between the bottom surface of the P-type pillar and the surface of the semiconductor substrate.

10. The SJ-IGBT structure according to claim 9, characterized in that, The gate structure includes: A gate oxide layer is located on the bottom surface and sidewall surface within the isolation gate trench; A gate conductive layer is located on the surface of the gate oxide layer, the top surface of the gate conductive layer is flush with the surface of the semiconductor substrate, or all or part of the gate conductive layer is located on the sidewall surface of the isolation gate trench and the thickness of the gate conductive layer is less than the thickness of the isolation gate trench.

11. The SJ-IGBT structure according to claim 9, characterized in that, Also includes: The P-type bulk doped region is located within the semiconductor substrate; The P-type body doped region is formed before the P-type pillar is formed in the semiconductor substrate.

12. The SJ-IGBT structure according to claim 9, characterized in that, Also includes: The P-type bulk doped region is located within the semiconductor substrate; The P-type body doped region is formed after the P-type pillars are formed in the semiconductor substrate and before the semiconductor substrate and the P-type pillars are etched to form the gate trench.

13. The SJ-IGBT structure according to claim 9, characterized in that, Also includes: The P-type bulk doped region is located within the semiconductor substrate; The P-type body doped region is formed after the gate structure is formed in the gate trench and before the dielectric layer is formed.

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