Method for fabricating the inter-gate dielectric layer of SGT semiconductor devices

Abstract

This invention discloses a method for manufacturing an inter-gate dielectric layer of an SGT semiconductor device, comprising: Step 1, forming a gate trench and a bottom dielectric layer, wherein the bottom dielectric layer covers the inner and outer surfaces of the gate trench. Step 2, forming a shielding gate conductive material layer and etching back the shielding gate conductive material layer. Step 3, using the bottom dielectric layer as a mask, forming a first inter-gate dielectric layer of desired thickness on the exposed top surface of the shielding gate conductive material layer. Step 4, forming a first mask layer to protect the top region of the first inter-gate dielectric layer. Step 5, performing a first etching using the first mask layer as a mask; after the first etching, the bottom dielectric layer located above the top surface of the shielding gate conductive material layer serves as a second inter-gate dielectric layer. Step 6, removing the first mask layer. Step 7, forming the gate dielectric layer and the gate conductive material layer. This invention allows for independent adjustment of the thickness of the inter-gate dielectric layer with high quality and a simple process.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a method for manufacturing the inter-gate dielectric layer of a trench gate (SGT) semiconductor device with a shielded gate. Background Technology

[0002] In SGT semiconductor devices such as SGT MOSFETs, the most crucial process step is the isolation between the two polysilicon gates in the gate trench—the polysilicon shield gate and the polysilicon gate itself. This isolation is typically achieved using an oxide layer, known as the inter-polysilicon oxide (IPO). The polysilicon shield gate connects to the source, which is composed of a front-side metal layer; hence, the polysilicon shield gate is also called the source polysilicon. The polysilicon gate connects to the gate, which is also composed of a front-side metal layer. The thickness and stability of the IPO not only affect the isolation effect between the gate and source but also the input capacitance, making it critical for the SGT process.

[0003] Currently, there are two main IPO production methods in the industry: thermal oxidation process for IPO formation and high-density plasma (HDP) chemical vapor deposition (CVD) process for IPO deposition.

[0004] In the thermal oxidation process for forming the IPO, after the bottom source polysilicon is formed, heavy ion implantation is performed to further create defects on the surface of the source polysilicon. Meanwhile, the semiconductor material, such as silicon, in the sidewall channel region of the gate trench (Mesa) remains in a relatively good single-crystal structure. Then, a thermal oxidation process is performed to form the IPO on top of the source polysilicon, while a gate oxide layer (GOX) is formed on the sidewall of the gate trench. Taking advantage of the numerous defects on the surface of the source polysilicon, the thickness of the IPO is made greater than the thickness of the gate oxide layer. This process is simple in steps but quite difficult. Furthermore, the IPO to GOX thickness ratio is fixed, limiting the adjustable thickness range and making it unsuitable for thin gate oxide products. Additionally, a significant thinning of the IPO is likely to occur at the polycorner of the source polysilicon.

[0005] In HDP CVD deposition of the IPO (Initial Gate Isolation), an oxide layer is formed to completely fill the gate trench using HDP CVD, and then the oxide layer is etched back to form the IPO of the desired thickness. This process allows for a wide adjustable range of IPO thickness, unaffected by the thickness of the gate oxide layer. However, the process is complex and costly. Furthermore, it is limited by the filling capacity of HDP, making it difficult to achieve an aspect ratio greater than 3. The IPO thickness depends on the oxide layer etch-back, resulting in significant fluctuations. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a method for manufacturing an inter-gate dielectric layer of an SGT semiconductor device, wherein the thickness of the inter-gate dielectric layer can be independent of the thickness of the gate dielectric layer and thus the thickness of the inter-gate dielectric layer can be independently adjusted and the quality of the inter-gate dielectric layer can be guaranteed, and the process is simple and the process difficulty is low.

[0007] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing the inter-gate dielectric layer of an SGT semiconductor device, comprising the following steps:

[0008] Step 1: Form a gate trench on a semiconductor substrate, and form a bottom dielectric layer in the gate trench. The bottom dielectric layer covers the bottom surface and side surface of the gate trench as well as the surface outside the gate trench.

[0009] Step 2: Form a shielding gate conductive material layer and etch back the shielding gate conductive material layer. The etched shielding gate conductive material layer fills the bottom region of the gate trench.

[0010] Step 3: Using the bottom dielectric layer as a mask, form a first inter-gate dielectric layer of the required thickness on the exposed top surface of the shielding gate conductive material layer; during the formation of the first inter-gate dielectric layer, the bottom dielectric layer is used to protect the side of the gate trench on the top of the shielding gate conductive material layer and the semiconductor substrate outside the gate trench.

[0011] Step 4: Form a first mask layer to protect the top region of the first inter-gate dielectric layer.

[0012] Step 5: Perform the first etching using the first mask layer as a mask.

[0013] The first etching removes the bottom dielectric layer outside the gate trench and etches the bottom dielectric layer on the side of the gate trench to the required position. After the first etching, the top surface of the bottom dielectric layer on the side of the gate trench is located above the top surface of the shielding gate conductive material layer. The bottom dielectric layer located above the top surface of the shielding gate conductive material layer serves as the second inter-gate dielectric layer, and the first inter-gate dielectric layer and the second inter-gate dielectric layer together constitute the inter-gate dielectric layer.

[0014] Step 6: Remove the first mask layer.

[0015] Step 7: Form a gate dielectric layer on the side of the gate trench at the top of the inter-gate dielectric layer, and fill the gate trench with a gate conductive material layer.

[0016] A further improvement is that, in step one, the semiconductor substrate includes a silicon substrate.

[0017] A further improvement is that the material of the bottom dielectric layer includes an oxide layer;

[0018] In step seven, the material of the gate dielectric layer includes an oxide layer.

[0019] A further improvement is that the material of the shielding gate conductive material layer includes polycrystalline silicon;

[0020] The material of the gate conductive material layer includes polycrystalline silicon.

[0021] A further improvement is that, in step three, the first inter-gate dielectric layer is an oxide layer and is formed on top of the shielding gate conductive material layer using a thermal oxidation process for self-alignment.

[0022] A further improvement is that, in step four, after forming the first mask layer, the first mask layer completely fills the remaining gaps of the gate trench and extends to the surface of the bottom dielectric layer outside the remaining gaps of the gate trench.

[0023] The next step includes a step of patterning the first mask layer, and using the top region of the first inter-gate dielectric layer of the patterned first mask layer for protection.

[0024] A further improvement is that, in step four, a first opening is formed in the patterned first mask layer in the device cell region. The first opening is located on both sides of the gate trench and exposes the surface of the bottom dielectric layer.

[0025] In step five, the first etching is performed using wet etching. In wet etching, the wet etching solution starts etching the bottom dielectric layer from the bottom surface of the first opening, and then gradually etches the bottom dielectric layer along the area defined between the first mask layer and the outer surface of the gate trench, as well as the side surface of the first mask layer and the gate trench, until the desired position is reached. The thickness of the second inter-gate dielectric layer is determined by the wet etching.

[0026] A further improvement is that, in step four, the first mask layer is made of photoresist and formed by a coating process.

[0027] A further improvement is that, in step four, a photolithography process is used to pattern the first mask layer.

[0028] A further improvement is that, in step four, the first photomask used in the photolithography process is formed by creating the pattern of the first opening in the device unit area based on the second photomask in the active region.

[0029] A further improvement is that, in step one, the top view structure of the gate trench is a strip-shaped structure.

[0030] Multiple gate trenches are formed on the semiconductor substrate, and in top view, the gate trenches are arranged in parallel.

[0031] On a top view, each of the first openings and the gate trenches are parallel.

[0032] A further improvement is that multiple aligned first openings are arranged on the same side of the gate trench; the length of each first opening is shorter than the length of the gate trench, the length sides of each first opening are aligned, and the width sides of each first opening are spaced apart by material of the first mask layer to enhance the support of the first mask layer.

[0033] A further improvement is that, in step one, a first epitaxial layer doped with a first conductivity type is formed on the surface of the semiconductor substrate, and the gate trench is formed in the first epitaxial layer.

[0034] It also includes the following steps:

[0035] Step 8: Form a body region doped with a second conductivity type on the surface of the semiconductor substrate.

[0036] The gate conductive material layer passes through the body region, and the surface of the body region covered by the side of the gate conductive material layer serves as the channel region.

[0037] The first epitaxial layer at the bottom of the body region serves as the drift region.

[0038] Step 9: Form a heavily doped source region of the first conductivity type on the surface of the body region.

[0039] A further improvement is that, in step five, the first etching ensures that the top surface of the formed second inter-gate dielectric layer is located at the bottom of the body region.

[0040] A further improvement is that the top surface of the second inter-gate dielectric layer is equal to, higher than or lower than the top surface of the first inter-gate dielectric layer.

[0041] A further improvement is that, after step two is completed, the bottom dielectric layer on top of the shielding gate conductive material layer is thinned, and then step three is performed to form the first inter-gate dielectric layer.

[0042] A further improvement is that the SGT semiconductor device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type.

[0043] Alternatively, the SGT semiconductor device is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0044] Unlike existing methods that involve etching back the bottom dielectric layer after etching back the shielding gate conductive material layer, this invention does not first etch back the bottom dielectric layer. Instead, it utilizes the characteristic of the bottom dielectric layer self-aligning to expose the top surface of the shielding gate conductive material layer. The bottom dielectric layer is used as a mask to directly form a first inter-gate dielectric layer of the required thickness on the exposed top surface of the shielding gate conductive material layer. Then, a first mask layer is formed to protect the top area of ​​the first inter-gate dielectric layer, and the bottom dielectric layer is etched back using the first mask layer to form a second inter-gate dielectric layer of the required thickness. The first and second inter-gate dielectric layers together constitute the inter-gate dielectric layer. The thicknesses of the first and second inter-gate dielectric layers are independent of the thickness of the gate dielectric layer. Therefore, this invention enables the thickness of the inter-gate dielectric layer to be independent of the thickness of the gate dielectric layer, thereby allowing for independent adjustment of the thickness of the inter-gate dielectric layer.

[0045] In this invention, the shielding gate conductive material layer and the gate conductive material layer are mainly isolated by a first inter-gate dielectric layer. During the formation of the first inter-gate dielectric layer, the bottom dielectric layer can protect the side of the gate trench at the top of the shielding gate conductive material layer and the semiconductor substrate outside the gate trench. The channel region is mainly located on the semiconductor substrate on the side of the gate trench at the top of the shielding gate conductive material layer. Therefore, the formation process of the first inter-gate dielectric layer will not affect the performance of the channel region, so a first inter-gate dielectric layer of good quality can be formed. For example, a first inter-gate dielectric layer composed of an oxide layer can be formed by a high-temperature oxidation process. The bottom dielectric layer is also usually formed by a high-temperature oxidation process, so the quality of the second inter-gate dielectric layer is also good. Therefore, this invention can also obtain an inter-gate dielectric layer of good quality.

[0046] In addition, since the shielding gate conductive material layer and the gate conductive material layer are mainly isolated by the first inter-gate dielectric layer in this invention, the accuracy requirement for the thickness of the second inter-gate dielectric layer is not very high. The fluctuation of the first etching will not have a significant impact on the isolation between the shielding gate conductive material layer and the gate conductive material layer. Therefore, this invention also has the advantages of simple process flow and low process difficulty, which is also conducive to achieving stable production. Attached Figure Description

[0047] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0048] Figure 1 This is a flowchart of a method for manufacturing the inter-gate dielectric layer of an SGT semiconductor device according to an embodiment of the present invention;

[0049] Figures 2A-2G A schematic diagram of the device cross-sectional structure in each step of the manufacturing method of the inter-gate dielectric layer of the SGT semiconductor device according to an embodiment of the present invention;

[0050] Figure 3 yes Figure 2DThe corresponding top view. Detailed Implementation

[0051] like Figure 1 The diagram shown is a flowchart of a method for manufacturing the inter-gate dielectric layer 105 of an SGT semiconductor device according to an embodiment of the present invention; as shown... Figures 2A to 2G As shown, this is a schematic diagram of the cross-sectional structure of the device in each step of the manufacturing method of the gate dielectric layer 105 of the SGT semiconductor device according to an embodiment of the present invention; as follows: Figure 3 As shown, is Figure 2D The corresponding top view; the manufacturing method of the inter-gate dielectric layer 105 of the SGT semiconductor device according to the present invention includes the following steps:

[0052] Step 1, such as Figure 2A As shown, a gate trench 102 is formed on a semiconductor substrate 101.

[0053] In the process of forming the gate trench 102, a hard mask layer 201 needs to be formed first. The hard mask layer 102 is a single oxide layer or a stacked layer of oxide-nitride-oxide (ONO).

[0054] Then, photolithography is used to open the formation region of the gate trench 102 shown;

[0055] Subsequently, the hard mask layer 201 and the semiconductor substrate 101 are etched sequentially to form the gate trench 102.

[0056] like Figure 2B As shown, a bottom dielectric layer 103a is formed in the gate trench 102, and the bottom dielectric layer 103a covers the bottom surface and side surface of the gate trench 102 as well as the surface outside the gate trench 102.

[0057] In this embodiment of the invention, the semiconductor substrate 101 includes a silicon substrate.

[0058] The material of the bottom dielectric layer 103a includes an oxide layer.

[0059] In some embodiments, a first epitaxial layer doped with a first conductivity type is further formed on the surface of the semiconductor substrate 101, and the gate trench 102 is formed in the first epitaxial layer.

[0060] Step Two, as follows Figure 2B As shown, a shielding gate conductive material layer 104 is formed and the shielding gate conductive material layer 104 is etched back. The etched shielding gate conductive material layer 104 fills the bottom region of the gate trench 102.

[0061] In this embodiment of the invention, the material of the shielding gate conductive material layer 104 includes polysilicon. When polysilicon is used, the shielding gate conductive material layer 104 is also called shield poly. In addition, the shielding gate conductive material layer 104 is connected to the source electrode, so it is also called source polysilicon.

[0062] Step 3, as follows Figure 2C As shown, a first inter-gate dielectric layer 1051 of the required thickness is formed on the exposed top surface of the shielding gate conductive material layer 104 using the bottom dielectric layer 103a as a mask; during the formation of the first inter-gate dielectric layer 1051, the bottom dielectric layer 103a is used to protect the side of the gate trench 102 on the top of the shielding gate conductive material layer 104 and the semiconductor substrate 101 outside the gate trench 102.

[0063] In this embodiment of the invention, the first inter-gate dielectric layer 1051 is an oxide layer and is formed on top of the shielding gate conductive material layer 104 by a thermal oxidation process with self-alignment.

[0064] In other embodiments, it can also be: such as Figure 2C1 As shown, after step two is completed, the bottom dielectric layer 103a on top of the shielding gate conductive material layer 104 is thinned before step three is performed to form the first inter-gate dielectric layer 1051; thinning the bottom dielectric layer 103a first helps to control the stress performance of the process.

[0065] Step 4, as follows Figure 2D As shown, a first mask layer 202 is formed to protect the top region of the first inter-gate dielectric layer 1051.

[0066] In this embodiment of the invention, after the first mask layer 202 is formed, the first mask layer 202 completely fills the remaining gaps of the gate trench 102 and extends to the surface of the bottom dielectric layer 103a outside the remaining gaps of the gate trench 102.

[0067] The next step includes a step of patterning the first mask layer 202, and using the patterned first mask layer 202 to protect the top region of the first inter-gate dielectric layer 1051.

[0068] Also refer to Figure 2D and Figure 3 As shown, in the device cell region, a first opening 203 is formed in the patterned first mask layer 202. The first opening 203 is located on both sides of the gate trench 102, and the first opening 203 exposes the surface of the bottom dielectric layer 103a at the bottom.

[0069] In some embodiments, the first mask layer 202 is made of photoresist and is formed by a coating process.

[0070] The first mask layer 202 is patterned using photolithography.

[0071] The first photomask used in the photolithography process is formed by setting the pattern of the first opening 203 in the device unit area based on the second photomask in the active area.

[0072] The top view of the gate trench 102 is a strip-shaped structure.

[0073] Multiple gate trenches 102 are formed on the semiconductor substrate 101, and in top view, the gate trenches 102 are arranged in parallel.

[0074] On a top view, each of the first openings 203 and the gate trenches 102 are parallel.

[0075] Multiple aligned first openings 203 are arranged on the same side of the gate trench 102; the length of each first opening 203 is shorter than the length of the gate trench 102, the length sides of each first opening 203 are aligned, and the width sides of each first opening 203 are spaced apart by material of the first mask layer 202 to enhance the support of the first mask layer 202. Figure 3 In the middle, the material of the first mask layer 202 between the width sides of each of the first openings 203 is marked separately by a mark 202a, and the material 202a serves as a lateral support strip.

[0076] Step 5, as follows Figure 2E As shown, the first etching is performed using the first mask layer 202 as a mask.

[0077] The first etching removes the bottom dielectric layer 103a outside the gate trench 102 and etches the bottom dielectric layer 103a on the side of the gate trench 102 to the required position. After the first etching, the top surface of the bottom dielectric layer 103 on the side of the gate trench 102 is located above the top surface of the shielding gate conductive material layer 104. The bottom dielectric layer 103 located above the top surface of the shielding gate conductive material layer 104 serves as the second inter-gate dielectric layer 1052. The first inter-gate dielectric layer 1051 and the second inter-gate dielectric layer 1052 together form the inter-gate dielectric layer 105. Figure 2EIn the diagram, the bottom dielectric layer after the first etching is marked separately with the symbol 103. The bottom dielectric layer 103 is isolated between the shielding gate conductive material layer 104 and the semiconductor substrate 101, so the bottom dielectric layer 103 is also called the shield dielectric layer. The bottom dielectric layer 103 is usually made of oxide layer, so it is also called shield oxide layer.

[0078] In this embodiment of the invention, the first etching is performed using wet etching. In the wet etching, as shown by arrow 204, the wet etching solution begins to etch the bottom dielectric layer 103a from the bottom surface of the first opening 203. Then, along the area defined between the outer surface of the first mask layer 202 and the gate trench 102 and the side surface of the first mask layer 202 and the gate trench 102, the bottom dielectric layer 103a is gradually etched until the desired position is reached. The thickness of the second inter-gate dielectric layer 1052 is determined by the wet etching.

[0079] Combination Figure 3 and Figure 2E As shown, the material 202a of the first mask layer 202 between the width sides of each of the first openings 203, i.e. the transverse support strip, will support the material of the entire first mask layer 202 during the wet etching process, preventing the first mask layer 202 from collapsing when the first opening 203 is too long.

[0080] Step Six, as Figure 2F As shown, the first mask layer 202 is removed.

[0081] Step 7, as follows Figure 2G As shown, a gate dielectric layer is formed on the side of the gate trench 102 at the top of the inter-gate dielectric layer 105, and a gate conductive material layer is filled in the gate trench 102.

[0082] In this embodiment of the invention, the material of the gate dielectric layer 106 includes an oxide layer.

[0083] The gate conductive material layer 107 is made of polysilicon, and the gate conductive material layer 107 is also called a polysilicon gate.

[0084] like Figure 2G As shown, the SGT semiconductor device in this embodiment of the invention is an SGT MOSFET, and the invention further includes the following steps:

[0085] Step 8: Form a body region 108 doped with a second conductivity type on the surface of the semiconductor substrate 101.

[0086] The gate conductive material layer 107 passes through the body region 108, and the surface of the body region 108 covered by the side of the gate conductive material layer 107 serves as a channel region.

[0087] The first epitaxial layer at the bottom of the body region 108 serves as a drift region.

[0088] In step five above, the first etching only needs to ensure that the surface of the second inter-gate dielectric layer 1052 formed is located at the bottom of the body region 108. Therefore, the requirements for the first etching in this embodiment of the invention are not very high; it is only necessary to ensure that the channel region can be formed. Figure 2G Although it is shown that the top surface of the second inter-gate dielectric layer 1052 is higher than the top surface of the first inter-gate dielectric layer 1051, in other embodiments, the top surface of the second inter-gate dielectric layer 1052 may be equal to or lower than the top surface of the first inter-gate dielectric layer 1051.

[0089] Step 9: Form a source region 109 with a first conductivity type heavily doped on the surface of the body region 108.

[0090] Following that, it also includes:

[0091] Interlayer membrane 111 is formed.

[0092] An opening for a contact hole 112 is formed through the interlayer film 111, and a heavily doped bulk contact region 110 of the second conductivity type is formed at the bottom of the opening of the contact hole 112 at the top of the source region 109.

[0093] The contact hole 112 is formed by filling the opening of the contact hole 112 with metal. The contact hole 112 at the top of the source region 109 contacts the source region 109 and is electrically connected to the body region 108 through the body contact region 110.

[0094] A front-side metal layer 113 is formed, and the front-side metal layer 113 is patterned to form the source and gate electrodes. Both the source region 109 and the shielding gate conductive material layer 104 are connected to the source electrode through the top contact hole 112. Figure 2G Only the contact hole 112 at the top of the source region 109 is shown; the gate conductive material layer 107 is connected to the gate through the contact hole 112 at the top.

[0095] The following back-side finishes are also included:

[0096] The semiconductor substrate 101 is thinned, and then heavy doped ions of the first conductivity type are implanted on the back side to form a drain region on the back side of the drift region.

[0097] In this embodiment of the invention, the SGT semiconductor device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type. In other embodiments, the SGT semiconductor device can also be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0098] Unlike existing methods where the bottom dielectric layer 103a is etched back after the shielding gate conductive material layer 104 is etched back, in this embodiment of the invention, the bottom dielectric layer 103a is not etched back first. Instead, taking advantage of the characteristic that the bottom dielectric layer 103a self-aligns and exposes the top surface of the shielding gate conductive material layer 104, the first inter-gate dielectric layer 1051 of the required thickness is directly formed on the exposed top surface of the shielding gate conductive material layer 104 using the bottom dielectric layer 103a as a mask. Then, a first mask layer 202 is formed to protect the first inter-gate dielectric layer 1051. The top region of 51 is etched back onto the bottom dielectric layer 103a using the first mask layer 202 as a mask to form a second inter-gate dielectric layer 1052 of the required thickness. The first inter-gate dielectric layer 1051 and the second inter-gate dielectric layer 1052 together form the inter-gate dielectric layer 105. The thicknesses of the first inter-gate dielectric layer 1051 and the second inter-gate dielectric layer 1052 are independent of the thickness of the gate dielectric layer. Therefore, the embodiment of the present invention enables the thickness of the inter-gate dielectric layer 105 to be independent of the thickness of the gate dielectric layer, thereby enabling independent adjustment of the thickness of the inter-gate dielectric layer 105.

[0099] In this embodiment of the invention, the shielding gate conductive material layer 104 and the gate conductive material layer are mainly isolated by the first inter-gate dielectric layer 1051. During the formation of the first inter-gate dielectric layer 1051, the bottom dielectric layer 103a can protect the side of the gate trench 102 at the top of the shielding gate conductive material layer 104 and the semiconductor substrate 101 outside the gate trench 102. The channel region is mainly located on the semiconductor substrate 101 on the side of the gate trench 102 at the top of the shielding gate conductive material layer 104. Therefore, the formation process of the first inter-gate dielectric layer 1051 will not affect the performance of the channel region, so a first inter-gate dielectric layer 1051 of good quality can be formed. For example, a high-temperature oxidation process can be used to form the first inter-gate dielectric layer 1051 composed of an oxide layer. The bottom dielectric layer 103a is also usually formed by a high-temperature oxidation process, so the quality of the second inter-gate dielectric layer 1052 is also good. Therefore, this embodiment of the invention can also obtain a high-quality inter-gate dielectric layer 105.

[0100] In addition, since the shielding gate conductive material layer 104 and the gate conductive material layer are mainly isolated by the first inter-gate dielectric layer 1051 in the embodiments of the present invention, the accuracy requirement for the thickness of the second inter-gate dielectric layer 1052 is not very high. The fluctuation of the first etching will not have a significant impact on the isolation between the shielding gate conductive material layer 104 and the gate conductive material layer. Therefore, the embodiments of the present invention also have the advantages of simple process flow and low process difficulty, which is also conducive to achieving stable production.

[0101] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing an inter-gate dielectric layer of an SGT semiconductor device, characterized in that, Includes the following steps: Step 1: Form a gate trench on a semiconductor substrate, and form a bottom dielectric layer in the gate trench, the bottom dielectric layer covering the bottom surface and side surface of the gate trench and the surface outside the gate trench; Step 2: Form a shielding gate conductive material layer and etch back the shielding gate conductive material layer. The etched shielding gate conductive material layer fills the bottom region of the gate trench. Step 3: Using the bottom dielectric layer as a mask, form a first inter-gate dielectric layer of the required thickness on the exposed top surface of the shielding gate conductive material layer; During the formation of the first inter-gate dielectric layer, the bottom dielectric layer is used to protect the side of the gate trench on top of the shielding gate conductive material layer and the semiconductor substrate outside the gate trench; Step 4: Form a first mask layer to protect the top region of the first inter-gate dielectric layer; Step 5: Perform the first etching using the first mask layer as a mask; The first etching removes the bottom dielectric layer outside the gate trench and etches the bottom dielectric layer on the side of the gate trench to the required position. After the first etching, the top surface of the bottom dielectric layer on the side of the gate trench is located above the top surface of the shielding gate conductive material layer. The bottom dielectric layer located above the top surface of the shielding gate conductive material layer serves as the second inter-gate dielectric layer, and the first inter-gate dielectric layer and the second inter-gate dielectric layer together constitute the inter-gate dielectric layer; Step 6: Remove the first mask layer; Step 7: Form a gate dielectric layer on the side of the gate trench at the top of the inter-gate dielectric layer, and fill the gate trench with a gate conductive material layer.

2. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 1, characterized in that: In step one, the semiconductor substrate includes a silicon substrate.

3. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 2, characterized in that: The material of the bottom dielectric layer includes an oxide layer; In step seven, the material of the gate dielectric layer includes an oxide layer.

4. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 3, characterized in that: The material of the conductive material layer of the shielding gate includes polycrystalline silicon; The material of the gate conductive material layer includes polycrystalline silicon.

5. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 4, characterized in that: In step three, the first inter-gate dielectric layer is an oxide layer and is formed on top of the shielding gate conductive material layer using a thermal oxidation process for self-alignment.

6. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 1, characterized in that: In step four, after the first mask layer is formed, the first mask layer completely fills the remaining gaps of the gate trench and extends to the surface of the bottom dielectric layer outside the remaining gaps of the gate trench. The next step includes a step of patterning the first mask layer, and using the top region of the first inter-gate dielectric layer of the patterned first mask layer for protection.

7. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 6, characterized in that: In step four, a first opening is formed in the patterned first mask layer in the device cell region. The first opening is located on both sides of the gate trench and exposes the surface of the bottom dielectric layer. In step five, the first etching is performed using wet etching. In wet etching, the wet etching solution starts etching the bottom dielectric layer from the bottom surface of the first opening, and then gradually etches the bottom dielectric layer along the area defined between the first mask layer and the outer surface of the gate trench, as well as the side surface of the first mask layer and the gate trench, until the desired position is reached. The thickness of the second inter-gate dielectric layer is determined by the wet etching.

8. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 7, characterized in that: In step four, the first mask layer is formed using photoresist and a coating process.

9. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 8, characterized in that: In step four, photolithography is used to pattern the first mask layer.

10. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 9, characterized in that: In step four, the first photomask used in the photolithography process is formed by creating the pattern of the first opening in the device unit area based on the second photomask in the active region.

11. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 10, characterized in that: In step one, the top view of the gate trench is a strip-shaped structure; Multiple gate trenches are formed on the semiconductor substrate, and in top view, the gate trenches are arranged in parallel. On a top view, each of the first openings and the gate trenches are parallel.

12. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 11, characterized in that: Multiple aligned first openings are arranged on the same side of the gate trench; the length of each first opening is shorter than the length of the gate trench, the length sides of each first opening are aligned, and the width sides of each first opening are spaced apart by material of the first mask layer to enhance the support of the first mask layer.

13. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 1, characterized in that: In step one, a first epitaxial layer doped with a first conductivity type is also formed on the surface of the semiconductor substrate, and the gate trench is formed in the first epitaxial layer; It also includes the following steps: Step 8: Form a bulk region doped with a second conductivity type on the surface of the semiconductor substrate; The gate conductive material layer passes through the body region, and the surface of the body region covered by the side of the gate conductive material layer serves as the channel region. The first epitaxial layer at the bottom of the body region serves as the drift region; Step 9: Form a heavily doped source region of the first conductivity type on the surface of the body region.

14. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 13, characterized in that: In step five, the first etching ensures that the top surface of the formed second inter-gate dielectric layer is located at the bottom of the body region.

15. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 14, characterized in that: The top surface of the second inter-gate dielectric layer is equal to, higher than or lower than the top surface of the first inter-gate dielectric layer.

16. The method for manufacturing the inter-gate dielectric layer of the SGT semiconductor device as described in claim 1, characterized in that: After step two is completed, the bottom dielectric layer on top of the shielding gate conductive material layer is thinned, and then step three is performed to form the first inter-gate dielectric layer.

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