Voltage multiplication circuit and voltage multiplication method

Abstract

The application discloses a voltage multiplication circuit and a voltage multiplication method. The circuit comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a first switch group, a second switch group, a third switch group, a first switch control unit and a second switch control unit. The first end of the first capacitor and the second capacitor is pre-charged. A pulse signal is provided to the second end of the first capacitor and the second capacitor, so that the first end of the first capacitor and the second capacitor generates a voltage. The fifth capacitor is pre-charged, and the first end of the third capacitor and the fourth capacitor is pre-charged by an input voltage, so that the first end of the fifth capacitor is charged alternately by the third capacitor and the fourth capacitor based on the voltage of the first end of the first capacitor and the second capacitor to generate an output voltage. According to the voltage multiplication circuit and the voltage multiplication method, a high enough high-side power supply voltage can be generated when the power supply voltage is low, and the demand of the high-side power supply voltage is met.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a voltage multiplier circuit and a voltage multiplication method. Background Technology

[0002] Traditional high-side power supply circuits that generate a high-side voltage domain often experience voltage loss during voltage domain conversion. The difference between the high-side power supply voltage and the input voltage is often only 0.8 times the power supply voltage. This means that when the power supply voltage is low, the difference between the high-side power supply voltage and the input voltage will be even lower, and an excessively low high-side power supply voltage may not be sufficient for the circuit to operate normally.

[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a voltage multiplication circuit and a voltage multiplication method that can generate a sufficiently high high-side power supply even when the power supply voltage is low, so as to meet the normal high-side power supply voltage requirements.

[0005] To achieve the above objectives, embodiments of the present invention provide a voltage multiplier circuit, comprising: a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a first switch group, a second switch group, a third switch group, a first switch control unit, and a second switch control unit.

[0006] The first terminal of the first capacitor and the first terminal of the second capacitor are connected to the power supply voltage through the first switch group, and the second terminal of the first capacitor and the second terminal of the second capacitor are used to receive pulse signals.

[0007] The first switch control unit is connected to the first terminal of the first capacitor and the second terminal of the third capacitor. The first switch control unit controls the switching between the first terminal of the first capacitor and the second terminal of the third capacitor based on the first control signal.

[0008] The second switch control unit is connected to the first terminal of the second capacitor and the second terminal of the fourth capacitor. The second switch control unit controls the switching between the first terminal of the second capacitor and the second terminal of the fourth capacitor based on the second control signal.

[0009] The first terminal of the third capacitor and the first terminal of the fourth capacitor are connected to the second terminal of the fifth capacitor and the signal input terminal through the second switch group. The first terminal of the third capacitor and the first terminal of the fourth capacitor are also connected to the first terminal of the fifth capacitor and the signal output terminal through the third switch group.

[0010] In one or more embodiments of the present invention, the first switch group includes a first MOSFET and a second MOSFET, the source of the first MOSFET and the source of the second MOSFET are connected to a power supply voltage, the drain of the first MOSFET is connected to the gate of the second MOSFET and a first terminal of a first capacitor, and the drain of the second MOSFET is connected to the gate of the first MOSFET and a first terminal of a second capacitor; or

[0011] The first switch group includes a first diode and a second diode. The anodes of the first diode and the second diode are connected to the power supply voltage. The cathode of the first diode is connected to the first terminal of the first capacitor, and the cathode of the second diode is connected to the first terminal of the second capacitor.

[0012] In one or more embodiments of the present invention, the first switch control unit includes a third MOSFET and a fourth MOSFET. The source of the third MOSFET is connected to a first terminal of a first capacitor. The gates of the third MOSFET and the fourth MOSFET are used to receive a first control signal. The drain of the third MOSFET is connected to the drain of the fourth MOSFET and a second terminal of the third capacitor. The source of the fourth MOSFET is connected to a reference voltage.

[0013] The first switch control unit includes a third diode and a fourth MOSFET. The anode of the third diode is connected to the first terminal of the first capacitor. The gate of the fourth MOSFET is used to receive a first control signal. The cathode of the third diode is connected to the drain of the fourth MOSFET and the second terminal of the third capacitor. The source of the fourth MOSFET is connected to a reference voltage.

[0014] In one or more embodiments of the present invention, the second switch control unit includes a fifth MOSFET and a sixth MOSFET. The source of the fifth MOSFET is connected to the first terminal of a second capacitor. The gates of the fifth MOSFET and the sixth MOSFET are used to receive a second control signal. The drain of the fifth MOSFET is connected to the drain of the sixth MOSFET MN4 and the second terminal of a fourth capacitor. The source of the sixth MOSFET is connected to a reference voltage; or

[0015] The second switch control unit includes a fourth diode and a sixth MOSFET. The anode of the fourth diode is connected to the first terminal of the second capacitor. The gate of the sixth MOSFET is used to receive a second control signal. The cathode of the fourth diode is connected to the drain of the sixth MOSFET and the second terminal of the fourth capacitor. The drain of the sixth MOSFET is connected to a reference voltage.

[0016] In one or more embodiments of the present invention, the second switch group includes a seventh MOS transistor and an eighth MOS transistor. The source of the seventh MOS transistor and the source of the eighth MOS transistor are connected to the second terminal of the fifth capacitor. The drain of the seventh MOS transistor is connected to the gate of the eighth MOS transistor and the first terminal of the third capacitor. The drain of the eighth MOS transistor is connected to the gate of the seventh MOS transistor and the first terminal of the fourth capacitor; or

[0017] The second switch group includes a fifth diode and a sixth diode. The anodes of the fifth diode and the sixth diode are connected to the second terminal of the fifth capacitor. The cathode of the fifth diode is connected to the first terminal of the third capacitor. The cathode of the sixth diode is connected to the first terminal of the fourth capacitor.

[0018] In one or more embodiments of the present invention, the third switch group includes a ninth MOS transistor and a tenth MOS transistor. The drains of the ninth and tenth MOS transistors are connected to the first terminal of a fifth capacitor. The source of the ninth MOS transistor is connected to the gate of the tenth MOS transistor and the first terminal of a fourth capacitor. The source of the tenth MOS transistor is connected to the gate of the ninth MOS transistor and the first terminal of a third capacitor. Or

[0019] The third switch group includes a seventh diode and an eighth diode. The cathodes of the seventh diode and the eighth diode are connected to the first terminal of the fifth capacitor. The anode of the seventh diode is connected to the first terminal of the fourth capacitor, and the anode of the eighth diode is connected to the first terminal of the third capacitor.

[0020] In one or more embodiments of the present invention, the voltage multiplier circuit further includes a first inverter, the input terminal of the first inverter being connected to the second terminal of a first capacitor, and the output terminal of the first inverter being connected to the second terminal of a second capacitor.

[0021] In one or more embodiments of the present invention, the voltage multiplier circuit further includes a second inverter and / or a third inverter, wherein the input terminal of the second inverter is connected to the second terminal of the first capacitor, the output terminal of the second inverter is used to output a first control signal, the input terminal of the third inverter is connected to the second terminal of the second capacitor, and the output terminal of the third inverter is used to output a second control signal.

[0022] The present invention also discloses a voltage multiplication method for the voltage multiplication circuit, the voltage multiplication method comprising:

[0023] The first terminal of the first capacitor and the first terminal of the second capacitor are precharged by the power supply voltage and through the first switch group.

[0024] A pulse signal is provided to the second terminal of the first capacitor and the second terminal of the second capacitor. The pulse signal consists of alternating high-level signals and low-level signals, so that the first terminal of the first capacitor generates a voltage to charge the third capacitor and the first terminal of the second capacitor generates a voltage to charge the fourth capacitor.

[0025] The second terminal of the fifth capacitor is pre-charged by the input voltage, and the first terminals of the third capacitor and the first terminals of the fourth capacitor are pre-charged by the input voltage and through the second switch group.

[0026] The voltage generated at the signal output terminal is generated by the voltage generated at the first terminal of the first capacitor by the third capacitor and the fourth capacitor, and by the voltage generated at the first terminal of the second capacitor, and by the third switch group alternately charging the first terminal of the fifth capacitor.

[0027] In one or more embodiments of the present invention, when a high-level signal is provided to the second terminal of the first capacitor, the voltage generated at the first terminal of the first capacitor is transmitted to the second terminal of the third capacitor through the first switch control unit; when a low-level signal is provided to the second terminal of the first capacitor, the second terminal of the third capacitor is connected to a reference voltage through the first switch control unit.

[0028] When a high-level signal is provided to the second terminal of the second capacitor, the voltage generated at the first terminal of the second capacitor is transmitted to the second terminal of the fourth capacitor through the second switch control unit; when a low-level signal is provided to the second terminal of the second capacitor, the second terminal of the fourth capacitor is connected to the reference voltage through the second switch control unit.

[0029] In one or more embodiments of the present invention, when the voltage generated by the first terminal of the first capacitor is provided to the second terminal of the third capacitor, the voltage of the first terminal of the third capacitor is transmitted to the first terminal of the fifth capacitor through the third switch group; when the voltage generated by the first terminal of the second capacitor is provided to the second terminal of the fourth capacitor, the voltage generated by the first terminal of the fourth capacitor is transmitted to the first terminal of the fifth capacitor through the third switch group.

[0030] Compared with the prior art, the voltage multiplication circuit and voltage multiplication method according to the embodiments of the present invention precharge the first terminal of the first capacitor and the first terminal of the second capacitor according to the power supply voltage; then provide a pulse signal to the second terminal of the first capacitor and the second terminal of the second capacitor, so that the first terminal of the first capacitor generates a voltage to charge the third capacitor and the first terminal of the second capacitor generates a voltage to charge the fourth capacitor; precharge the second terminal of the fifth capacitor through the input voltage, and precharge the first terminal of the third capacitor and the first terminal of the fourth capacitor through the input voltage, so that the third capacitor and the fourth capacitor alternately charge the first terminal of the fifth capacitor based on the voltage generated by the first terminal of the first capacitor and the voltage generated by the first terminal of the second capacitor, so as to generate an output voltage that varies with the input voltage at the signal output terminal. The voltage multiplication circuit of the present invention can generate a sufficiently high high-side power supply voltage even when the power supply voltage is low, so as to meet the normal high-side power supply voltage requirements. Attached Figure Description

[0031] Figure 1 This is a circuit diagram of a voltage multiplier circuit according to Embodiment 1 of the present invention.

[0032] Figure 2 This is a first flowchart of the voltage multiplication method according to Embodiment 1 of the present invention.

[0033] Figure 3 This is a second flowchart of the voltage multiplication method according to Embodiment 1 of the present invention.

[0034] Figure 4 This is a circuit diagram of the voltage multiplier circuit according to Embodiment 2 of the present invention.

[0035] Figure 5 This is a circuit diagram of the voltage multiplier circuit according to Embodiment 3 of the present invention.

[0036] Figure 6 This is a circuit diagram of the voltage multiplier circuit according to Embodiment 4 of the present invention.

[0037] Figure 7 This is a circuit diagram of the voltage multiplier circuit according to Embodiment 5 of the present invention. Detailed Implementation

[0038] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0039] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0040] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in this invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0041] The N-type MOSFET described in this application has two symmetrical N-terminals as its source and drain, and a P-terminal in the middle as its gate. Therefore, the source and drain of the N-type MOSFET can be interchanged. The P-type MOSFET has two symmetrical P-terminals as its source and drain, and an N-terminal in the middle as its gate. Therefore, the source and drain of the P-type MOSFET can also be interchanged.

[0042] Example 1

[0043] like Figure 1 As shown, a voltage multiplier circuit includes: a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first inverter INV1, a second inverter INV2, a third inverter INV3, a first switch group 10, a first switch control unit 20, a second switch control unit 30, a second switch group 40, and a third switch group 50.

[0044] In this embodiment, the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are connected to the power supply voltage VDD through the first switch group 10. The input terminal of the first inverter INV1 is connected to the second terminal of the first capacitor C1, and the output terminal of the first inverter INV1 is connected to the second terminal of the second capacitor C2. In this embodiment, the pulse signal consists of alternating high-level and low-level signals. The pulse signal is first sent to the second terminal of the first capacitor C1, then inverted by the first inverter INV1 before being sent to the second terminal of the second capacitor C2. This ensures that the second terminals of the first capacitor C1 and the second terminals of the second capacitor C2 receive inverted pulse signals; that is, when the second terminal of the first capacitor C1 is at a high level, the second terminal of the second capacitor C2 is at a low level, and vice versa. The inversion of the pulse signal can be achieved by the first inverter INV1, or by an external signal generator generating two inverted pulse signals and sending them to the second terminals of the first capacitor C1 and the second terminal of the second capacitor C2 respectively.

[0045] In this embodiment, the low-level signal of the pulse signal is 0, and the high-level signal is VDD. The value of the high-level signal is also the voltage value of the power supply voltage VDD. It should be noted that the voltage value of the power supply voltage VDD can be changed as needed. In other embodiments, the low-level signal may not be 0 and can be changed as needed.

[0046] Specifically, the first switch group 10 includes a first MOSFET MN1 and a second MOSFET MN2. The source of the first MOSFET MN1 and the source of the second MOSFET MN2 are connected to the power supply voltage VDD. The drain of the first MOSFET MN1 is connected to the gate of the second MOSFET MN2 and the first terminal of the first capacitor C1. The drain of the second MOSFET MN2 is connected to the gate of the first MOSFET MN1 and the first terminal of the second capacitor C2.

[0047] like Figure 1 As shown, the first switch control unit 20 is connected to the first terminal of the first capacitor C1 and the second terminal of the third capacitor C3. The first switch control unit 20 controls the switching between the first terminal of the first capacitor C1 and the second terminal of the third capacitor C3 based on the first control signal.

[0048] Specifically, the first switch control unit 20 includes a third MOSFET MP1 and a fourth MOSFET MN3. The source of the third MOSFET MP1 is connected to the first terminal of the first capacitor C1, the input terminal of the second inverter INV2 is connected to the second terminal of the first capacitor C1, the gate of the third MOSFET MP1 is connected to the gate of the fourth MOSFET MN3 and simultaneously to the output terminal of the second inverter INV2, the drain of the third MOSFET MP1 is connected to the drain of the fourth MOSFET MN3 and the second terminal of the third capacitor C3, and the source of the fourth MOSFET MN3 is connected to a reference voltage. In this embodiment, the reference voltage is ground; in other embodiments, the reference voltage can be set to other values ​​as needed.

[0049] In this embodiment, the pulse signal input to the second terminal of the first capacitor C1 is simultaneously inverted by the second inverter INV2 and output as a first control signal to control the turning on and off of the third MOSFET MP1 and the fourth MOSFET MN3. At this time, it is equivalent to the first control signal being in phase with the pulse signal input to the second terminal of the second capacitor C2. In other embodiments, an external signal generator can be used to generate a first control signal that is inverted from the pulse signal input to the second terminal of the first capacitor C1, which can then be directly input to the gates of the third MOSFET MP1 and the fourth MOSFET MN3. Alternatively, the gates of the third MOSFET MP1 and the fourth MOSFET MN3 can be connected to the output terminal of the first inverter INV1.

[0050] like Figure 1As shown, the second switch control unit 30 is connected to the first terminal of the second capacitor C2 and the second terminal of the fourth capacitor C4. The second switch control unit 30 controls the switching between the first terminal of the second capacitor C2 and the second terminal of the fourth capacitor C4 based on the second control signal.

[0051] Specifically, the second switch control unit 30 includes a fifth MOSFET MP2 and a sixth MOSFET MN4. The source of the fifth MOSFET MP2 is connected to the first terminal of the second capacitor C2, the gate of the fifth MOSFET MP2 is connected to the gate of the sixth MOSFET MN4 and simultaneously connected to the output terminal of the third inverter INV3, the input terminal of the third inverter INV3 is connected to the second terminal of the second capacitor C2 and the output terminal of the first inverter INV1, the drain of the fifth MOSFET MP2 is connected to the drain of the sixth MOSFET MN4 and the second terminal of the fourth capacitor C4, and the source of the sixth MOSFET MN4 is connected to ground.

[0052] In this embodiment, the pulse signal input to the second terminal of the second capacitor C2 is simultaneously inverted by the third inverter INV3 and output as a second control signal to control the turning on and off of the fifth MOSFET MP2 and the sixth MOSFET MN4. At this time, this second control signal is equivalent to being in phase with the pulse signal input to the second terminal of the first capacitor C1. In other embodiments, a second control signal inverted from the pulse signal input to the second terminal of the second capacitor C2 can be generated by an external signal generator and directly input to the gates of the fifth MOSFET MP2 and the sixth MOSFET MN4. Alternatively, the gates of the fifth MOSFET MP2 and the sixth MOSFET MN4 can be connected to the second terminal of the first capacitor C1.

[0053] like Figure 1 As shown, the first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4 are connected to the second terminal of the fifth capacitor C5 and the signal input terminal Vin through the second switch group 40. The first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4 are also connected to the first terminal of the fifth capacitor C5 and the signal output terminal Vout through the third switch group 50.

[0054] Specifically, the second switch group 40 includes a seventh MOSFET MN5 and an eighth MOSFET MN6. The source of the seventh MOSFET MN5 and the source of the eighth MOSFET MN6 are connected to the second terminal of the fifth capacitor C5 and the signal input terminal Vin. The drain of the seventh MOSFET MN5 is connected to the gate of the eighth MOSFET MN6 and the first terminal of the third capacitor C3. The drain of the eighth MOSFET MN6 is connected to the gate of the seventh MOSFET MN5 and the first terminal of the fourth capacitor C4.

[0055] Specifically, the third switch group 50 includes a ninth MOSFET MP3 and a tenth MOSFET MP4. The drains of the ninth MOSFET MP3 and the tenth MOSFET MP4 are connected to the first terminal of the fifth capacitor C5 and the signal output terminal Vout. The source of the ninth MOSFET MP3 is connected to the gate of the tenth MOSFET MP4 and the first terminal of the fourth capacitor C4. The source of the tenth MOSFET MP4 is connected to the gate of the ninth MOSFET MP3 and the first terminal of the third capacitor C3.

[0056] This embodiment also discloses a voltage multiplication method for the aforementioned voltage multiplication circuit. The voltage multiplication method includes:

[0057] In the initial state, the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are pre-charged through the power supply voltage VDD and the first switch group 10, so that the voltage of the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 is pre-charged to VDD-0.7V, where 0.7V is the voltage drop generated by the parasitic diode on the MOS transistor.

[0058] A pulse signal is periodically provided to the second terminals of the first capacitor C1 and the second terminals of the second capacitor C2. The pulse signal consists of alternating high-level and low-level signals, so that the first terminal of the first capacitor C1 generates a voltage to charge the third capacitor C3, and the first terminal of the second capacitor C2 generates a voltage to charge the fourth capacitor C4. In this embodiment, the pulse signals provided to the second terminals of the first capacitor C1 and the second terminals of the second capacitor C2 are inverted.

[0059] When a high-level signal is provided to the second terminal of the first capacitor C1, the voltage generated at the first terminal of the first capacitor C1 is transmitted to the second terminal of the third capacitor C3 through the first switch control unit 20; when a low-level signal is provided to the second terminal of the first capacitor C1, the second terminal of the third capacitor C3 is connected to the reference voltage through the first switch control unit 20.

[0060] When a high-level signal is provided to the second terminal of the second capacitor C2, the voltage generated at the first terminal of the second capacitor C2 is transmitted to the second terminal of the fourth capacitor C4 through the second switch control unit 30; when a low-level signal is provided to the second terminal of the second capacitor C2, the second terminal of the fourth capacitor C4 is connected to the reference voltage through the second switch control unit 30.

[0061] Specifically, such as Figure 2 As shown, a high-level signal (i.e., the power supply voltage VDD) is provided to the second terminal of the first capacitor C1, and a low-level signal (i.e., 0) is provided to the second terminal of the second capacitor C2. The voltage at the first terminal of the first capacitor C1 is 2VDD-0.7V.

[0062] The voltage 2VDD-0.7V at the first terminal of the first capacitor C1 controls the conduction of the second MOSFET MN2, causing the voltage at the first terminal of the second capacitor C2 to become VDD. At this time, since the second MOSFET MN2 is fully turned on, the 0.7V voltage drop also disappears.

[0063] The fourth MOSFET MN3 is turned off and the third MOSFET MP1 is turned on by a low-level signal. The voltage 2VDD-0.7V at the first terminal of the first capacitor C1 is sent to the second terminal of the third capacitor C3 through the turned-on third MOSFET MP1. That is, the voltage at the second terminal of the third capacitor C3 is 2VDD-0.7V. In this embodiment, the low-level signal is obtained by the second inverter INV2 flipping the high-level signal input to the second terminal of the first capacitor C1.

[0064] The high-level signal controls the sixth MOS transistor MN4 to conduct, so that the second terminal of the fourth capacitor C4 is connected to the reference voltage, that is, the voltage of the second terminal of the fourth capacitor C4 is 0; in this embodiment, the high-level signal is obtained by the third inverter INV3 flipping the low-level signal output by the first inverter INV1.

[0065] When a low-level signal is provided to the second terminal of the first capacitor C1 and a high-level signal is provided to the second terminal of the second capacitor C2, the voltage at the first terminal of the second capacitor C2 is 2VDD.

[0066] The voltage 2VDD at the first terminal of the second capacitor C2 controls the first MOSFET MN1 to turn on, so that the voltage at the first terminal of the first capacitor C1 becomes VDD.

[0067] The sixth MOSFET MN4 is turned off and the fifth MOSFET MP2 is turned on by a low-level signal. The voltage 2VDD at the first terminal of the second capacitor C2 is transmitted to the second terminal of the fourth capacitor C4 through the turned-on fifth MOSFET MP2. That is, the voltage at the second terminal of the fourth capacitor C4 is 2VDD. In this embodiment, the low-level signal is obtained by the third inverter INV3 flipping the high-level signal output by the first inverter INV1.

[0068] The high-level signal controls the fourth MOS transistor MN3 to conduct, so that the second terminal of the third capacitor C3 is connected to the reference voltage, that is, the voltage of the second terminal of the third capacitor C3 is 0; in this embodiment, the high-level signal is obtained by the second inverter INV2 flipping the low-level signal input to the second terminal of the first capacitor C1.

[0069] As can be seen from the above, by alternating high and low level signals, the second terminals of the third capacitor C3 and the fourth capacitor C4 both generate voltage signals that vary in the range of 0 to 2VDD, and the two voltage signals have a phase difference.

[0070] In this embodiment, in the initial state, the second terminal of the fifth capacitor C5 is pre-charged by the input voltage Vin, so that the voltage of the second terminal of the fifth capacitor C5 is the input voltage Vin. The first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4 are pre-charged by the input voltage Vin and through the second switch group 40, so that the voltage of the first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4 is Vin-0.7V.

[0071] When the voltage generated by the first terminal of the first capacitor C1 is supplied to the second terminal of the third capacitor C3, the voltage at the first terminal of the third capacitor C3 is transmitted to the first terminal of the fifth capacitor C5 through the third switch group 50; when the voltage generated by the first terminal of the second capacitor C2 is supplied to the second terminal of the fourth capacitor C4, the voltage generated at the first terminal of the fourth capacitor C4 is transmitted to the first terminal of the fifth capacitor C5 through the third switch group 50.

[0072] The first terminal of the fifth capacitor C5 is alternately charged by the third capacitor C3 and the fourth capacitor C4 based on the voltage generated at the first terminal of the first capacitor C1 and the voltage generated at the first terminal of the second capacitor C2, and by the third switch group 50, so as to generate an output voltage Vout at the signal output terminal that varies with the input voltage Vin. In this embodiment, the input voltage Vin can be selected as any value as needed.

[0073] Specifically, such as Figure 3 As shown, when the voltage at the second terminal of the third capacitor C3 is 2VDD, the voltage at the first terminal of the third capacitor C3 is 2VDD+Vin-0.7V, where Vin is the input voltage value of the signal input terminal. At this time, the voltage at the first terminal of the third capacitor C3, 2VDD+Vin-0.7V, controls the eighth MOS transistor MN6 to turn on, so that the voltage at the first terminal of the fourth capacitor C4 is the input voltage Vin.

[0074] When the voltage at the second terminal of the fourth capacitor C4 is 2VDD, the voltage at the first terminal of the fourth capacitor C4 is 2VDD+Vin. The voltage at the first terminal of the fourth capacitor C4, 2VDD+Vin, controls the seventh MOSFET MN5 to turn on, so that the voltage at the first terminal of the third capacitor C3 is the input voltage Vin.

[0075] The voltage Vin at the first terminal of the third capacitor C3 controls the conduction of the ninth MOSFET MP3, and the conducting ninth MOSFET MP3 transmits the voltage 2VDD+Vin at the first terminal of the fourth capacitor C4 to the signal output terminal.

[0076] At this time, the voltage at the first terminal of the third capacitor C3 is the input voltage Vin. In the next cycle, the voltage at the second terminal of the third capacitor C3 is 2VDD, and the voltage at the first terminal of the third capacitor C3 becomes the input voltage 2VDD+Vin. The voltage 2VDD+Vin at the first terminal of the third capacitor C3 controls the eighth MOSFET MN6 to turn on, so that the voltage at the first terminal of the fourth capacitor C4 is the input voltage Vin.

[0077] The voltage Vin at the first terminal of the fourth capacitor C4 controls the conduction of the tenth MOSFET MP4, and the conducting tenth MOSFET MP4 transmits the voltage 2VDD+Vin at the first terminal of the third capacitor C3 to the signal output terminal.

[0078] As can be seen from the above, through cyclic operation, the output voltage Vout at the signal output terminal is Vout = 2VDD + Vin.

[0079] Example 2

[0080] like Figure 4 As shown, the structure of a voltage multiplier circuit differs from that in Embodiment 1 in that the first MOSFET MN1 and the second MOSFET MN2 are replaced with the first diode D1 and the second diode D2, the third MOSFET MP1 is replaced with the third diode D3, the fifth MOSFET MP2 is replaced with the fourth diode D4, the seventh MOSFET MN5 and the eighth MOSFET MN6 are replaced with the fifth diode D5 and the sixth diode D6, and the ninth MOSFET MP3 and the tenth MOSFET MP4 are replaced with the seventh diode D7 and the eighth diode D8.

[0081] Specifically, the anode of the first diode D1 and the anode of the second diode D2 are connected to the power supply voltage VDD, the cathode of the first diode D1 is connected to the first terminal of the first capacitor C1, and the cathode of the second diode D2 is connected to the first terminal of the second capacitor C2.

[0082] The anode of the third diode D3 is connected to the first terminal of the first capacitor C1. The gate of the fourth MOSFET MN3 is used to receive the first control signal. The cathode of the third diode D3 is connected to the drain of the fourth MOSFET MN3 and the second terminal of the third capacitor C3. The source of the fourth MOSFET MN3 is connected to the reference voltage. In this embodiment, the reference voltage is ground voltage. In other embodiments, the reference voltage can be set to other values ​​as needed.

[0083] The anode of the fourth diode D4 is connected to the first terminal of the second capacitor C2. The gate of the sixth MOSFET MN4 is used to receive the second control signal. The cathode of the fourth diode D4 is connected to the drain of the sixth MOSFET MN4 and the second terminal of the fourth capacitor C4. The drain of the sixth MOSFET MN4 is connected to the reference voltage.

[0084] The anodes of the fifth diode D5 and the sixth diode D6 are connected to the second terminal of the fifth capacitor C5. The cathode of the fifth diode D5 is connected to the first terminal of the third capacitor C3. The cathode of the sixth diode D6 is connected to the first terminal of the fourth capacitor C4.

[0085] The cathodes of the seventh diode D7 and the eighth diode D8 are connected to the first terminal of the fifth capacitor C5. The anode of the seventh diode D7 is connected to the first terminal of the fourth capacitor C4. The anode of the eighth diode D8 is connected to the first terminal of the third capacitor C3.

[0086] This embodiment also discloses a voltage multiplication method for the aforementioned voltage multiplication circuit. The voltage multiplication method includes:

[0087] In the initial state, the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are precharged through the power supply voltage VDD and the first switch group 10, so that the voltage of the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 is precharged to VDD-0.7V.

[0088] A pulse signal is periodically provided to the second terminals of the first capacitor C1 and the second terminals of the second capacitor C2. The pulse signal consists of alternating high-level and low-level signals, so that the first terminal of the first capacitor C1 generates a voltage to charge the third capacitor C3, and the first terminal of the second capacitor C2 generates a voltage to charge the fourth capacitor C4. In this embodiment, the pulse signals provided to the second terminals of the first capacitor C1 and the second terminals of the second capacitor C2 are inverted.

[0089] When a high-level signal is provided to the second terminal of the first capacitor C1, the voltage generated at the first terminal of the first capacitor C1 is transmitted to the second terminal of the third capacitor C3 through the first switch control unit 20; when a low-level signal is provided to the second terminal of the first capacitor C1, the second terminal of the third capacitor C3 is connected to the reference voltage through the first switch control unit 20.

[0090] When a high-level signal is provided to the second terminal of the second capacitor C2, the voltage generated at the first terminal of the second capacitor C2 is transmitted to the second terminal of the fourth capacitor C4 through the second switch control unit 30; when a low-level signal is provided to the second terminal of the second capacitor C2, the second terminal of the fourth capacitor C4 is connected to the reference voltage through the second switch control unit 30.

[0091] Specifically, a high-level signal (i.e., the power supply voltage VDD) is provided to the second terminal of the first capacitor C1, and a low-level signal (i.e., 0) is provided to the second terminal of the second capacitor C2. The voltage at the first terminal of the first capacitor C1 is 2VDD-0.7V, where 0.7V is the forward voltage drop of the first diode D1.

[0092] The fourth MOSFET MN3 is turned off by a low-level signal. The voltage 2VDD-0.7V at the first terminal of the first capacitor C1 is transmitted to the second terminal of the third capacitor C3 through the third diode D3, so that the voltage at the second terminal of the third capacitor C3 is 2VDD-1.4V. The added 0.7V here is the forward voltage drop of the third diode D3. In this embodiment, the low-level signal is obtained by the second inverter INV2 flipping the high-level signal input to the second terminal of the first capacitor C1.

[0093] The high-level signal controls the sixth MOS transistor MN4 to conduct, so that the second terminal of the fourth capacitor C4 is connected to the reference voltage, that is, the voltage of the second terminal of the fourth capacitor C4 is 0; in this embodiment, the high-level signal is obtained by the third inverter INV3 flipping the low-level signal output by the first inverter INV1.

[0094] When a low-level signal is provided to the second terminal of the first capacitor C1 and a high-level signal is provided to the second terminal of the second capacitor C2, the voltage at the first terminal of the second capacitor C2 is 2VDD-0.7V, where 0.7V is the forward voltage drop of the second diode D2.

[0095] The sixth MOSFET MN4 is turned off by a low-level signal. The voltage 2VDD-0.7V at the first terminal of the second capacitor C2 is transmitted to the second terminal of the fourth capacitor C4 through the fourth diode D4, so that the voltage at the second terminal of the fourth capacitor C4 is 2VDD-1.4V. The added 0.7V here is the forward voltage drop of the fourth diode D4. In this embodiment, the low-level signal is obtained by the third inverter INV3 flipping the high-level signal output by the first inverter INV1.

[0096] The high-level signal controls the fourth MOS transistor MN3 to conduct, so that the second terminal of the third capacitor C3 is connected to the reference voltage, that is, the voltage of the second terminal of the third capacitor C3 is 0; in this embodiment, the high-level signal is obtained by the second inverter INV2 flipping the low-level signal input to the second terminal of the first capacitor C1.

[0097] As can be seen from the above, by alternating high and low level signals, the second terminals of the third capacitor C3 and the fourth capacitor C4 both generate voltage signals that vary in the range of 0 to 2VDD-1.4V, and the two voltage signals have a phase difference.

[0098] In this embodiment, in the initial state, the second terminal of the fifth capacitor C5 is pre-charged by the input voltage Vin, so that the voltage of the second terminal of the fifth capacitor C5 is the input voltage Vin. The first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4 are pre-charged by the input voltage Vin and through the second switch group 40, so that the voltage of the first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4 is Vin-0.7V.

[0099] When the voltage generated by the first terminal of the first capacitor C1 is supplied to the second terminal of the third capacitor C3, the voltage at the first terminal of the third capacitor C3 is transmitted to the first terminal of the fifth capacitor C5 through the third switch group 50; when the voltage generated by the first terminal of the second capacitor C2 is supplied to the second terminal of the fourth capacitor C4, the voltage generated at the first terminal of the fourth capacitor C4 is transmitted to the first terminal of the fifth capacitor C5 through the third switch group 50.

[0100] The first terminal of the fifth capacitor C5 is alternately charged by the third capacitor C3 and the fourth capacitor C4 based on the voltage generated at the first terminal of the first capacitor C1 and the voltage generated at the first terminal of the second capacitor C2, and by the third switch group 50, so as to generate an output voltage Vout at the signal output terminal that varies with the input voltage Vin. In this embodiment, the input voltage Vin can be selected as any value as needed.

[0101] Specifically, when the voltage at the second terminal of the third capacitor C3 is 2VDD-1.4V, the voltage at the first terminal of the third capacitor C3 is 2VDD+Vin-2.1V. The increase of 0.7V is the forward voltage drop of the fifth diode D5, and Vin is the input voltage at the signal input terminal.

[0102] The voltage 2VDD+Vin-2.1V at the first terminal of the third capacitor C3 is transmitted to the signal output terminal through the eighth diode D8. The voltage output through the signal output terminal is 2VDD+Vin-2.8V, and the increase of 0.7V is the forward voltage drop of the eighth diode D8.

[0103] When the voltage at the second terminal of the fourth capacitor C4 is 2VDD-1.4V, the voltage at the first terminal of the fourth capacitor C4 is 2VDD+Vin-2.1V. The increase of 0.7V is the forward voltage drop of the sixth diode D6.

[0104] The voltage 2VDD+Vin-2.1V at the first terminal of the fourth capacitor C4 is transmitted to the signal output terminal through the seventh diode D7. The voltage output through the signal output terminal is 2VDD+Vin-2.8V, and the increase of 0.7V is the forward voltage drop of the seventh diode D7.

[0105] As can be seen from the above, through cyclic operation, the output voltage Vout at the signal output terminal is Vout = 2VDD + Vin - 2.8V.

[0106] Example 3

[0107] like Figure 5 As shown, the structure of the voltage multiplier circuit in this embodiment differs from that in Embodiment 1 in that the first MOSFET MN1 and the second MOSFET MN2 are replaced with the first diode D1 and the second diode D2; the third MOSFET MP1 is replaced with the third diode D3; and the fifth MOSFET MP2 is replaced with the fourth diode D4.

[0108] Specifically, the anode of the first diode D1 and the anode of the second diode D2 are connected to the power supply voltage VDD, the cathode of the first diode D1 is connected to the first terminal of the first capacitor C1, and the cathode of the second diode D2 is connected to the first terminal of the second capacitor C2.

[0109] The anode of the third diode D3 is connected to the first terminal of the first capacitor C1. The gate of the fourth MOSFET MN3 is used to receive the first control signal. The cathode of the third diode D3 is connected to the drain of the fourth MOSFET MN3 and the second terminal of the third capacitor C3. The source of the fourth MOSFET MN3 is connected to the reference voltage. In this embodiment, the reference voltage is ground voltage. In other embodiments, the reference voltage can be set to other values ​​as needed.

[0110] The anode of the fourth diode D4 is connected to the first terminal of the second capacitor C2. The gate of the sixth MOSFET MN4 is used to receive the second control signal. The cathode of the fourth diode D4 is connected to the drain of the sixth MOSFET MN4 and the second terminal of the fourth capacitor C4. The drain of the sixth MOSFET MN4 is connected to the reference voltage.

[0111] This embodiment also discloses a voltage multiplication method for the aforementioned voltage multiplication circuit. The voltage multiplication method includes:

[0112] In the initial state, the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are precharged through the power supply voltage VDD and the first switch group 10, so that the voltage of the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 is precharged to VDD-0.7V.

[0113] A pulse signal is periodically provided to the second terminals of the first capacitor C1 and the second terminals of the second capacitor C2. The pulse signal consists of alternating high-level and low-level signals, so that the first terminal of the first capacitor C1 generates a voltage to charge the third capacitor C3, and the first terminal of the second capacitor C2 generates a voltage to charge the fourth capacitor C4. In this embodiment, the pulse signals provided to the second terminals of the first capacitor C1 and the second terminals of the second capacitor C2 are inverted.

[0114] When a high-level signal is provided to the second terminal of the first capacitor C1, the voltage generated at the first terminal of the first capacitor C1 is transmitted to the second terminal of the third capacitor C3 through the first switch control unit 20; when a low-level signal is provided to the second terminal of the first capacitor C1, the second terminal of the third capacitor C3 is connected to the reference voltage through the first switch control unit 20.

[0115] When a high-level signal is provided to the second terminal of the second capacitor C2, the voltage generated at the first terminal of the second capacitor C2 is transmitted to the second terminal of the fourth capacitor C4 through the second switch control unit 30; when a low-level signal is provided to the second terminal of the second capacitor C2, the second terminal of the fourth capacitor C4 is connected to the reference voltage through the second switch control unit 30.

[0116] Specifically, a high-level signal (i.e., the power supply voltage VDD) is provided to the second terminal of the first capacitor C1, and a low-level signal (i.e., 0) is provided to the second terminal of the second capacitor C2. The voltage at the first terminal of the first capacitor C1 is 2VDD-0.7V, where 0.7V is the forward voltage drop of the first diode D1.

[0117] The fourth MOSFET MN3 is turned off by a low-level signal. The voltage 2VDD-0.7V at the first terminal of the first capacitor C1 is transmitted to the second terminal of the third capacitor C3 through the third diode D3, so that the voltage at the second terminal of the third capacitor C3 is 2VDD-1.4V. The added 0.7V here is the forward voltage drop of the third diode D3. In this embodiment, the low-level signal is obtained by the second inverter INV2 flipping the high-level signal input to the second terminal of the first capacitor C1.

[0118] The high-level signal controls the sixth MOS transistor MN4 to conduct, so that the second terminal of the fourth capacitor C4 is connected to the reference voltage, that is, the voltage of the second terminal of the fourth capacitor C4 is 0; in this embodiment, the high-level signal is obtained by the third inverter INV3 flipping the low-level signal output by the first inverter INV1.

[0119] When a low-level signal is provided to the second terminal of the first capacitor C1 and a high-level signal is provided to the second terminal of the second capacitor C2, the voltage at the first terminal of the second capacitor C2 is 2VDD-0.7V.

[0120] The sixth MOS transistor MN4 is turned off by controlling the low-level signal, and the voltage 2VDD-0.7V at the first terminal of the second capacitor C2 is sent to the second terminal of the fourth capacitor C4 through the fourth diode D4, so that the voltage at the second terminal of the fourth capacitor C4 is 2VDD-1.4V; in this embodiment, the low-level signal is obtained by the third inverter INV3 flipping the high-level signal output by the first inverter INV1.

[0121] The high-level signal controls the fourth MOS transistor MN3 to conduct, so that the second terminal of the third capacitor C3 is connected to the reference voltage, that is, the voltage of the second terminal of the third capacitor C3 is 0; in this embodiment, the high-level signal is obtained by the second inverter INV2 flipping the low-level signal input to the second terminal of the first capacitor C1.

[0122] As can be seen from the above, by alternating high and low level signals, the second terminals of the third capacitor C3 and the fourth capacitor C4 both generate voltage signals that vary in the range of 0 to 2VDD-1.4V, and the two voltage signals have a phase difference.

[0123] In this embodiment, in the initial state, the second terminal of the fifth capacitor C5 is pre-charged by the input voltage Vin, so that the voltage of the second terminal of the fifth capacitor C5 is the input voltage Vin. The first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4 are pre-charged by the input voltage Vin and through the second switch group 40, so that the voltage of the first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4 is Vin-0.7V.

[0124] When the voltage generated by the first terminal of the first capacitor C1 is supplied to the second terminal of the third capacitor C3, the voltage at the first terminal of the third capacitor C3 is transmitted to the first terminal of the fifth capacitor C5 through the third switch group 50; when the voltage generated by the first terminal of the second capacitor C2 is supplied to the second terminal of the fourth capacitor C4, the voltage generated at the first terminal of the fourth capacitor C4 is transmitted to the first terminal of the fifth capacitor C5 through the third switch group 50.

[0125] The first terminal of the fifth capacitor C5 is alternately charged by the third capacitor C3 and the fourth capacitor C4 based on the voltage generated at the first terminal of the first capacitor C1 and the voltage generated at the first terminal of the second capacitor C2, and by the third switch group 50, so as to generate an output voltage Vout at the signal output terminal that varies with the input voltage Vin. In this embodiment, the input voltage Vin can be selected as any value as needed.

[0126] Specifically, when the voltage at the second terminal of the third capacitor C3 is 2VDD-1.4V, the voltage at the first terminal of the third capacitor C3 is 2VDD+Vin-2.1V, where Vin is the input voltage value of the signal input terminal. At this time, the voltage 2VDD+Vin-2.1V at the first terminal of the third capacitor C3 controls the eighth MOSFET MN6 to turn on, so that the voltage at the first terminal of the fourth capacitor C4 is the input voltage Vin.

[0127] When the voltage at the second terminal of the fourth capacitor C4 is 2VDD-1.4V, the voltage at the first terminal of the fourth capacitor C4 is 2VDD+Vin-1.4V.

[0128] The voltage 2VDD+Vin-1.4V at the first terminal of the fourth capacitor C4 controls the seventh MOSFET MN5 to conduct, so that the voltage at the first terminal of the third capacitor C3 is the input voltage Vin.

[0129] The voltage Vin at the first terminal of the third capacitor C3 controls the conduction of the ninth MOSFET MP3, and the conducting ninth MOSFET MP3 transmits the voltage 2VDD+Vin-1.4V at the first terminal of the fourth capacitor C4 to the signal output terminal.

[0130] At this time, the voltage at the first terminal of the third capacitor C3 is the input voltage Vin. In the next cycle, the voltage at the second terminal of the third capacitor C3 is 2VDD-1.4V, and the voltage at the first terminal of the third capacitor C3 becomes the input voltage 2VDD+Vin-1.4V.

[0131] The voltage 2VDD+Vin-1.4V at the first terminal of the third capacitor C3 controls the conduction of the eighth MOSFET MN6, making the voltage at the first terminal of the fourth capacitor C4 equal to the input voltage Vin.

[0132] The voltage Vin at the first terminal of the fourth capacitor C4 controls the conduction of the tenth MOSFET MP4, and the conducting tenth MOSFET MP4 transmits the voltage 2VDD+Vin at the first terminal of the third capacitor C3 to the signal output terminal.

[0133] As can be seen from the above, through cyclic operation, the output voltage Vout at the signal output terminal is Vout = 2VDD + Vin - 1.4V.

[0134] Example 4

[0135] like Figure 6 As shown, the structure of the voltage multiplier circuit in this embodiment differs from that in Embodiment 1 in that the first MOS transistor MN1 and the second MOS transistor MN2 are replaced with the first diode D1 and the second diode D2.

[0136] Specifically, the anode of the first diode D1 and the anode of the second diode D2 are connected to the power supply voltage VDD, the cathode of the first diode D1 is connected to the first terminal of the first capacitor C1, and the cathode of the second diode D2 is connected to the first terminal of the second capacitor C2.

[0137] The source of the third MOSFET MP1 is connected to the first terminal of the first capacitor C1. The input terminal of the second inverter INV2 is connected to the second terminal of the first capacitor C1. The gate of the third MOSFET MP1 is connected to the gate of the fourth MOSFET MN3 and simultaneously to the output terminal of the second inverter INV2. The drain of the third MOSFET MP1 is connected to the drain of the fourth MOSFET MN3 and the second terminal of the third capacitor C3. The source of the fourth MOSFET MN3 is connected to the reference voltage. In this embodiment, the reference voltage is ground. In other embodiments, the reference voltage can be set to other values ​​as needed.

[0138] The source of the fifth MOSFET MP2 is connected to the first terminal of the second capacitor C2. The gate of the fifth MOSFET MP2 is connected to the gate of the sixth MOSFET MN4 and simultaneously connected to the output terminal of the third inverter INV3. The input terminal of the third inverter INV3 is connected to the second terminal of the second capacitor C2 and the output terminal of the first inverter INV1. The drain of the fifth MOSFET MP2 is connected to the drain of the sixth MOSFET MN4 and the second terminal of the fourth capacitor C4. The source of the sixth MOSFET MN4 is connected to the reference voltage.

[0139] The source of the seventh MOSFET MN5 and the source of the eighth MOSFET MN6 are connected to the second terminal of the fifth capacitor C5 and the signal input terminal Vin. The drain of the seventh MOSFET MN5 is connected to the gate of the eighth MOSFET MN6 and the first terminal of the third capacitor C3. The drain of the eighth MOSFET MN6 is connected to the gate of the seventh MOSFET MN5 and the first terminal of the fourth capacitor C4.

[0140] The drain of the ninth MOSFET MP3 and the drain of the tenth MOSFET MP4 are connected to the first terminal of the fifth capacitor C5 and the signal output terminal Vout. The source of the ninth MOSFET MP3 is connected to the gate of the tenth MOSFET MP4 and the first terminal of the fourth capacitor C4. The source of the tenth MOSFET MP4 is connected to the gate of the ninth MOSFET MP3 and the first terminal of the third capacitor C3.

[0141] This embodiment also discloses a voltage multiplication method for the aforementioned voltage multiplication circuit. The voltage multiplication method includes:

[0142] In the initial state, the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are precharged through the power supply voltage VDD and the first switch group 10, so that the voltage of the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 is precharged to VDD-0.7V.

[0143] A pulse signal is periodically provided to the second terminals of the first capacitor C1 and the second terminals of the second capacitor C2. The pulse signal consists of alternating high-level and low-level signals, so that the first terminal of the first capacitor C1 generates a voltage to charge the third capacitor C3, and the first terminal of the second capacitor C2 generates a voltage to charge the fourth capacitor C4. In this embodiment, the pulse signals provided to the second terminals of the first capacitor C1 and the second terminals of the second capacitor C2 are inverted.

[0144] When a high-level signal is provided to the second terminal of the first capacitor C1, the voltage generated at the first terminal of the first capacitor C1 is transmitted to the second terminal of the third capacitor C3 through the first switch control unit 20; when a low-level signal is provided to the second terminal of the first capacitor C1, the second terminal of the third capacitor C3 is connected to the reference voltage through the first switch control unit 20.

[0145] When a high-level signal is provided to the second terminal of the second capacitor C2, the voltage generated at the first terminal of the second capacitor C2 is transmitted to the second terminal of the fourth capacitor C4 through the second switch control unit 30; when a low-level signal is provided to the second terminal of the second capacitor C2, the second terminal of the fourth capacitor C4 is connected to the reference voltage through the second switch control unit 30.

[0146] Specifically, a high-level signal (i.e., the power supply voltage VDD) is provided to the second terminal of the first capacitor C1, and a low-level signal (i.e., 0) is provided to the second terminal of the second capacitor C2. The voltage at the first terminal of the first capacitor C1 is 2VDD-0.7V, where 0.7V is the forward voltage drop of the first diode D1.

[0147] The fourth MOSFET MN3 is turned off and the third MOSFET MP1 is turned on by a low-level signal. The voltage 2VDD-0.7V at the first terminal of the first capacitor C1 is sent to the second terminal of the third capacitor C3 through the turned-on third MOSFET MP1. That is, the voltage at the second terminal of the third capacitor C3 is 2VDD-0.7V. In this embodiment, the low-level signal is obtained by the second inverter INV2 flipping the high-level signal input to the second terminal of the first capacitor C1.

[0148] The high-level signal controls the sixth MOS transistor MN4 to conduct, so that the second terminal of the fourth capacitor C4 is connected to the reference voltage, that is, the voltage of the second terminal of the fourth capacitor C4 is 0; in this embodiment, the high-level signal is obtained by the third inverter INV3 flipping the low-level signal output by the first inverter INV1.

[0149] When a low-level signal is provided to the second terminal of the first capacitor C1 and a high-level signal is provided to the second terminal of the second capacitor C2, the voltage at the first terminal of the second capacitor C2 is 2VDD-0.7V, where 0.7V is the forward voltage drop of the second diode D2.

[0150] The sixth MOSFET MN4 is turned off and the fifth MOSFET MP2 is turned on by a low-level signal. The voltage 2VDD-0.7V at the first terminal of the second capacitor C2 is sent to the second terminal of the fourth capacitor C4 through the turned-on fifth MOSFET MP2. That is, the voltage at the second terminal of the fourth capacitor C4 is 2VDD-0.7V. In this embodiment, the low-level signal is obtained by the third inverter INV3 flipping the high-level signal output by the first inverter INV1.

[0151] A high-level signal controls the fourth MOSFET MN3 to conduct, making the second terminal of the third capacitor C3 connected to the reference voltage, i.e., the voltage at the second terminal of the third capacitor C3 is 0; in this embodiment, the high-level signal...

[0152] The flat signal is obtained by flipping the low-level signal input to the second terminal of the first capacitor C1 by 5 using the second inverter INV2.

[0153] As can be seen from the above, by alternating high and low level signals, the second terminals of the third capacitor C3 and the fourth capacitor C4 both generate voltage signals that vary in the range of 0 to 2VDD-0.7V, and the two voltage signals have a phase difference.

[0154] In this embodiment, in the initial state, the second terminal of the fifth capacitor C5 is pre-charged by the input voltage Vin, so that the voltage at the second terminal of the fifth capacitor C5 is equal to the input voltage Vin.

[0155] The voltage Vin is used to precharge the first terminals of the third capacitor C3 and the fourth capacitor C4 through the second switch group 40, so that the voltage at which the first terminals of the third capacitor C3 and the first terminals of the fourth capacitor C4 are precharged is Vin-0.7V.

[0156] When the voltage generated by the first terminal of the first capacitor C1 is supplied to the second terminal of the third capacitor C3, the voltage at the first terminal of the third capacitor C3 is transmitted to the first terminal of the fifth capacitor C5 through the third switch group 50.

[0157] When the voltage generated by the first terminal of the second capacitor C2 is supplied to the second terminal of the fourth capacitor C4, the voltage generated by the first terminal of the fourth capacitor C4 is transmitted to the first terminal of the fifth capacitor C5 through the third switch group 50.

[0158] The voltage generated at the first terminal of the first capacitor C1 and the voltage generated at the first terminal of the second capacitor C2, based on the voltage generated by the third capacitor C3 and the fourth capacitor C4, are used to alternately charge the first terminal of the fifth capacitor C5 through the third switch group 50, so as to generate an output voltage Vout that varies with the input voltage Vin at the signal output terminal.

[0159] In this embodiment, the input voltage Vin can be selected as any value as needed.

[0160] Specifically, when the voltage at the second terminal of the third capacitor C3 is 2VDD-0.7V, the voltage at the first terminal of the third capacitor C3 is 2VDD+Vin-1.4V. The added 0.7V is the forward voltage drop of the parasitic diode of the seventh MOSFET MN5, and Vin is the input voltage value of the signal input terminal. At this time, the voltage 2VDD+Vin-1.4V at the first terminal of the third capacitor C3 controls the eighth MOSFET MN6 to turn on, so that the voltage at the first terminal of the fourth capacitor C4 is the input voltage Vin.

[0161] When the voltage at the second terminal of the fourth capacitor C4 is 2VDD-0.7V, the voltage at the first terminal of the fourth capacitor C4 is 2VDD+Vin-0.7V.

[0162] The voltage 2VDD+Vin-0.7V at the first terminal of the fourth capacitor C4 controls the seventh MOSFET MN5 to conduct, so that the voltage at the first terminal of the third capacitor C3 is the input voltage Vin.

[0163] The voltage Vin at the first terminal of the third capacitor C3 controls the conduction of the ninth MOSFET MP3, and the conducting ninth MOSFET MP3 transmits the voltage 2VDD+Vin-0.7V at the first terminal of the fourth capacitor C4 to the signal output terminal.

[0164] At this time, the voltage at the first terminal of the third capacitor C3 is the input voltage Vin. In the next cycle, the voltage at the second terminal of the third capacitor C3 is 2VDD+Vin-0.7V, and the voltage at the first terminal of the third capacitor C3 becomes the input voltage 2VDD+Vin-0.7V.

[0165] The voltage 2VDD+Vin-0.7V at the first terminal of the third capacitor C3 controls the conduction of the eighth MOSFET MN6, making the voltage at the first terminal of the fourth capacitor C4 equal to the input voltage Vin.

[0166] The voltage Vin at the first terminal of the fourth capacitor C4 controls the conduction of the tenth MOSFET MP4, and the conducting tenth MOSFET MP4 transmits the voltage 2VDD+Vin-0.7V at the first terminal of the third capacitor C3 to the signal output terminal.

[0167] As can be seen from the above, through cyclic operation, the output voltage Vout at the signal output terminal is Vout = 2VDD + Vin - 0.7V.

[0168] Example 5

[0169] like Figure 7As shown, the structure of the voltage multiplier circuit in this embodiment differs from that in Embodiment 1 in that the third MOS transistor MP1 and the fifth MOS transistor MP2 are replaced with the third diode D3 and the fourth diode D4.

[0170] Specifically, the source of the first MOSFET MN1 and the source of the second MOSFET MN2 are connected to the power supply voltage VDD. The drain of the first MOSFET MN1 is connected to the gate of the second MOSFET MN2 and the first terminal of the first capacitor C1. The drain of the second MOSFET MN2 is connected to the gate of the first MOSFET MN1 and the first terminal of the second capacitor C2.

[0171] The anode of the third diode D3 is connected to the first terminal of the first capacitor C1. The input terminal of the second inverter INV2 is connected to the second terminal of the first capacitor C1. The output terminal of the second inverter INV2 is connected to the gate of the fourth MOSFET MN3. The cathode of the third diode D3 is connected to the drain of the fourth MOSFET MN3 and the second terminal of the third capacitor C3. The source of the fourth MOSFET MN3 is connected to the reference voltage. In this embodiment, the reference voltage is ground. In other embodiments, the reference voltage can be set to other values ​​as needed.

[0172] The anode of the fourth diode D4 is connected to the first terminal of the second capacitor C2. The cathode of the fourth diode D4 is connected to the drain of the sixth MOSFET MN4 and the second terminal of the fourth capacitor C4. The source of the sixth MOSFET MN4 is connected to the reference voltage. The gate of the sixth MOSFET MN4 is connected to the output terminal of the third inverter INV3. The input terminal of the third inverter INV3 is connected to the second terminal of the second capacitor C2 and the output terminal of the first inverter INV1.

[0173] The source of the seventh MOSFET MN5 and the source of the eighth MOSFET MN6 are connected to the second terminal of the fifth capacitor C5 and the signal input terminal Vin. The drain of the seventh MOSFET MN5 is connected to the gate of the eighth MOSFET MN6 and the first terminal of the third capacitor C3. The drain of the eighth MOSFET MN6 is connected to the gate of the seventh MOSFET MN5 and the first terminal of the fourth capacitor C4.

[0174] The drain of the ninth MOSFET MP3 and the drain of the tenth MOSFET MP4 are connected to the first terminal of the fifth capacitor C5 and the signal output terminal Vout. The source of the ninth MOSFET MP3 is connected to the gate of the tenth MOSFET MP4 and the first terminal of the fourth capacitor C4. The source of the tenth MOSFET MP4 is connected to the gate of the ninth MOSFET MP3 and the first terminal of the third capacitor C3.

[0175] This embodiment also discloses a voltage multiplication method for the aforementioned voltage multiplication circuit. The voltage multiplication method includes:

[0176] In the initial state, the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are precharged through the power supply voltage VDD and the first switch group 10, so that the voltage of the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 is precharged to VDD-0.7V.

[0177] A pulse signal is periodically provided to the second terminals of the first capacitor C1 and the second terminals of the second capacitor C2. The pulse signal consists of alternating high-level and low-level signals, so that the first terminal of the first capacitor C1 generates a voltage to charge the third capacitor C3, and the first terminal of the second capacitor C2 generates a voltage to charge the fourth capacitor C4. In this embodiment, the pulse signals provided to the second terminals of the first capacitor C1 and the second terminals of the second capacitor C2 are inverted.

[0178] When a high-level signal is provided to the second terminal of the first capacitor C1, the voltage generated at the first terminal of the first capacitor C1 is transmitted to the second terminal of the third capacitor C3 through the first switch control unit 20; when a low-level signal is provided to the second terminal of the first capacitor C1, the second terminal of the third capacitor C3 is connected to the reference voltage through the first switch control unit 20.

[0179] When a high-level signal is provided to the second terminal of the second capacitor C2, the voltage generated at the first terminal of the second capacitor C2 is transmitted to the second terminal of the fourth capacitor C4 through the second switch control unit 30; when a low-level signal is provided to the second terminal of the second capacitor C2, the second terminal of the fourth capacitor C4 is connected to the reference voltage through the second switch control unit 30.

[0180] Specifically, a high-level signal (i.e., the power supply voltage VDD) is provided to the second terminal of the first capacitor C1, and a low-level signal (i.e., 0) is provided to the second terminal of the second capacitor C2. The voltage at the first terminal of the first capacitor C1 is 2VDD-0.7V, where 0.7V is the forward voltage drop of the parasitic diode of the first MOSFET MN1.

[0181] The voltage 2VDD-0.7V at the first terminal of the first capacitor C1 controls the conduction of the second MOSFET MN2, causing the voltage at the first terminal of the second capacitor C2 to become VDD. At this time, since the second MOSFET MN2 is fully turned on, the 0.7V also disappears.

[0182] The fourth MOSFET MN3 is turned off by a low-level signal. The voltage 2VDD-0.7V at the first terminal of the first capacitor C1 is transmitted to the second terminal of the third capacitor C3 through the third diode D3, so that the voltage at the second terminal of the third capacitor C3 is 2VDD-1.4V. The added 0.7V is the on-state voltage drop of the third transistor D3. In this embodiment, the low-level signal is obtained by the second inverter INV2 flipping the high-level signal input to the second terminal of the first capacitor C1.

[0183] The high-level signal controls the sixth MOS transistor MN4 to conduct, so that the second terminal of the fourth capacitor C4 is connected to the reference voltage, that is, the voltage of the second terminal of the fourth capacitor C4 is 0; in this embodiment, the high-level signal is obtained by the third inverter INV3 flipping the low-level signal output by the first inverter INV1.

[0184] When a low-level signal is provided to the second terminal of the first capacitor C1 and a high-level signal is provided to the second terminal of the second capacitor C2, the voltage at the first terminal of the second capacitor C2 is 2VDD.

[0185] The voltage 2VDD at the first terminal of the second capacitor C2 controls the first MOSFET MN1 to turn on, so that the voltage at the first terminal of the first capacitor C1 becomes VDD.

[0186] The sixth MOSFET MN4 is turned off by a low-level signal. The voltage 2VDD at the first terminal of the second capacitor C2 is transmitted to the second terminal of the fourth capacitor C4 through the fourth diode D4, so that the voltage at the second terminal of the fourth capacitor C4 is 2VDD-0.7V, where 0.7V is the forward voltage drop of the fourth diode D4. In this embodiment, the low-level signal is obtained by the third inverter INV3 flipping the high-level signal output by the first inverter INV1.

[0187] The high-level signal controls the fourth MOS transistor MN3 to conduct, so that the second terminal of the third capacitor C3 is connected to the reference voltage, that is, the voltage of the second terminal of the third capacitor C3 is 0; in this embodiment, the high-level signal is obtained by the second inverter INV2 flipping the low-level signal input to the second terminal of the first capacitor C1.

[0188] As can be seen from the above, by alternating high and low level signals, the second terminals of the third capacitor C3 and the fourth capacitor C4 both generate voltage signals that vary in the range of 0 to 2VDD-0.7V, and the two voltage signals have a phase difference.

[0189] In this embodiment, in the initial state, the second terminal of the fifth capacitor C5 is pre-charged by the input voltage Vin, so that the voltage of the second terminal of the fifth capacitor C5 is the input voltage Vin. The first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4 are pre-charged by the input voltage Vin and through the second switch group 40, so that the voltage of the first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4 is Vin-0.7V.

[0190] When the voltage generated by the first terminal of the first capacitor C1 is supplied to the second terminal of the third capacitor C3, the voltage at the first terminal of the third capacitor C3 is transmitted to the first terminal of the fifth capacitor C5 through the third switch group 50; when the voltage generated by the first terminal of the second capacitor C2 is supplied to the second terminal of the fourth capacitor C4, the voltage generated at the first terminal of the fourth capacitor C4 is transmitted to the first terminal of the fifth capacitor C5 through the third switch group 50.

[0191] The first terminal of the fifth capacitor C5 is alternately charged by the third capacitor C3 and the fourth capacitor C4 based on the voltage generated at the first terminal of the first capacitor C1 and the voltage generated at the first terminal of the second capacitor C2, and by the third switch group 50, so as to generate an output voltage Vout at the signal output terminal that varies with the input voltage Vin. In this embodiment, the input voltage Vin can be selected as any value as needed.

[0192] Specifically, when the voltage at the second terminal of the third capacitor C3 is 2VDD-0.7V, the voltage at the first terminal of the third capacitor C3 is 2VDD+Vin-1.4V. The added 0.7V is the forward voltage drop of the parasitic diode of the seventh MOSFET MN5, and Vin is the input voltage value of the signal input terminal. At this time, the voltage 2VDD+Vin-1.4V at the first terminal of the third capacitor C3 controls the eighth MOSFET MN6 to turn on, so that the voltage at the first terminal of the fourth capacitor C4 is the input voltage Vin.

[0193] When the voltage at the second terminal of the fourth capacitor C4 is 2VDD-0.7V, the voltage at the first terminal of the fourth capacitor C4 is 2VDD+Vin-0.7V.

[0194] The voltage 2VDD+Vin-0.7V at the first terminal of the fourth capacitor C4 controls the seventh MOSFET MN5 to conduct, so that the voltage at the first terminal of the third capacitor C3 is the input voltage Vin.

[0195] The voltage Vin at the first terminal of the third capacitor C3 controls the conduction of the ninth MOSFET MP3, and the conducting ninth MOSFET MP3 transmits the voltage 2VDD+Vin-0.7V at the first terminal of the fourth capacitor C4 to the signal output terminal.

[0196] At this time, the voltage at the first terminal of the third capacitor C3 is the input voltage Vin. In the next cycle, the voltage at the second terminal of the third capacitor C3 is 2VDD-0.7V, and the voltage at the first terminal of the third capacitor C3 becomes the input voltage 2VDD+Vin-0.7V.

[0197] The voltage 2VDD+Vin-0.7V at the first terminal of the third capacitor C3 controls the conduction of the eighth MOSFET MN6, making the voltage at the first terminal of the fourth capacitor C4 equal to the input voltage Vin.

[0198] The voltage Vin at the first terminal of the fourth capacitor C4 controls the conduction of the tenth MOSFET MP4, and the conducting tenth MOSFET MP4 transmits the voltage 2VDD+Vin-0.7V at the first terminal of the third capacitor C3 to the signal output terminal.

[0199] As can be seen from the above, through cyclic operation, the output voltage Vout at the signal output terminal is Vout = 2VDD + Vin - 0.7V.

[0200] It should be noted that although only five embodiments are given above, the structure in Embodiment 1 can be further modified as needed. For example, only the seventh MOSFET MN5 and the eighth MOSFET MN6 can be replaced with the fifth diode D5 and the sixth diode D6, or only the ninth MOSFET MP3 and the tenth MOSFET MP4 can be replaced with the seventh diode D7 and the eighth diode D8, or the seventh MOSFET MN5 and the eighth MOSFET MN6 can be replaced with the fifth diode D5 and the sixth diode D6, and the ninth MOSFET MP3 and the tenth MOSFET MP4 can be replaced with the seventh diode D7 and the eighth diode D8. The specific principles can be derived from Embodiments 1 to 5, and will not be elaborated here.

[0201] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings; the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments and various different choices and modifications of the invention without departing from the scope and spirit of the invention. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A voltage multiplier circuit, characterized in that, include: First capacitor, second capacitor, third capacitor, fourth capacitor, fifth capacitor, first switch group, second switch group, third switch group, first switch control unit and second switch control unit; The first terminal of the first capacitor and the first terminal of the second capacitor are connected to the power supply voltage through the first switch group, and the second terminal of the first capacitor and the second terminal of the second capacitor are used to receive pulse signals. The first switch control unit is connected to the first terminal of the first capacitor and the second terminal of the third capacitor. The first switch control unit controls the switching between the first terminal of the first capacitor and the second terminal of the third capacitor based on the first control signal. The second switch control unit is connected to the first terminal of the second capacitor and the second terminal of the fourth capacitor. The second switch control unit controls the switching between the first terminal of the second capacitor and the second terminal of the fourth capacitor based on the second control signal. The first terminal of the third capacitor and the first terminal of the fourth capacitor are connected to the second terminal of the fifth capacitor and the signal input terminal through the second switch group. The first terminal of the third capacitor and the first terminal of the fourth capacitor are also connected to the first terminal of the fifth capacitor and the signal output terminal through the third switch group.

2. The voltage multiplier circuit as described in claim 1, characterized in that, The first switch group includes a first MOSFET and a second MOSFET. The source of the first MOSFET and the source of the second MOSFET are connected to the power supply voltage. The drain of the first MOSFET is connected to the gate of the second MOSFET and the first terminal of the first capacitor. The drain of the second MOSFET is connected to the gate of the first MOSFET and the first terminal of the second capacitor; or The first switch group includes a first diode and a second diode. The anodes of the first diode and the second diode are connected to the power supply voltage. The cathode of the first diode is connected to the first terminal of the first capacitor, and the cathode of the second diode is connected to the first terminal of the second capacitor.

3. The voltage multiplier circuit as described in claim 1, characterized in that, The first switch control unit includes a third MOSFET and a fourth MOSFET. The source of the third MOSFET is connected to the first terminal of the first capacitor. The gates of the third and fourth MOSFETs are used to receive a first control signal. The drains of the third and fourth MOSFETs are connected to the drain of the fourth MOSFET and the second terminal of the third capacitor. The source of the fourth MOSFET is connected to a reference voltage; or The first switch control unit includes a third diode and a fourth MOSFET. The anode of the third diode is connected to the first terminal of the first capacitor. The gate of the fourth MOSFET is used to receive a first control signal. The cathode of the third diode is connected to the drain of the fourth MOSFET and the second terminal of the third capacitor. The source of the fourth MOSFET is connected to a reference voltage.

4. The voltage multiplier circuit as described in claim 1, characterized in that, The second switch control unit includes a fifth MOSFET and a sixth MOSFET. The source of the fifth MOSFET is connected to the first terminal of the second capacitor. The gates of the fifth and sixth MOSFETs are used to receive a second control signal. The drain of the fifth MOSFET is connected to the drain of the sixth MOSFET MN4 and the second terminal of the fourth capacitor. The source of the sixth MOSFET is connected to a reference voltage; or The second switch control unit includes a fourth diode and a sixth MOSFET. The anode of the fourth diode is connected to the first terminal of the second capacitor. The gate of the sixth MOSFET is used to receive a second control signal. The cathode of the fourth diode is connected to the drain of the sixth MOSFET and the second terminal of the fourth capacitor. The drain of the sixth MOSFET is connected to a reference voltage.

5. The voltage multiplier circuit as described in claim 1, characterized in that, The second switch group includes a seventh MOSFET and an eighth MOSFET. The sources of the seventh and eighth MOSFETs are connected to the second terminal of the fifth capacitor. The drain of the seventh MOSFET is connected to the gate of the eighth MOSFET and the first terminal of the third capacitor. The drain of the eighth MOSFET is connected to the gate of the seventh MOSFET and the first terminal of the fourth capacitor; or The second switch group includes a fifth diode and a sixth diode. The anodes of the fifth diode and the sixth diode are connected to the second terminal of the fifth capacitor. The cathode of the fifth diode is connected to the first terminal of the third capacitor. The cathode of the sixth diode is connected to the first terminal of the fourth capacitor.

6. The voltage multiplier circuit as described in claim 1, characterized in that, The third switch group includes a ninth MOS transistor and a tenth MOS transistor. The drains of the ninth MOS transistor and the tenth MOS transistor are connected to the first terminal of the fifth capacitor. The source of the ninth MOS transistor is connected to the gate of the tenth MOS transistor and the first terminal of the fourth capacitor. The source of the tenth MOS transistor is connected to the gate of the ninth MOS transistor and the first terminal of the third capacitor. or The third switch group includes a seventh diode and an eighth diode. The cathodes of the seventh diode and the eighth diode are connected to the first terminal of the fifth capacitor. The anode of the seventh diode is connected to the first terminal of the fourth capacitor, and the anode of the eighth diode is connected to the first terminal of the third capacitor.

7. The voltage multiplier circuit as described in claim 1, characterized in that, The voltage multiplier circuit also includes a first inverter, the input terminal of which is connected to the second terminal of a first capacitor, and the output terminal of which is connected to the second terminal of a second capacitor.

8. The voltage multiplier circuit as described in claim 1, characterized in that, The voltage multiplier circuit further includes a second inverter and / or a third inverter. The input terminal of the second inverter is connected to the second terminal of the first capacitor, and the output terminal of the second inverter is used to output a first control signal. The input terminal of the third inverter is connected to the second terminal of the second capacitor, and the output terminal of the third inverter is used to output a second control signal.

9. A voltage multiplication method, characterized in that, For a voltage multiplication circuit as described in any one of claims 1 to 8, the voltage multiplication method includes: The first terminal of the first capacitor and the first terminal of the second capacitor are precharged by the power supply voltage and through the first switch group. A pulse signal is provided to the second terminal of the first capacitor and the second terminal of the second capacitor. The pulse signal consists of alternating high-level signals and low-level signals, so that the first terminal of the first capacitor generates a voltage to charge the third capacitor and the first terminal of the second capacitor generates a voltage to charge the fourth capacitor. The second terminal of the fifth capacitor is pre-charged by the input voltage, and the first terminals of the third capacitor and the first terminals of the fourth capacitor are pre-charged by the input voltage and through the second switch group. An output voltage is generated at the signal output terminal by using the voltage generated at the first terminal of the first capacitor based on the voltage generated at the first terminal of the first capacitor by the third and fourth capacitors and the voltage generated at the first terminal of the second capacitor, and by alternately charging the first terminal of the fifth capacitor by the third switch group.

10. The voltage multiplication method as described in claim 9, characterized in that, When a high-level signal is provided to the second terminal of the first capacitor, the voltage generated at the first terminal of the first capacitor is transmitted to the second terminal of the third capacitor through the first switch control unit; when a low-level signal is provided to the second terminal of the first capacitor, the second terminal of the third capacitor is connected to the reference voltage through the first switch control unit. When a high-level signal is provided to the second terminal of the second capacitor, the voltage generated at the first terminal of the second capacitor is transmitted to the second terminal of the fourth capacitor through the second switch control unit; when a low-level signal is provided to the second terminal of the second capacitor, the second terminal of the fourth capacitor is connected to the reference voltage through the second switch control unit.

11. The voltage multiplication method as described in claim 9, characterized in that, When the voltage generated by the first terminal of the first capacitor is supplied to the second terminal of the third capacitor, the voltage at the first terminal of the third capacitor is transmitted to the first terminal of the fifth capacitor through the third switch group; when the voltage generated by the first terminal of the second capacitor is supplied to the second terminal of the fourth capacitor, the voltage generated at the first terminal of the fourth capacitor is transmitted to the first terminal of the fifth capacitor through the third switch group.

Images