FPGA implementation method of non-correlation spread spectrum pseudo code synchronization

Abstract

The application discloses a kind of non-related spread spectrum pseudo code synchronization FPGA implementation method, comprising the following steps: obtaining parameters, the sampling position of the sampling point of data participating in correlation operation is calculated according to parameter calculation;The correlation operation value of the local pseudo code of the small section number K small section and sampling point data is calculated, and the final correlation value is obtained after the correlation value of K small section is squared and accumulated;Sampling data is accumulated according to sampling rate f s Sliding, the correlation operation result of different relative phases is obtained through correlation operation;The correlation result is cached, whether the central correlation value satisfies the normalization initial synchronization threshold value is compared, then the front and rear half chip correlation values are compared, the data phase is adjusted, and the pseudo code tracking is completed.The processing structure of the K small section local pseudo code correlation operation circuit based on data sliding of the application simply and effectively solves the problem that the correlation values at the boundaries of data bits 1 and 0 cancel each other out, and can balance the acquisition time and resource consumption, and has strong compatibility.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication system, especially relates to a non-correlation spread spectrum pseudo code synchronization FPGA implementation method. BACKGROUND

[0002] With the rapid development of communication technology and the complex communication environment, the high requirements of users on the anti-interference performance and security performance of communication system, the excellent anti-interference ability and high security of spread spectrum communication system make the spread spectrum communication technology develop rapidly. As a key technology of spread spectrum communication system, pseudo code synchronization has been studied by more and more scholars.

[0003] The existing pseudo code synchronization scheme is generally divided into three methods: sliding correlation method, matched filtering method and FFT capture method. Although the serial sliding correlation method has a simple structure, the processing delay is long and it is difficult to meet the low delay requirement of the system. Although the parallel sliding correlation method can shorten the processing delay, the system calculation amount is too large and the resource consumption is too much. The matched filtering method reduces the processing delay, but it is more complex to realize and needs large hardware resources. The FFT fast capture method starts from the frequency domain of the signal, replaces the time domain correlation operation with the frequency domain operation, effectively balances the capture time and hardware resources, but its disadvantage is that the time information is lost and the frequency in the time domain cannot be positioned.

[0004] Therefore, the balance between processing delay and resource occupation, the simple structure, the high phase accuracy and good timing of the pseudo code synchronization circuit after synchronization have always been the focus of research. In addition, the problem of missing synchronization caused by the mutual cancellation of the correlation values at the boundaries of data bits 1 and 0 is an important problem in the research of pseudo code synchronization. In the existing literature, the commonly used methods to solve the bit transition problem are delay multiplication method, half-bit method and matched filtering method. The delay multiplication method will increase the noise power and reduce the signal-to-noise ratio in the receiver; the half-bit method uses a correlation length of half a bit, and the correlation length is long and the calculation amount is large. Compared with the half-bit method, the correlation length of the present application is adjustable, the calculation amount is smaller and the resource consumption is lower; the matched filtering method has high algorithm complexity and complex circuit structure. SUMMARY

[0005] In view of the above defects of the prior art, the technical problem to be solved by the present application is that in the existing pseudo code synchronization circuit, the correlation values at the boundaries of data bits 1 and 0 cancel each other out to cause missed synchronization, imbalance between processing delay and hardware resources, complex synchronization circuit and other problems. The present application provides an FPGA implementation method of non-correlation spread spectrum pseudo code synchronization, aiming at the problems of missed synchronization caused by the correlation values at the boundaries of data bits 1 and 0 canceling each other out, high resource consumption of the synchronization circuit, large processing delay, complex circuit structure and other problems, a processing structure of a K-small-section local pseudo code correlation operation circuit based on data sliding is provided, and the selection of the small section number K, the small section length N and the normalized initial synchronization threshold threshold is given, which simply and effectively solves the problem of missed synchronization caused by the correlation values at the boundaries of data bits 1 and 0 canceling each other out, and can balance the acquisition time and resource consumption, and has strong compatibility.

[0006] To achieve the above object, the present application provides an FPGA implementation method of non-correlation spread spectrum pseudo code synchronization, comprising the following steps:

[0007] S1, obtaining parameters, including pseudo code rate f chip , sampling rate f s , bit rate f b , small section number K, small section pseudo code length N, and normalized initial synchronization threshold threshold;

[0008] S2, calculating the sampling position of the sampling point of the data participating in the correlation operation according to the parameters of step S1;

[0009] S3, calculating the correlation operation value of the small section local pseudo code with the sampling point data in step S2, and accumulating the correlation values of the K small sections after squaring to obtain the final correlation value corr_fine;

[0010] S4, sliding the sampling data in step S2 according to the sampling rate f s , and obtaining the correlation operation results of different relative phases through step S3;

[0011] S5, buffering the correlation results calculated in step S4, comparing whether the center correlation value meets the normalized initial synchronization threshold threshold, completing pseudo code acquisition when the data slides to the center correlation value greater than the normalized initial synchronization threshold, and then comparing the front and rear half chip correlation values to adjust the data phase and complete the pseudo code tracking.

[0012] Further, the length N of the small section pseudo code is set to be the same as the length N of the selected K small section local pseudo code; for local pseudo codes of different orders, the shortest truncated length N min consistent under the same signal-to-noise ratio SNR condition, wherein the relationship between the shortest truncated length N min and the signal-to-noise ratio SNR is:

[0013] N min = 9.279 x e -0.2339×SNR + 10.47 x e -0.03244×SNR .

[0014] Further, the number of segments K is set as K = 2, and the correlation operation is performed using K = 2.

[0015] Further, the normalized synchronization threshold threshold in step S1 is set as not greater than (K-1) / K.

[0016] Further, the normalized synchronization threshold is set as threshold = μ x (K-1) / K, μ = 0.70-0.95.

[0017] Further, the sampling position of the sampling point of the data participating in the correlation operation in each round in step S2 is set as 1, ceil(f s / f chip *1), ceil(f s / f chip *2),..., ceil(f s / f chip *(i-1), i = 1, 2,..., wherein ceil[] represents rounding up.

[0018] Further, the correlation operation value of the K-number-of-segment local pseudo code and the sampling point data in step S2 is calculated, the correlation values of the K segments are squared and accumulated to obtain the final correlation value corr_fine, and the correlation operation is directly performed.

[0019] Further, the correlation operation value of the K-number-of-segment local pseudo code and the sampling point data in step S2 is calculated, the correlation values of the K segments are squared and accumulated to obtain the final correlation value corr_fine, and the correlation operation is performed through a K-segment time division multiplexing correlation operation circuit.

[0020] Further, step S5 is implemented through a finite state machine.

[0021] Technical effects

[0022] The FPGA implementation method of the non-correlation spread spectrum pseudo code synchronization is based on a correlation operation sub-module as a core, and correlation operations are performed on K small local pseudo codes based on the relative phase of the sliding data adjustment, so that the pseudo code synchronization with high phase accuracy can be realized; and the correlation value square accumulation after the K small local pseudo code correlation operation solves the problem of the correlation value drop and synchronization leakage at the boundary of the bit sequence 1 and 0.

[0023] The concept, specific structure and generated technical effects of the present application will be further described below in combination with the drawings, so as to fully understand the purposes, features and effects of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 The system structure schematic diagram of the FPGA implementation method of the non-correlation spread spectrum pseudo code synchronization of the preferred embodiment of the present application is shown in the figure;

[0025] Figure 2 The pseudo code synchronization leakage synchronization probability and false synchronization probability schematic diagram of the FPGA implementation method of the non-correlation spread spectrum pseudo code synchronization of the preferred embodiment of the present application is shown in the figure;

[0026] Figure 3 The pseudo code synchronization correlation result and traditional pseudo code synchronization correlation operation result schematic diagram of the FPGA implementation method of the non-correlation spread spectrum pseudo code synchronization of the preferred embodiment of the present application is shown in the figure;

[0027] Figure 4 The two small segment correlation calculation schematic diagram of the FPGA implementation method of the non-correlation spread spectrum pseudo code synchronization of the preferred embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0028] In order to make the technical problems, technical solutions and beneficial effects of the present application more clearly understood, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0029] In the following description, specific details are set forth such as specific internal programs, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits and methods are omitted in order not to obscure the description of the present application with unnecessary details.

[0030] The application provides a non-correlation spread spectrum pseudo code synchronization FPGA implementation method, comprising the following steps:

[0031] S1, obtaining parameters, including pseudo code rate f chip , sampling rate f s , bit rate f b , signal-to-noise ratio SNR, the parameters are system parameters, and are determined according to a required working rate in a project early stage; segment number K is generally selected as K=2; segment pseudo code length N is obtained by a formula N min =9.279×e -0.2339×SNR +10.47×e -0.03244×SNR , and the minimum pseudo code length for system stable working is obtained, and N≥N min can be selected; a normalized initial synchronization threshold threshold=μ×(K-1) / K=μ / 2, wherein μ=0.70-0.95;

[0032] S2, sampling positions of sampling points of data participating in correlation operation are calculated according to the parameters in step S1, and the calculation values are 1, ceil(f s / f chip *1), ceil(f s / f chip *2),..., ceil(f s / f chip *(i-1)), i=1, 2,..., wherein ceil[] represents upward rounding;

[0033] S3, correlation operation values of K segment local pseudo codes of the segment number K and the sampling point data in step S2 are calculated, and the correlation value of the jth segment is , wherein the sampling data of the operator module, g is a local pseudo code value after bipolar conversion. The correlation values of the K segments are squared and accumulated to obtain a final correlation value

[0034] S4, the sampling data in step S2 is slid according to the sampling rate f s , and the correlation operation results of different relative phases are obtained through step S3;

[0035] S5, the correlation results calculated in step S4 are cached, and whether the central correlation value meets the normalized initial synchronization threshold threshold is compared; when the data is slid to the central correlation value greater than the normalized initial synchronization threshold, pseudo code capture is completed, then the front and rear half chip correlation values are compared, the data phase is adjusted, and pseudo code tracking is completed.

[0036] The synchronization effect is better when the lengths of the K small pieces of local pseudo codes are not the same, so the length N of the small piece of pseudo code is set to be the same as the length of the local pseudo code selected by K small pieces; for the local pseudo codes of different orders, under the condition of the same signal-to-noise ratio SNR, the shortest length N of the small piece of pseudo code meeting the synchronization requirement is min consistent, wherein the shortest length N of the small piece of pseudo code meeting the synchronization requirement is min The relationship between the signal-to-noise ratio SNR and the length N of the small piece of pseudo code meeting the synchronization requirement is as follows:

[0037] N min = 9.279 x e -0.2339×SNR + 10.47 x e -0.03244×SNR .

[0038] When K is greater than or equal to 2, the greater the value of K, the greater the minimum correlation value (K-1) * N in theory, the more reliable the pseudo code synchronization, but the longer the processing time of the correlation operation and the greater the consumption of circuit resources. The number of small pieces K is set to be K = 2, and the correlation operation is performed using K = 2.

[0039] The normalized synchronization threshold threshold in step S1 is set to be not greater than (K-1) / K. The normalized synchronization threshold is set to be threshold = μ x (K-1) / K, and μ = 0.70-0.95.

[0040] The sampling positions of the sampling points of the data participating in the correlation operation in each round in step S2 are set to be 1, ceil(f s / f chip *1), ceil(f s / f chip *2),..., ceil(f s / f chip *(i-1), i = 1, 2,..., wherein ceil[] represents rounding up.

[0041] The correlation operation values of the small piece of local pseudo code with the number of small pieces K and the sampling point data in step S2 are calculated, the correlation values of the K small pieces are squared and accumulated to obtain the final correlation value corr_fine, which specifically includes directly performing the correlation operation, or performing the correlation operation through a K small piece time division multiplexing correlation operation circuit.

[0042] Step S5 is implemented through a finite state machine.

[0043] The following will illustrate the specific process of the FPGA implementation method of the non-correlation spread spectrum pseudo code synchronization of the application.

[0044] As Figure 1The system structure diagram of the present invention is shown. This design mainly consists of a pseudo code correlation circuit and a phase adjustment circuit. The sampled data after carrier synchronization is input into the pseudo code synchronization system and enters the data sliding shift register. The counting and extraction circuit completes the selection of the sampling points of the data participating in the correlation operation in each round in step S2. The pseudo code correlation operation submodule calculates the correlation operation value of the local pseudo code of the small segment number K and the sampling point data in step S2. The correlation value of the jth segment is Among them, data is the sampled data input to the pseudo code synchronization correlation operation submodule, and g is the local pseudo code value after bipolar conversion. The correlation values ​​of K small segments are squared and then accumulated to obtain the final correlation value Complete step S3. The input data continuously slides into the data sliding shift register, completing the phase sliding of the carrier-synchronized data. After the correlation operation, pseudo-code synchronization correlation operation values ​​with different relative phases are obtained, completing step S4. The calculated correlation operation value is stored in the shift register, and the center correlation value is compared with the synchronization threshold. If the synchronization threshold is met, synchronization capture is completed. The correlation values ​​of the preceding and following half-chips are then compared. If the correlation value of the preceding half-chip is greater than the correlation value of the lagging half-chip, the phase of the input data is adjusted forward through the phase adjustment circuit. If the correlation value of the preceding half-chip is less than the correlation value of the lagging half-chip, the phase of the input data is adjusted backward through the phase adjustment circuit. If the correlation value of the preceding half-chip is equal to the correlation value of the lagging half-chip, the phase of the input data remains unchanged, and the correlation values ​​of the preceding and following half-chips are continuously compared to achieve pseudo-code tracking. Finally, the pseudo-code synchronized data is output through the valid data output control circuit, completing step S5.

[0045] Assume the pseudo code is rate f chip =3MHz 10th order Gold code, by x 10 +x 8 +x 7 +x 4 +x 2 +x 1 +1 initial phase 1000000000 and x 10 +x 9 +x 8 +x 7 +x 5 +x 4 +1 Two m-sequences with initial phase 1001001000 are generated, with sampling rate f s =40MHz, pseudo code synchronous input data signal to noise ratio is SNR = -7dB. The number of segments is K = 2. According to the formula N min =9.279×e -0.2339×SNR +10.47×e -0.03244×SNR Obtain the minimum pseudo code length N for stable operation of the systemmin ≈60.85, then N≥N min The length N=256 of the small code segment is selected. The threshold=μ×(K-1) / K=μ / 2 is obtained from the normalized synchronization threshold formula, wherein μ=0.70-0.95, and the threshold≈0.47 is selected. The sampling position formula of the sampling points participating in the correlation operation is: 1, ceil(f s / f chip *1), ceil(f s / fchip*2,..., ceilfs / fchip*(i-1), i=1, 2,..., wherein ceil[] represents rounding up, and in the present example, the positions of the data sampling points participating in the correlation operation are 1, 14, 27,....

[0046] As Figure 2 described, the synchronization miss synchronization probability and false synchronization probability of the code segment provided in the present application are very small and basically tend to zero, which indicates that the code segment synchronization algorithm has excellent performance. As Figure 3 described, the correlation results of the code segment provided in the present application and the correlation results of the traditional code segment synchronization correlation operation are compared, and it can be seen from the comparison of the correlation results that the correlation peak of the traditional correlation result is reduced at the bit transition, causing miss synchronization. The simulation test shows that the miss synchronization probability of the code segment synchronization algorithm provided in the present application is 0, while the miss synchronization probability of the traditional correlation operation is 15.79%, and the present application well solves the problem of the correlation peak reduction at the bit transition.

[0047] In the present example, for the sampling data in the data sliding shift register, the correlation operation of the two small segments selects one sampling point in each chip for correlation operation. The input data in the data sliding shift register to be subjected to code segment synchronization are [d[0], d[1], d[2],...] in turn. The correlation values of the two small segments are:

[0048] corr_s1_value=-d[0]-d

[13] -d

[26] +d

[40] +...-d

[3400] ;

[0049] corr_s2_value=-d

[3413] +d

[3426] -d

[3440] -d

[3453] +...+d

[6813] ;

[0050] The final correlation value is obtained by squaring and adding the two values:

[0051] corr_fine=|corr_s1_value|^2+|corr_s2_value|^2.

[0052] As Figure 4The data continuously slide in the shift register, no correlation peak appears when the local pseudo code and the received data pseudo code are not phase aligned, and a correlation peak appears when the local pseudo code and the received data pseudo code are phase aligned. The data continuously slide into the shift register, the correlation result is calculated, and the buffer 13 (in this example, there are floor(f s / f chip ) = 13 sample points) correlation results are stored. Whether the central correlation value satisfies the normalized initial synchronization threshold is compared. When the data slide to the central correlation value greater than the normalized initial synchronization threshold, the pseudo code capture is completed. Then, the correlation values of the front and rear half code chips are compared. If the correlation value of the front half code chip is greater than that of the rear half code chip, the data phase is adjusted forward by one sample point. If the correlation value of the front half code chip is less than that of the rear half code chip, the data phase is adjusted backward by one sample point. The sampling data continuously slide to calculate the correlation value, and the data phase is continuously adjusted to complete the pseudo code tracking.

[0053] The preferred embodiments of the present application are described in detail above. It should be understood that those skilled in the art can make many modifications and variations without creative work based on the concept of the present application. Therefore, any technical solution obtained by logical analysis, reasoning or limited experiment based on the prior art according to the concept of the present application shall be within the protection scope defined by the claims.

Claims

1. A method for realizing FPGA synchronization of non-correlated spread spectrum pseudo-code, characterized in that: The following steps are involved: S1, obtain parameters, including pseudo code rate f chip , sampling rate f s , bit rate f b , the number of small segments K, the length of the small segment pseudo code N, the normalized initial synchronization threshold threshold; the normalized synchronization threshold threshold is set to be selected to be no greater than (K-1) / K; S2, calculate the sampling positions of the sampling points of the data participating in the correlation operation according to the parameters of step S1; the sampling positions of the sampling points of the data participating in the correlation operation in each round are set to 1, ceil(f s / f chip *1),ceil(f s / f chip *2),……,ceil(f s / f chip *(i-1)), i=1,2,..., where ceil[] means rounding up; S3, calculating the correlation operation value of the small segment local pseudo code of the number K of small segments and the sampling point data in step S2, squaring the correlation values ​​of the K small segments and then accumulating them to obtain the final correlation value corr_fine; S4, the sampled data in step S2 is processed at a sampling rate f s Slide, and obtain the correlation operation results of different relative phases through step S3; S5, cache the correlation results calculated in step S4, compare whether the center correlation value meets the normalized initial synchronization threshold, and complete the pseudo code capture when the data slides to the center correlation value greater than the normalized initial synchronization threshold. Then compare the correlation values ​​of the previous and next half code bits, adjust the data phase, and complete the pseudo code tracking.

2. The FPGA implementation method of the non-correlated spread spectrum pseudo code synchronization according to claim 1, characterized in that: The length N of the small pseudo code segment is set to select the local pseudo code of K small segments with the same length as N; for local pseudo codes of different orders under the same signal-to-noise ratio SNR conditions, the shortest intercept length N that meets the synchronization requirements min Consistent, where the shortest intercept length N min The relationship between the signal-to-noise ratio (SNR) is: N min =9.279×e -0.2339×SNR +10.47×e -0.03244×SNR 。 3. The FPGA implementation method of the non-correlated spread spectrum pseudo code synchronization according to claim 1, characterized in that: The number of small segments K is set to K=2, and the correlation operation is performed using K=2.

4. The FPGA implementation method of non-correlated spread spectrum pseudo code synchronization according to claim 3, wherein: The normalized synchronization threshold is set to threshold=μ×(K-1) / K, μ=0.70~0.

95.

5. The FPGA implementation method of non-correlated spread spectrum pseudo code synchronization according to claim 1, characterized in that: Calculate the correlation operation value of the small segment local pseudo code of the number K of small segments and the sampling point data in step S2, square the correlation values ​​of the K small segments and then accumulate them to obtain the final correlation value corr_fine, specifically including directly performing the correlation operation.

6. The FPGA implementation method of non-correlated spread spectrum pseudo code synchronization according to claim 1, characterized in that: Calculate the correlation operation value of the small segment local pseudo code of the number K of small segments and the sampling point data in step S2, square the correlation values ​​of the K small segments and then accumulate them to obtain the final correlation value corr_fine, specifically including performing correlation operation through the K small segment time division multiplexing correlation operation circuit.

7. The FPGA implementation method of non-correlated spread spectrum pseudo code synchronization according to claim 1, characterized in that: The step S5 is implemented by a finite state machine.

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