A Fast Acquisition Method for Low Signal-to-Noise Ratio and Large Dynamic Short Message Signals

Abstract

A fast acquisition method for low signal-to-noise ratio and large dynamic short message signals. First, the sampled intermediate frequency signal is down-converted to the baseband, then the baseband signal is accumulated and decelerated, and the data after accumulation and deceleration is sequentially stored in the buffer area. The local pseudo-code is written into the buffer area with the same width, and the local pseudo-code rate is corrected according to the center frequency point of each frequency interval. After the data storage is completed, reading starts. The read data is multiplied by the corresponding chip to achieve parallel despreading and quadrature frequency conversion, and is divided into different frequency intervals. Two storage areas are used for ping-pong caching of the data after partitioning the intervals, and then high-speed FFT operations are performed. After all code phases are searched in the current frequency interval, the frequency interval is changed and the search continues. If all frequency intervals are searched, a decision on whether the acquisition is successful is made. The storage space occupied by the present invention is reduced to 1 / 98 of the traditional method, the number of parallel correlation channels is reduced to 1 / 6, the number of FFT cores used is reduced to 1 / 4 of the traditional method, and the acquisition time is controlled within 40 ms.

Description

Technical Field

[0001] The present invention belongs to the field of communications and relates to a method for quickly capturing low signal-to-noise ratio and large dynamic short message signals. Background Art

[0002] The direct sequence spread spectrum communication system has the advantages of strong anti-interference ability, low probability of being intercepted, strong anti-multipath ability, code division multiple access, etc., and is more and more widely used in military and civilian communications. This system is widely used in the field of aerospace TT&C, effectively combining remote control, telemetry, ranging and velocity measurement. In order to further improve the signal concealment, reduce the signal detectability, and increase the number of served users, a spread spectrum communication method with short message bursts is adopted, requiring the receiving end to complete the capture, tracking, demodulation, decoding and information analysis of the spread spectrum signal within an extremely short time.

[0003] For traditional spread spectrum signal capture methods, to quickly capture short message signals, a large amount of device resources are required, which cannot adapt to the on-board environment with limited device resources. Among the currently available public publications, some involve the capture methods of low signal-to-noise ratio burst spread spectrum signals. For example, "Compatible Fast Capture Algorithm for Burst Spread Spectrum Signals Based on FFT" (Xing Yabin) proposes an improved compatible fast capture algorithm for burst spread spectrum signals based on FFT, which can achieve the fast capture of burst spread spectrum signals. However, the algorithm structure is complex, using multiple FFT operation units, occupying a large amount of device resources, and is not suitable for the environment with limited device resources. "A Low-Complexity Fast Synchronization Method for Burst Spread Spectrum Communication" (Wang Tianxiong) uses differential accumulation for fast capture of spread spectrum signals, which is a capture algorithm based on a matched filter. This method does not estimate the capture time, and multiple-stage matched filters will occupy a large amount of device resources and are not suitable for the environment with large Doppler dynamics. Summary of the Invention

[0004] The technical problem solved by the present invention is: overcoming the deficiencies of the prior art, providing a method for quickly capturing low signal-to-noise ratio and large dynamic short message signals, reducing the occupied storage space to 1 / 98 of the traditional method, reducing the number of parallel correlation channels to 1 / 6, reducing the number of FFT cores used to 1 / 4 of the traditional method, and controlling the capture time within 40 ms.

[0005] The technical solution of the present invention is:

[0006] A method for quickly capturing low signal-to-noise ratio and large dynamic short message signals, the steps are as follows:

[0007] (1) Perform quadrature down-conversion on the data after AD sampling to move the data from intermediate frequency to baseband;

[0008] (2) Perform accumulation and speed reduction on the down-converted data;

[0009] (3) Delay the data after the accumulation speed reduction by m*k times, generate m*k data and store them in the same address of buffer RAM1 in sequence, writing one data per clock cycle, and reading out the m*k data corresponding to a certain address in RAM1 at one time when reading, which is equivalent to converting the data after the accumulation speed reduction from serial to parallel processing;

[0010] (4) Divide the frequency range according to the Doppler range and signal-to-noise ratio, and correct the local pseudo-code rate according to the center frequency point of each frequency range;

[0011] (5) Let the initial values of i and j be both 1;

[0012] (6) At the i-th code phase, read out the m*k data in one address of RAM1 and the m*k chips in the corresponding address of RAM2 in each clock cycle, multiply the data and the chips correspondingly to achieve parallel despreading, divide the m*k despreading results obtained in the same clock cycle into k groups, with m despreading results in each group, and perform parallel accumulation on the m despreading results to obtain k groups of accumulation results;

[0013] (7) Use the center frequency point of the j-th frequency range to perform quadrature frequency conversion on the data after despreading and accumulation, and divide the intervals for the accumulation results after quadrature frequency conversion of all clock cycles at the current code phase;

[0014] (8) Use two storage areas to perform ping-pong caching on the data after interval division. When one of the two storage areas is in the write state, the other is in the read state;

[0015] (9) After the data storage is completed, call a pipelined FFT core to perform FFT operation. When the local pseudo-code phase is aligned with the data after AD sampling in step (1), the peak position of the FFT spectrum is the Doppler frequency offset;

[0016] (10) Judge whether i is equal to I, where I is the total number of code phases. If not, slide one code phase, that is, increment the value of i by 1, and execute steps (6)-(9). Sliding the code phase is achieved by changing the initial read address of RAM2; if equal, enter step (11);

[0017] (11) Judge whether j is equal to J, where J is the total number of frequency ranges. If not, increment the value of j by 1, and let i = 1, and execute steps (6)-(10); if equal, enter step (12);

[0018] (12) If the peak value of the FFT spectrum is greater than the preset threshold, it is judged as successful capture, and start the tracking module; if the peak value of the FFT spectrum is less than the preset threshold, it is judged as failed capture, and return to step (1) to start the capture again.

[0019] Preferably, in the step (2), assuming that the global clock is clk, the accumulated data rate after deceleration is clk / N, where N is the number of accumulation points.

[0020] Preferably, in the step (3), the depth D of the buffer RAM1 e is with a width of m*k, N being the number of accumulation points, and R being the accumulated data rate.

[0021] Preferably, in the step (4), assuming that the radio frequency is F s , the pseudo-code rate is f c , the Doppler frequency range is -f d to f d , the capture operation cumulative time is 1 / R, and the minimum number of frequency interval J is R is the accumulated data rate; assuming that the center frequency point of the frequency interval is f q , then the corrected pseudo-code rate is

[0022] Preferably, the sampling rate of the local pseudo-code is the same as the accumulated data rate after deceleration, which is clk / N.

[0023] Preferably, the depth of the pseudo-code storage space is where f c is the pseudo-code rate and H is the pseudo-code period.

[0024] Preferably, in the step (8), the storage depth of one storage area is D / k, where D is the number of FFT operation points.

[0025] Preferably, D = R a / R, R a is the data rate after despreading and accumulation in step (5), and R is the accumulated data rate in step (3).

[0026] Preferably, in the step (9), a pipelined FFT core is called to perform high-speed FFT operation using k times the global clock.

[0027] Preferably, the capture time = data buffer time + capture operation time;

[0028] where R is the accumulated data rate, f c is the pseudo-code rate, and H is the pseudo-code period;

[0029] If during capture, the sliding accuracy of the pseudo-code phase is 1 / t chips, then the capture operation time for one round in each frequency interval is clock cycles, and the capture time required for J serially searched frequency intervals is clock cycles, where D is the number of FFT operation points.

[0030] The beneficial effects of the present invention are as follows:

[0031] The present invention proposes a novel and efficient capture architecture based on multi-level data caching, and realizes a fast capture method for short message signals with low signal-to-noise ratio, large dynamic range, and short duration through progressive caching. Frequency intervals are divided according to the Doppler dynamics and signal-to-noise ratio requirements, and the center frequency point of each interval is used to correct the pseudo-code rate, so as to realize the fast capture of short message signals with low signal-to-noise ratio, large dynamic range, and short duration. The capture architecture is flexible and can adapt to the capture of short message signals under different signal-to-noise ratios and Doppler frequency offsets by changing parameters. Under the same signal-to-noise ratio, Doppler dynamics, and capture time requirements, by adopting the method proposed by the present invention, the storage space occupied by the algorithm is reduced to 1 / 98 of the traditional method, the number of parallel correlation channels is reduced to 1 / 6, the number of FFT cores used is reduced to 1 / 4 of the traditional method, and the capture time is controlled within 40 ms. Brief Description of the Drawings

[0032] Figure 1 is the capture flow chart;

[0033] Figure 2 is the capture control flow chart;

[0034] Figure 3 is the capture flow chart of the traditional capture method. Detailed Embodiments

[0035] As Figure 1 shown, based on the partial correlation FFT algorithm, the present invention stores the zero intermediate frequency signal after accumulation and deceleration, and converts the serial sampling points into parallel processing, which can save device resources while ensuring fast capture; to ensure that the local pseudo-code does not slide more than half a chip relative to the received signal within one accumulation time of the capture operation under low signal-to-noise ratio and large Doppler frequency offset, the Doppler is divided into multiple intervals, and the center frequency point of each interval is used to correct the local pseudo-code rate; in order to match the data throughput of RAM3 and save FFT operation resources, a high multiple clock is used for FFT operation to quickly obtain the Doppler position and code phase.

[0036] Embodiment:

[0037] (1) Down-conversion: Perform quadrature down-conversion on the data after AD sampling to move the data from the intermediate frequency to the baseband.

[0038] (2) Accumulation and deceleration: Accumulate the down-converted signal. The purpose of accumulation is to reduce the subsequent data storage amount, that is, to reduce the storage resource size occupied by RAM1. The number of accumulation points N needs to be determined according to the spreading code rate of the input signal. In order to reduce signal loss, the data rate after accumulation needs to be set to 3 to 4 times the pseudo-code rate. Assuming the global clock is clk, the data rate after accumulation is clk / N.

[0039] (3) Data storage: The data after cumulative deceleration is sequentially stored in the buffer, which is Figure 1 RAM1. When writing data into the buffer, the data after cumulative deceleration is delayed m*k times, generating m*k data and storing them at the same address in RAM1. One data is written in one clock cycle. When reading data, the m*k data corresponding to a certain address in RAM1 are read out at once, which is equivalent to converting the data after cumulative deceleration from serial to parallel processing.

[0040] The width m*k and depth D of the buffer e are determined according to the capture time, Doppler frequency offset, and the requirement of the carrier-to-noise ratio of the received signal. To obtain the specific values of the buffer width and depth, it is first necessary to determine the cumulative data rate R of the capture operation. Assume that the carrier-to-noise ratio of the received signal is CNR (the carrier-to-noise ratio corresponds to the received signal level), and the signal-to-noise ratio after the capture operation is SNR. R can be calculated as R = 10 (CNR-SNR) . Usually, when the signal-to-noise ratio SNR after the capture operation is greater than or equal to 20 dB, a capture probability of 99% can be achieved. Then the depth D of the data buffer e is

[0041] (4) Local pseudo-code generation and storage: At low signal-to-noise ratios, to achieve a certain capture probability, a long accumulation time is required; therefore, when the Doppler frequency offset is large, under the action of the code Doppler, if the local pseudo-code rate involved in the correlation operation is the nominal code rate, during the capture operation accumulation time, the relative sliding between the local pseudo-code and the received signal will exceed half a chip, resulting in capture failure. Therefore, before generating the local pseudo-code, it is necessary to divide different frequency intervals according to the Doppler range and signal-to-noise ratio, and correct the local pseudo-code rate according to the center frequency point of each frequency interval.

[0042] Assume that the radio frequency is F s , the pseudo-code rate is f c , the Doppler frequency range is -f d ~f d , and the capture operation accumulation time is 1 / R. To ensure that the code phase sliding is less than half a chip during the capture accumulation time, the minimum number J of frequency intervals is Assume that the center frequency point of the frequency interval is f q , then the corrected pseudo-code rate is The Doppler frequency range that can be captured by this method is not limited to -100 kHz to 100 kHz and can be extended according to actual needs.

[0043] Refer to Figure 1, after the local pseudo-code is generated, it is stored in the buffer RAM2, and the width of the storage area is the same as the stored data. That is, the local pseudo-code with a sampling rate of clk / N is delayed m*k times, and m*k chips are generated and stored at the same address in RAM2. One chip is written in one clock cycle. When reading the pseudo-code, the m*k chips corresponding to a certain address in RAM2 are read out at one time, which is equivalent to converting the local pseudo-code from serial to parallel processing.

[0044] Since the local code phase needs to be slid during the acquisition operation, and the sliding of the code phase is achieved by changing the initial reading address of RAM2. Compared with the stored data, the local pseudo-code needs to store one more code cycle of data volume. The sampling rate of the local pseudo-code is the same as the data rate after accumulation deceleration, which is clk / N. Assume the pseudo-code rate is f c , the pseudo-code period is H, then the depth of the pseudo-code storage space is

[0045] (5) Parallel despreading and parallel accumulation: After the signal is despread, it needs to be accumulated again to reduce the number of FFT operation points. In the present invention, due to the low signal-to-noise ratio of the received signal, frequency intervals are divided during acquisition. To save device resources, different frequency intervals are searched serially. To ensure fast acquisition within 40 ms, parallel despreading of m*k data is required, and the re-accumulation is also performed in parallel. The data rate R after parallel accumulation a is determined by the Doppler frequency offset. Generally, the data rate is required to be 3 to 4 times the maximum Doppler frequency offset. The number of accumulations m can be calculated,

[0046] From steps (3) and (4), and Figure 1 it can be obtained that after the data and pseudo-code are stored, m*k data and chips in one address are read out in one clock cycle, the data and chips are multiplied correspondingly to achieve parallel despreading, and then the m despreading results in the same clock cycle are accumulated in parallel. k accumulation results can be obtained in each clock cycle.

[0047] (6) Divide frequency intervals: According to the number of frequency intervals obtained in step (4), the signal after despreading and accumulation is orthogonally frequency-converted with the center frequency point of the jth interval. Here, the center frequency point and the pseudo-code rate correction amount in step (4) are in one-to-one correspondence. To save resources, the division of frequency intervals is performed serially, that is, after searching the code phase corresponding to one frequency interval, the next frequency interval is changed. The initial value of j is 1.

[0048] (7)Data storage after frequency interval division: After dividing the frequency interval, there are k sampling points in one clock cycle. The k sampling points need to be juxtaposed and written into one address of the data buffer RAM3 simultaneously. Since the subsequent FFT operation occupies a large amount of device resources, in order to achieve the reuse of FFT operation resources, only one FFT module is used to complete all operations. When reading data, a clock k times the global clock is used, and this high multiple clock is also used for the subsequent FFT operation. Since there is a buffer RAM3 between the two clock domains for data isolation, it meets the requirements of cross-clock domain processing.

[0049] To save the capture time, two storage areas are used for ping-pong caching of the data after frequency interval division. When one storage area is in the write state, the other is in the read state. One address of the storage area stores k accumulation results, and the storage depth is D / k, where D is the number of FFT operation points, which is determined by the signal-to-noise ratio and Doppler frequency offset, and can be calculated from the parameter R in step (3) and the parameter R in step (5). a Calculated as, D = R a / R.

[0050] (8)FFT operation: After the data storage is completed, a pipelined FFT core is called and the operation is performed using a clock k times the global clock to achieve the reuse of FFT. When the local pseudo-code phase is aligned with the data after AD sampling, the peak position of the FFT spectrum is the Doppler frequency offset.

[0051] (9)Capture result decision: The capture decision module controls the entire capture process. The capture control flow chart is as Figure 2 shown. After the capture starts, the data and local pseudo-code are cached according to steps (3) and (4) respectively. After both are cached, parallel despreading and accumulation are performed, then the frequency interval is divided according to step (6), and then data caching and high-speed FFT operation are performed according to steps (7) and (8). After searching all code phases, it is judged whether all frequency intervals have been searched. If not, the value of j is incremented by 1, the frequency interval is changed, and the above steps are repeated to continue searching all code phases for capture; if all frequency intervals have been searched, a decision on whether the capture is successful is made, and a dynamic threshold (N times the average value of each frame of FFT operation result) is set. If the FFT peak is greater than the threshold, it is judged that the capture is successful and the tracking module is started; if the peak is less than the threshold, it is judged that the capture fails, the capture module is reset, and the capture starts again.

[0052] (10)Capture time calculation: The capture time includes the data caching time and the capture operation time.

[0053] (a)Data caching time: From steps (3) and (4), the pseudo-code caching requires one more pseudo-code period than the data caching. Therefore, the time required for caching is the pseudo-code caching time, which can be obtained through calculation.

[0054] (b) Acquisition operation time: Since two buffers are set up before the FFT operation to perform ping-pong buffering on the data, that is, the FFT operation and data buffering are carried out simultaneously, and the FFT operation is performed using a high multiple clock, the FFT operation time is the same as the data buffering time. Therefore, the FFT operation can be omitted when calculating the acquisition time. From steps (5)-(8), the Doppler frequency offset is divided into J intervals, and serial search is performed in each interval. First, calculate the acquisition time required for one frequency interval. k sampling points with a rate of R a can be output in one clock cycle, and each frame of FFT operation requires D sampling points with a rate of R a . That is, it takes D / k clock cycles, which is the acquisition time for one frequency interval and one pseudo-code phase acquisition operation. Assume that during acquisition, the sliding accuracy of the pseudo-code phase is 1 / t chips. Then the acquisition operation time for one round in each frequency interval is clock cycles. The acquisition time required for J serially searched frequency intervals is clock cycles.

[0055] Examples of each parameter: Taking the received signal level of -130 dBm (corresponding to a carrier-to-noise ratio CNR of 42 dBHz), a Doppler frequency offset range of -100 kHz to 100 kHz, an acquisition time within 40 ms, a pseudo-code period H of 1023, a pseudo-code rate f c of 3.069 Mcps, a radio frequency frequency F s of 2 GHz, and a global clock of 60 MHz as an example, examples are given for each parameter in the present invention.

[0056] In step (2), the data rate after accumulation needs to be set to 3 to 4 times the pseudo-code rate. Therefore, the number of accumulation points N can be set to 6. Since the acquisition signal-to-noise ratio SNR is greater than or equal to 20 dB, the acquisition probability can reach 99%. Therefore, the acquisition operation accumulated data rate R is less than or equal to 158 bps. The number of divided frequency intervals J is obtained by rounding up according to the formula in step 4. Here, it can be set to 2, that is, divided into 2 frequency intervals. The data rate R a before the FFT operation needs to be set to 3 to 4 times the maximum Doppler frequency offset. Considering the integer multiple relationship between this rate and the global clock, R a can be set to 312.5 kbps. The number of FFT points D can be obtained through R aIt is calculated by R and is a power of 2 to the nth, so D can be set to 2048 here. The number m of parallel accumulations can be obtained by rounding the formula in step (5), and can be set to 32 here. During capture, the code phase sliding accuracy is half a chip, that is, t can be taken as 2. To complete the serial capture of 2 frequency intervals within 40 ms, according to the formula in step (10), the number k of parallel results after accumulation in step (5) is rounded up and set to 4. At this time, the specific capture time is 34.9 ms; the number of channels for parallel despreading is m*k = 128 channels.

[0057] Resource occupancy estimation: Since the on-board device resources are limited, the resources occupied by the algorithm have always been a concern. While ensuring fast capture, this method effectively reduces the resources occupied by the algorithm. The following estimates the storage space occupied by the algorithm and the number of FFT cores used.

[0058] (a) In step (3), the size of the storage resource occupied by the data cache RAM1 is B1 is the sum of the IQ data widths after the accumulation speed reduction. According to engineering experience, B1 can be set to 5 + 5 = 10 bit. In step (4), the size of the storage resource occupied by the local pseudo-code cache RAM2 is In step (7), the size of the storage resource occupied by the data cache RAM3 is B2 is the sum of the IQ data bit widths. To meet the capture under low signal-to-noise ratio, B2 needs to be set to 12 + 12 = 24 bit.

[0059] The storage space occupied by the algorithm is the sum of RAM1, RAM2, and RAM3. Using the parameters in step 11, the total storage resource occupied can be obtained as 797.839 kbit.

[0060] (b) From steps (7) and (8), since the present invention uses a high multiple clock to read the data in RAM3 and perform FFT operations, realizing the reuse of FFT operation resources, the algorithm only uses 1 FFT core.

[0061] (c) Comparison of resource occupancy with traditional spread spectrum capture methods: To capture spread spectrum signals with large Doppler frequency offsets and low signal-to-noise ratios, traditional capture methods also need to divide frequency intervals and correct the pseudo-code rate according to the divided frequency intervals before despreading. To shorten the capture time, it is necessary to increase the number of parallel processing channels. The block diagram of the traditional capture method is as Figure 3 shown.

[0062] Taking the above parameters as examples, i.e., the global clock clk is 60 MHz, each sampling point is serially processed under the global clock, the pseudo-code period H is 1023, the number of coherent accumulation points Nc is 192, R is 158 bps, t is 2 (i.e., the code phase sliding accuracy is half a chip), the number of divided frequency intervals is 2, the number of FFT operation points is 2048, and the time required for each frequency interval to serially search for the code phase once is To achieve fast acquisition within 40 ms, each frequency interval needs to be controlled within 20 ms, and a total of 799 code phase parallel searches are required.

[0063] The time required for caching 799 code phase data is If one FFT core is used for operation, the time required for operation is 799 * 2048 = 1,636,352 clock cycles, which amounts to 27.3 ms in total. This does not match the data storage time, and 4 FFT cores are required for parallel operation.

[0064] To achieve the same performance indicators and acquisition time as the present invention, the bit widths of the 799 parallel correlation operation IQ data in the traditional acquisition method need to be set to 12 bits, the number of FFT points is set to 2048, and two memories are used for ping-pong caching. The occupied memory resources are 2 * 24 * 2048 * 799 = 78.544 Mbit.

[0065] Under the conditions of the same performance indicators and acquisition time, Table 1 shows the comparison of the resources occupied by the present invention and the traditional spread spectrum signal acquisition method on the FPGA.

[0066] Table 1 Comparison of the resources occupied by the present invention and the traditional spread spectrum signal acquisition method on the FPGA

[0067] Storage space Number of parallel related paths Number of FFT cores The present invention 797.839 kbit 128 paths 1 Traditional method 78.544 Mbit 799 paths 4

[0068] It can be seen that this method effectively reduces the device resources occupied by the algorithm while ensuring the acquisition time remains unchanged.

[0069] As can be seen from the above, a fast acquisition method for low signal-to-noise ratio and large dynamic short message signals of the present invention proposes a new and efficient acquisition architecture based on multi-level data caching, and realizes the fast acquisition of low signal-to-noise ratio and large dynamic short message signals through step-by-step caching. The acquisition architecture is flexible and can adapt to the acquisition of short message signals under different signal-to-noise ratios and Doppler frequency offsets by changing parameters. While ensuring fast acquisition, it effectively reduces the resources occupied by the acquisition algorithm. This method has stable performance and can be widely applied to the field of burst spread spectrum measurement and control.

[0070] During the development of a certain project, after applying the method proposed by the present invention, short message signals with large Doppler dynamics (-100 kHz to 100 kHz) and low signal-to-noise ratio (received carrier-to-noise ratio less than 42 dBHz) can be captured, and rapid capture can be completed within 40 ms.

[0071] The content not described in detail in the specification of the present invention belongs to the well-known technology of those skilled in the art.

Claims

1. A fast acquisition method for low signal-to-noise ratio and large dynamic short message signals, characterized in that The steps are as follows: (1) Perform orthogonal down-conversion on the data after AD sampling, and move the data from the intermediate frequency to the baseband; (2) Accumulate and decelerate the data after down-conversion; (3) Delay the data after accumulation and deceleration by m*k times, generate m*k data and store them successively in the same address of buffer RAM1. Write one data per clock cycle. When reading, read out the m*k data corresponding to a certain address in RAM1 at one time, and convert the data after accumulation and deceleration from serial to parallel processing; (4) Divide the frequency range according to the Doppler range and signal-to-noise ratio, and correct the local pseudo-code rate according to the center frequency point of each frequency range; (5) Let the initial values of both i and j be 1; (6) At the i-th code phase, read out the m*k data in one address of RAM1 and the m*k chips in the corresponding address of RAM2 in each clock cycle, multiply the data and the chips correspondingly to achieve parallel despreading. Divide the m*k despreading results obtained in the same clock cycle into k groups, with m despreading results in each group. Perform parallel accumulation on the m despreading results to obtain k groups of accumulation results; (7) Perform orthogonal up-conversion on the data after despreading and accumulation using the center frequency point of the j-th frequency range, and divide the accumulation results after orthogonal up-conversion for all clock cycles at the current code phase into intervals; (8) Use two storage areas to perform ping-pong caching on the data after dividing the intervals. When one storage area is in the write state, the other is in the read state; (9) After the data storage is completed, call a pipelined FFT core to perform FFT operation. When the local pseudo-code phase is aligned with the data after AD sampling in step (1), the peak position of the FFT spectrum is the Doppler frequency offset; (10) Judge whether i is equal to I, where I is the total number of code phases. If not, slide one code phase, that is, increment the value of i by 1, and execute steps (6)-(9). Sliding the code phase is achieved by changing the initial read address of RAM2. If equal, enter step (11); (11) Judge whether j is equal to J, where J is the total number of frequency ranges. If not, increment the value of j by 1, and set i = 1, and execute steps (6)-(10). If equal, enter step (12); (12) If the peak value of the FFT spectrum is greater than the preset threshold, it is judged as successful capture, and start the tracking module. If the peak value of the FFT spectrum is less than the preset threshold, it is judged as failed capture, and return to step (1) to start the capture again.

2. The rapid capture method of a low signal-to-noise ratio and large dynamic short message signal according to claim 1, wherein In step (2), if the global clock is clk, the data rate after accumulation and deceleration is clk / N, where N is the number of accumulation points.

3. A fast acquisition method for low signal-to-noise ratio and large dynamic short message signals according to claim 2, characterized in that In the step (3), the depth D of the buffer RAM1 e is with a width of m*k, N being the number of accumulation points, and R being the accumulation data rate.

4. A fast acquisition method for a low signal-to-noise ratio and large dynamic short message signal according to claim 1, characterized in that In the step (4), the radio frequency is F s , the pseudo-code rate is f c , the Doppler frequency range is -f d ~f d , the capture operation cumulative time is 1 / R, and the minimum number of frequency interval J is R is the cumulative data rate; the center frequency of the frequency interval is f q , then the corrected pseudo-code rate is 5. A fast acquisition method for a low signal-to-noise ratio and large dynamic short message signal according to claim 4, characterized in that, The sampling rate of the local pseudo-code is the same as the data rate after accumulation and deceleration, which is clk / N, where clk is the global clock and N is the number of accumulation points.

6. A fast acquisition method for low signal-to-noise ratio and large dynamic short message signals according to claim 5, characterized in that, The depth of the pseudo-code storage space is where f c is the pseudo-code rate, H is the pseudo-code period, and R is the accumulated data rate.

7. A fast acquisition method for low signal-to-noise ratio and large dynamic short message signals according to claim 1, characterized in that In step (8), the storage depth of one storage area is D / k, where D is the number of FFT operation points.

8. A fast acquisition method for a low signal-to-noise ratio and large dynamic short message signal according to claim 7, characterized in that D = R a / R, R a is the data rate after despreading and accumulation in step (5), and R is the accumulated data rate in step (3).

9. The rapid capture method of a low signal-to-noise ratio and large dynamic short message signal according to claim 1, characterized in that In step (9), call a pipelined FFT core to perform high-speed FFT operation using k times the global clock; 10. A fast acquisition method for low signal-to-noise ratio and large dynamic short message signals according to claim 1, characterized in that, Capture time = data caching time + capture operation time; Among them, R is the cumulative data rate, f c is the pseudocode rate, and H is the pseudocode period; If the sliding accuracy of the pseudo-code phase is 1 / t chips during capture, the time for one round of capture operation in each frequency interval is clock cycles, and the capture time required for J serially searched frequency intervals is clock cycles, where D is the number of FFT operation points.

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