Communication circuit, communication method, storage unit built-in self-test system

Abstract

The present invention discloses a communication circuit, a communication method, and a memory built-in self-test system. The communication circuit includes: a communication client, a communication server, a first signal line and a second signal line connecting the communication client and the communication server; the communication client has different states and sends a status signal to the communication server through the first signal line; the communication server sends a corresponding pulse signal through the second signal line when the communication client is in the corresponding state according to a preset communication protocol, triggering the communication client to switch to different states. The present invention has a simple structure, low dynamic power consumption, high working frequency, and stable and reliable communication control.

Description

Technical Field

[0001] The present invention relates to the technical field of communication technologies between modules of digital circuits, and particularly to a new communication circuit and a corresponding communication method. Background Art

[0002] Communication circuits in the prior art are basically used for data transmission.

[0003] A prior patent with publication number US5199105A discloses a universal asynchronous receiver / transmitter, and the communication protocol involved therein is also used for data transmission.

[0004] However, in practical applications, generally, a communication client may have multiple different control modes (operating modes), and the communication server needs to know the operating mode of the communication client to perform specific control and / or configuration on it. The technical solutions disclosed in the above prior patents cannot solve this problem.

[0005] In other prior arts, in order to perform control based on states, generally, the implementation circuits and / or communication protocols are very complex. Therefore, a simple and efficient communication circuit and a corresponding communication method are needed to solve this technical problem. Summary of the Invention

[0006] In order to solve the technical problem that communication circuits for state-based control in the prior art are very complex, the present invention provides a communication circuit, a communication method, and a built-in self-test system for a storage unit.

[0007] The communication circuit provided by the present invention includes: a communication client, a communication server, a first signal line and a second signal line connecting the communication client and the communication server;

[0008] The communication client has different states and sends a state signal to the communication server through the first signal line;

[0009] When the communication client is in a corresponding state, the communication server sends a corresponding pulse signal through the second signal line according to a preset communication protocol to trigger the communication client to switch to different states.

[0010] Furthermore, the communication server and the communication client operate based on the same clock frequency, or the communication server and the communication client operate based on different clock frequencies, and the clock frequency of the communication client is higher than that of the communication server.

[0011] Further, the states of the communication client include an idle state and a working state. When the communication client is in the idle state, the communication server sends a pulse signal according to a preset communication protocol to trigger the communication client to switch to the working state. When the communication server receives that the communication client is in the working state, it stops sending the pulse signal and waits for the next sending.

[0012] Further, the communication server includes: a signal receiving module for receiving a preparation signal and the state signal of the communication client, and a pulse signal generating module for generating a pulse signal.

[0013] Further, the signal receiving module includes a first NAND gate and a first inverter, and the pulse signal generating module includes a first NOR gate, a first D flip-flop, and a second D flip-flop; one of the two input terminals of the first NAND gate is connected to the preparation signal, and the first signal line is connected to the other input terminal through the first inverter; the output terminal of the first NAND gate is connected to one input terminal of the first NOR gate, the other input terminal of the first NOR gate is connected to the output terminal of the first D flip-flop, and the output terminal of the first NOR gate is connected to the input terminal of the first D flip-flop; the output terminal of the first D flip-flop is simultaneously connected to the input terminal of the second D flip-flop, and the output terminal of the second D flip-flop generates the pulse signal. The first and second D flip-flops are connected to the same clock signal, but the triggering edges are opposite. For example, if it is default that the first D flip-flop is triggered by the rising edge of the clock, then the second D flip-flop is triggered by the falling edge of the clock.

[0014] Further, the communication client includes: a shift register group for delaying, a pulse detection module for receiving the pulse signal, and a latch module for latching the state of the communication client.

[0015] Further, the pulse detection module includes a third D flip-flop, a first exclusive-OR gate, a first AND gate, a second NOR gate, and a third NOR gate; the latch module includes a fourth D flip-flop and a fifth D flip-flop; the output of the shift register group serves as the input of the third flip-flop and one input of the first exclusive-OR gate; the output of the third flip-flop serves as the other input of the first exclusive-OR gate; the output of the third flip-flop and the output of the first exclusive-OR gate respectively serve as the two inputs of the first AND gate, the output of the first AND gate and the output of the fifth D flip-flop respectively serve as the two inputs of the second NOR gate, the output of the second NOR gate and the work completion signal serve as the two inputs of the third NOR gate, and the output of the third NOR gate serves as the input of the fourth D flip-flop and the fifth D flip-flop at the same time. The fourth and fifth D flip-flops are triggered using opposite edges.

[0016] The communication method based on the above communication circuit according to the present invention includes:

[0017] An external device connected to the communication server sends a control signal to set the clock enable signal high, and the communication server and the communication client are selected and enabled;

[0018] The communication circuit performs an initialization and reset operation, and the initial state of the communication client is the idle state;

[0019] After the external device sends a ready signal to the communication server, the communication server starts to send corresponding pulse signals to the communication client;

[0020] After receiving the pulse signal, the communication client starts to work and switches its state to the working state.

[0021] The built-in self-test system of the storage unit of the present invention includes a self-test controller and at least one storage unit to be tested, and the self-test controller and the storage unit to be tested are connected through the communication circuit described in the above technical solution.

[0022] The present invention can achieve that, except for the clock signal line, the status identification and control channels of the communication circuit only use two unidirectional transmission wires, which can very likely avoid introducing layout and routing congestion problems in the back-end design of digital chips. In addition, the present invention realizes a simple and efficient control signal protocol, and its signal average transition rate is very low and it is in a steady state during a long working period. On the one hand, it is beneficial to reduce dynamic power consumption, and on the other hand, it helps to achieve high-frequency transmission. In the edge-sensitive signal recognition, a multi-edge recognition working mode is adopted instead of single-edge recognition, which further improves the robustness of communication.

[0023] The structure of the present invention is simple, efficient and practical, friendly to layout and routing, and suitable for area-sensitive designs.

[0024] The present invention has low dynamic power consumption, high working frequency, and stable and reliable communication control. The present invention does not limit the data transmission mode, has a certain design compatibility, and is highly flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention will be described in detail below in conjunction with embodiments and drawings, wherein:

[0026] Figure 1 is the circuit structure diagram of the communication server according to an embodiment of the present invention.

[0027] Figure 2 is the circuit structure diagram of the communication client according to an embodiment of the present invention.

[0028] Figure 3 is the schematic diagram of an application embodiment of the present invention.

[0029] Figure 4 is the signal timing diagram of the communication protocol according to an embodiment of the present invention.

[0030] Figure 5 It is the working timing diagram of the client pulse detection module according to an embodiment of the present invention.

[0031] Figure 6 It is the communication circuit and test clock timing diagram according to an embodiment of the present invention. Detailed implementation manners

[0032] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0033] Therefore, a feature pointed out in this specification will be used to illustrate one of the features of one embodiment of the present invention, rather than implying that each embodiment of the present invention must have the illustrated feature. In addition, it should be noted that this specification describes many features. Although some features may be combined together to show possible system designs, these features can also be used in other combinations that are not explicitly described. Therefore, unless otherwise stated, the illustrated combinations are not intended to be limiting.

[0034] The communication circuit of the present invention includes a communication client, a communication server, a first signal line and a second signal line connecting the communication client and the communication server.

[0035] The communication client of the present invention has different states, and it sends status signals to the communication server through the first signal line. For example, in one embodiment, the communication client has an idle state and a working state.

[0036] The communication server sends corresponding pulse signals through the second signal line when the communication client is in the corresponding state according to the preset communication protocol, triggering the communication client to switch to different states.

[0037] Taking the communication client having an idle state and a working state as an example, the specific rules of the preset communication protocol are as follows: when the communication client is in the idle state, the communication server can, under the trigger of a corresponding signal (such as receiving an internal control instruction or receiving an external trigger signal), send a corresponding pulse signal to trigger the communication client to switch to the working state. When the communication server receives that the communication client is in the working state, it stops sending the corresponding pulse signal and waits for the next sending.

[0038] In one embodiment, the communication server and the communication client of the present invention can work synchronously, that is, work based on the same clock frequency.

[0039] In another embodiment, the communication server and the communication client of the present invention can work asynchronously, that is, the communication server and the communication client work based on different clock frequencies, and the clock frequency of the communication client is higher than that of the communication server.

[0040] The communication server includes: a signal receiving module for receiving a preparation signal and a status signal of the communication client, and a pulse signal generating module for generating a pulse signal.

[0041] Figure 1 A specific implementation circuit diagram of the communication server is shown. The signal receiving module of the communication server includes a first NAND gate and a first inverter. The pulse signal generating module of the communication server includes a first NOR gate, a first D flip-flop, and a second D flip-flop. One of the two input terminals of the first NAND gate is connected to the preparation signal, and the first signal line is connected to the other input terminal through the first inverter; the output terminal of the first NAND gate is connected to one input terminal of the first NOR gate, the other input terminal of the first NOR gate is connected to the output terminal of the first D flip-flop, and the output terminal of the first NOR gate is connected to the input terminal of the first D flip-flop; the output terminal of the first D flip-flop is simultaneously connected to the input terminal of the second D flip-flop, and the output terminal of the second D flip-flop generates a corresponding pulse signal. The first and second D flip-flops are connected to the same clock signal, but the triggering edges are opposite.

[0042] In one embodiment, when the communication server sends a communication signal to the communication client, the status signal (idle signal) of the communication client is at a low level, and the preparation signal (ready signal) is at a high level. The communication server continuously generates a corresponding pulse signal (such as an update signal) from the output terminal of the second D flip-flop through two D flip-flops. When the idle signal of the communication client is received as a high level, the output of the first flip-flop 402 remains 0, so the first flip-flop 401 stops generating the output of the pulse signal, and the communication server stops sending the corresponding pulse signal.

[0043] In one embodiment, it can be defaulted that the rising edge is valid.

[0044] The communication client includes: a shift register group for delaying, a pulse detection module for receiving a pulse signal, and a latch module for latching the status of the communication client.

[0045] The pulse detection module of the communication client includes a third D flip-flop, a first exclusive-OR gate, a first AND gate, a second NOR gate, and a third NOR gate; the latch module of the communication client includes a fourth D flip-flop and a fifth D flip-flop.

[0046] The output of the shift register bank serves as the input to the third flip-flop and one input of the first exclusive-OR gate; the output of the third flip-flop serves as the other input of the first exclusive-OR gate; the output of the third flip-flop and the output of the first exclusive-OR gate respectively serve as the two inputs of the first AND gate, the output of the first AND gate and the output of the fifth D flip-flop respectively serve as the two inputs of the second NOR gate, the output of the second NOR gate and the work completion signal serve as the two inputs of the third NOR gate, and the output of the third NOR gate serves as the input to both the fourth D flip-flop and the fifth D flip-flop simultaneously. The fourth and fifth D flip-flops are triggered on opposite edges.

[0047] Figure 2 Fig. shows a specific embodiment of the communication client of the present invention. For the client, the shift register bank 501 delays the detection of the corresponding pulse signal (such as the update signal). The pulse detection module is configurable. By setting the number of bits of different shift registers, it is possible to adjust after which pulse signal the pulse detection module detects the corresponding pulse signal. Taking the update signal as an example, when a negative edge is generated by the update signal, after a specific clock cycle, the pulse detection module will generate a high-level signal and latch it in two registers, namely, latch it in the fourth D flip-flop and the fifth D flip-flop. At this time, the communication client outputs a high-level signal, that is, both idle_p1 and idle_n2 are high level. idle_p1 indicates that the high level takes effect on the rising edge of the clock, and idle_n2 indicates that the high level takes effect on the falling edge of the clock. Until the completion signal (done signal) of the second functional logic module is received, the two registers are unlocked and the output of the client resumes to a low-level signal. According to actual needs, either the idle_p1 or idle_n2 signal can be freely selected as the identification signal of the first signal line (idle).

[0048] Figure 3 Fig. shows a specific application embodiment of the present invention. In this embodiment, the first functional logic module 105 and the second functional logic module 106 are connected through the above communication circuit. The communication server is connected to the first functional logic module 105, and the communication client is connected to the second functional logic module 106.

[0049] The communication server receives the ready signal (ready signal) from the first functional logic module 105 and transmits an update pulse signal (update signal) to the communication client through the update signal line connected to the communication client. The communication client receives the update pulse signal (update signal) from the communication server and the completion signal (done signal) of the second functional logic module 106.

[0050] In this embodiment, the communication server and the communication client complete the response communication only through two signal lines for sending the update signal and the idle (busy / idle flag). When the status signal (idle signal) is at a low level, it indicates that the communication client is in an idle state. When the status signal (idle signal) is at a high level, it indicates that the communication client is in a working state. In the working state, the communication server cannot initiate the corresponding pulse signal.

[0051] When the first functional logic module 105 is ready, it sends a ready signal (ready signal) to notify the communication server 101 to send the corresponding pulse signal to the communication client 102. The communication client receives the corresponding pulse signal sent by the communication server, triggering the second functional logic module 106 to perform the corresponding configuration work. At the same time, the idle signal is pulled high to enter the working state, and the communication server stops sending the corresponding pulse signal to the communication client and notifies the first functional logic module 105 to start preparing the next configuration information. After the second functional logic module 106 completes the current configuration operation, it notifies the communication client 102 to send an identification signal to the communication server 101, that is, to pull down the level of the idle line (the first signal line). The communication server 101 sends a signal to the first functional logic module 105. After the first functional logic module 105 is ready, it will notify the communication server, and the communication server will send the next pulse signal. The first functional logic module 105 and the second functional logic module 106 perform the next communication according to the above process.

[0052] In addition to the clock signal (clk signal), the reset signal (rst signal), the clock enable signal (ce signal), the communication server 101 receives the ready signal and the idle signal from the communication client. The communication server 101 also sends the update signal to the communication client through the pulse generation module 103. In addition to the clock signal, the reset signal, and the clock enable signal, the communication client 102 receives the done signal, detects the update pulse signal from the communication server through the pulse detection module 104, and sends the idle signal to the communication server and the outside (the second functional logic module 106).

[0053] The communication method of the communication circuit of the above technical solution includes the following steps.

[0054] The external device connected to the communication server sends a control signal to set the clock enable signal high, and the communication server and the communication client are selected and enabled;

[0055] Perform an initialization reset operation on the communication circuit, and the initial state of the communication client is the idle state;

[0056] After the external device sends a ready signal to the communication server, the communication server starts to send the corresponding pulse signal to the communication client;

[0057] After receiving the pulse signal, the communication client starts to work and switches its state to the working state.

[0058] The following is based on Figures 4 to 6 Describe in detail the specific communication process of the communication protocol of the present invention.

[0059] Preparation stage 201 of the communication server: The first functional logic module 105 sends a control signal to set the clock enable signal high, and the communication server and the communication client are selected, that is, at this time the ce signal is high level (ce is used to control the clock signal, and when the ce signal is low level, the communication server and the communication client do not work). Then, an initialization reset operation is performed on the communication server and the communication client. The reset signal (rst signal) for initialization is generated at the falling edge of the clock (clk), and the clock enable signal (ce signal) takes effect at the falling edge of the clock. After the first functional logic module 105 sends the ready signal to the communication server 101, the communication server starts to work and enters the next stage.

[0060] Configuration signal sending stage 202 of the communication server: The ready signal is generated at the falling edge of the clock. After the communication server receives the ready signal, it actively communicates with the communication client. At the next falling edge of the clock after the ready signal is generated, the communication server starts to continuously send the update signal to the communication client. The update signal is generated at the falling edge of the clock. Until the idle signal sent by the communication client is at high level, in order to reduce the power consumption of the communication circuit, the pulse signal sending is stopped, and the communication server enters the waiting stage 203.

[0061] Configuration stage 204 of the communication client: When the update signal is generated, the second functional logic module 106 loads the corresponding configuration information. For example, when the second functional logic module is the storage unit to be tested, the configuration information on the data bus connected to the storage unit to be tested can be loaded to prepare for the next operation.

[0062] Configuration stage 205 of the second functional logic module: The configuration signal (Config signal) of the second functional logic module 106 remains high level and will become low level after the configuration is completed.

[0063] Working stage 206 of the communication client: The pulse detection module samples the pulse signal (such as the update signal) at the rising edge of the clock and detects the falling edge of the pulse signal at the falling edge of the clock. After detecting the falling edge of the pulse signal, the communication client sets the idle signal to high level and enters the working state. The pulse detection module stops detecting the pulse signal. During the working stage of the communication client, the working signal (work signal) of the second functional logic module 106 is also at high level. The work signal is an identification signal of the second functional logic module 106 and can also be replaced by the idle signal. After the current operation is completed, the work signal is pulled low and enters the idle state.

[0064] End stage 207 of the communication client: After the communication client 102 receives the work completion identification done signal from the second functional logic module 106, it pulls the idle signal low, indicating that the current client state returns to the idle state. The pulse detector starts listening to detect the pulse signal from the communication server, ending this communication. Enter the next communication stage 208.

[0065] The communication client detects the update signal from the communication server through the pulse detection module. Samples the update signal at the rising edge of the clock through a D-type flip-flop. If a valid update signal is detected, the communication client will generate high-level busy / idle identification signals at the rising and falling edges of the clock respectively. The idle signal corresponding to the trigger edge can be selected according to the application scenario.

[0066] The communication protocol of the present invention can support the asynchronous working mode, that is, the communication client and the communication server can work at different clock frequencies. It should be noted that when working asynchronously, the working clock frequency of the communication client must be faster than that of the communication server, otherwise the communication client cannot detect the update signal, resulting in the abnormal operation of the communication circuit.

[0067] A lightweight circuit module design implemented by the present invention through the above technical solutions. For example, it can be used in the design of digital functional modules that are extremely sensitive to the chip area occupied. A specific application scenario example is the MBIST (memory built-in self-test) module used to implement the DFT function in digital circuits. Adopting the server-client mode to connect the controller of MBIST and each memory unit under test. In particular, it can achieve the control and connection of a single controller to multiple memory units.

[0068] The memory built-in self-test system of the present invention includes a self-test controller and at least one memory unit under test. The self-test controller and the memory unit under test are connected through the communication circuit of the above technical solution.

[0069] Although the present invention defines the behavior patterns and state interpretations of its control signals and divides various working states based on this, it does not stipulate or limit the channel bandwidth, transmission mode, etc. of data communication. Therefore, this control protocol can be combined with existing data communication protocols. Minor modifications may be required during the combination process, but it provides great flexibility to adapt to more complex and variable application scenarios.

[0070] In practical applications, this control protocol can be combined with common data communication protocols, such as UART (Universal Asynchronous Receiver / Transmitter) or SPI (Serial Peripheral Interface), etc. The data communication protocol is set in the working stage of this control protocol (see the detailed description). If the data communication volume in the application scenario is very small, for example, when applied to the configuration control of the MBIST system, it is more applicable. The configuration signal or data is only enabled for control configuration or data transmission when both functional modules are ready.

[0071] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A communication circuit, characterized in that, Comprising: A communication client, a communication server, a first signal line and a second signal line connecting the communication client and the communication server; The communication client has different states and sends a status signal to the communication server through the first signal line; The communication server includes: a signal receiving module for receiving a preparation signal and the status signal of the communication client, and a pulse signal generating module for generating a pulse signal; The signal receiving module includes a first NAND gate and a first inverter; the pulse signal generating module includes a first NOR gate, a first D flip-flop and a second D flip-flop; One of the two input terminals of the first NAND gate is connected to the preparation signal, and the first signal line is connected to the other input terminal through the first inverter; the output terminal of the first NAND gate is connected to one input terminal of the first NOR gate, the other input terminal of the first NOR gate is connected to the output terminal of the first D flip-flop, and the output terminal of the first NOR gate is connected to the input terminal of the first D flip-flop; the output terminal of the first D flip-flop is simultaneously connected to the input terminal of the second D flip-flop, and the output terminal of the second D flip-flop generates the pulse signal. The first and second D flip-flops are connected to the same clock signal, but the triggering edges are opposite; The communication server sends a corresponding pulse signal through the second signal line according to a preset communication protocol when the communication client is in a corresponding state, triggering the communication client to switch to different states.

2. The communication circuit according to claim 1, characterized in that, The communication server and the communication client operate based on the same clock frequency, or the communication server and the communication client operate based on different clock frequencies, and the clock frequency of the communication client is higher than the clock frequency of the communication server.

3. The communication circuit according to claim 1, characterized in that, The states of the communication client include an idle state and a working state. The communication server sends a pulse signal to trigger the communication client to switch to the working state according to a preset communication protocol when the communication client is in the idle state. When the communication server receives that the communication client is in the working state, it stops sending the pulse signal and waits for the next sending.

4. The communication circuit according to any one of claims 1 to 3, characterized in that, The communication client includes: a shift register group for delaying, a pulse detection module for receiving the pulse signal, and a latch module for latching the state of the communication client.

5. The communication circuit according to claim 4, characterized in that, The pulse detection module includes a third D flip-flop, a first exclusive-OR gate, a first AND gate, a second NOR gate and a third NOR gate; the latch module includes a fourth D flip-flop and a fifth D flip-flop; The output of the shift register group serves as the input of the third flip-flop and one input of the first exclusive-OR gate; the output of the third flip-flop serves as the other input of the first exclusive-OR gate; the output of the third flip-flop and the output of the first exclusive-OR gate respectively serve as the two inputs of the first AND gate, the output of the first AND gate and the output of the fifth D flip-flop respectively serve as the two inputs of the second NOR gate, the output of the second NOR gate and the work completion signal serve as the two inputs of the third NOR gate, and the output of the third NOR gate serves as the input of the fourth D flip-flop and the fifth D flip-flop at the same time. The fourth and fifth D flip-flops are triggered using opposite edges.

6. A communication method based on the communication circuit according to any one of claims 1 to 5, characterized in that, Comprising: An external device connected to the communication server sends a control signal to set the clock enable signal high, and the communication server and the communication client are selected and enabled; Perform an initialization reset operation on the communication circuit, and the initial state of the communication client is the idle state; After the external device sends a ready signal to the communication server, the communication server starts to send corresponding pulse signals to the communication client; The communication client starts to work after receiving the pulse signal and switches its state to the working state.

7. A memory built-in self-test system, including a self-test controller and at least one memory under test, characterized in that, The self-test controller and the storage unit under test are connected through the communication circuit according to any one of claims 1 to 5.

Images