Imaging element and imaging device

Abstract

Provided is an imaging element and an imaging apparatus. The imaging element includes: a first semiconductor layer provided with a plurality of pixels, the plurality of pixels each having a photoelectric conversion section that generates electric charges by photoelectrically converting light, and a reset section that resets the electric charges generated by the photoelectric conversion section; and a second semiconductor layer provided with a supply section that supplies a signal for resetting the electric charges generated by the photoelectric conversion section to the reset section.

Description

[0001] This application is filed in division based on the application for invention with international application date of September 27, 2016, international application number of PCT / JP2016 / 078522, entering the national application number of 201680056712.2 in China (the application number of the first divisional application is 202010656402.2). TECHNICAL FIELD

[0002] The present application relates to an imaging device and an electronic camera (electronic camera head). BACKGROUND

[0003] At present, there is known an imaging device in which a chip in which pixels are formed and a chip in which a pixel drive circuit that drives the pixels are stacked (for example, Patent Literature 1). In the conventional imaging device, there is a problem that two power supplies must be provided to each pixel in order to control the exposure amount for each pixel.

[0004] PRIOR ART DOCUMENT

[0005] PATENT LITERATURE

[0006] Patent Literature 1: Japanese Patent Application Laid-Open No. 2010-225927 SUMMARY

[0007] According to a first aspect, an imaging device includes: a first semiconductor layer provided with a plurality of pixels, the pixels each having a photoelectric conversion section that photoelectrically converts incident light, an accumulation section that accumulates electric charges generated by the photoelectric conversion section, and a transfer section that transfers the electric charges generated by the photoelectric conversion section to the accumulation section; a second semiconductor layer provided with a supply section for each of the plurality of pixels, the supply section supplying a transfer signal for transferring the electric charges from the photoelectric conversion section to the accumulation section to the transfer section; and a third semiconductor layer that inputs a signal based on the electric charges transferred to the accumulation section.

[0008] According to a second aspect, an imaging device includes: a first semiconductor substrate provided with a plurality of pixels, the pixels each having a photoelectric conversion section that photoelectrically converts incident light, an accumulation section that accumulates electric charges generated by the photoelectric conversion section, and a transfer section that transfers the electric charges generated by the photoelectric conversion section to the accumulation section; and a semiconductor layer that is stacked on the first semiconductor substrate and is provided with a supply section for each of the plurality of pixels, the supply section supplying a transfer signal for transferring the electric charges from the photoelectric conversion section to the accumulation section to the transfer section.

[0009] According to a third aspect, the image pickup element includes: a first semiconductor substrate formed with an insulating portion and provided with a prescribed substrate voltage; a photoelectric conversion portion provided in the first semiconductor substrate and photoelectrically converting incident light; a transfer portion provided in the first semiconductor substrate and transferring electric charges obtained by the photoelectric conversion by the photoelectric conversion portion to an accumulation portion based on a transfer signal; and a supply portion supplying the transfer signal including a first signal voltage as a positive voltage and a second signal voltage as a negative voltage to the transfer portion and electrically insulated from the first semiconductor substrate by the insulating portion. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a cross-sectional view schematically showing a configuration of an imaging device.

[0011] Figure 2 is a cross-sectional view of an image pickup element.

[0012] Figure 3 is a block diagram schematically showing a configuration of a pixel.

[0013] Figure 4 is a circuit diagram of an analog circuit portion and a pixel drive portion.

[0014] Figure 5 is a diagram schematically showing a well configuration of a first semiconductor substrate and a second semiconductor substrate.

[0015] Figure 6 is a time chart showing a photographing timing using the image pickup element.

[0016] Figure 7 is a circuit diagram of a transfer signal supply portion.

[0017] Figure 8 is a plan view of the transfer signal supply portion.

[0018] Figure 9 is a diagram schematically showing a cross section of the transfer signal supply portion.

[0019] In the drawings, the following signs are used:

[0020] 3 image pickup element, 7 first semiconductor substrate, 8 second semiconductor substrate, 9 insulating portion,

[0021] 30 pixel, 31 photodiode, 301 analog circuit portion, 302 A / D conversion portion, 303 sampling portion, 306 individual pixel control portion, 307 pixel drive portion DETAILED DESCRIPTION

[0022] (First Embodiment)

[0023] Figure 1is a cross-sectional view schematically showing a configuration of a photographing apparatus using the imaging element of the first embodiment. The photographing apparatus 1 includes an imaging optical system 2, an imaging element 3, a control section 4, a lens driving section 5, and a display section 6.

[0024] The imaging optical system 2 images an object image on a photographing surface of the imaging element 3. The imaging optical system 2 is composed of a lens 2a, a focus lens 2b, and a lens 2c. The focus lens 2b is a lens for adjusting a focus of the imaging optical system 2. The focus lens 2b is configured to be driven in the direction of the optical axis O.

[0025] The lens driving section 5 has an actuator not shown. The lens driving section 5 drives the focus lens 2b in the direction of the optical axis O by the actuator only by a desired amount. The imaging element 3 photographs an object image and outputs an image. The control section 4 controls each section of the imaging element 3 and the like. The control section 4 performs image processing and the like on an image signal output by the imaging element 3, and records the image on a recording medium not shown, or displays the image on the display section 6. The display section 6 is a display apparatus having a display member such as a liquid crystal panel.

[0026] Figure 2 is a cross-sectional view of the imaging element 3. In Figure 2 , only a cross section of a part of the entire imaging element 3 is shown. The imaging element 3 is a so-called back-illuminated type imaging element. The imaging element 3 photoelectrically converts incident light from the paper surface direction. The imaging element 3 includes a first semiconductor substrate 7, a second semiconductor substrate 8, and an insulating section 9. Hereinafter, the first semiconductor substrate 7 and the second semiconductor substrate 8 are sometimes referred to as a first semiconductor layer and a second semiconductor layer, respectively.

[0027] The first semiconductor substrate 7 is a part of an SOI (Silicon on Insulator) substrate. The SOI substrate is a silicon substrate in which an insulating film is buried inside. The first semiconductor substrate 7 is one of two silicon layers insulated (isolated) by the buried insulating film, which the SOI substrate has. The insulating section 9 is a layer provided between the first semiconductor substrate 7 and the second semiconductor substrate 8. The insulating section 9 includes the buried insulating film and the other of the two silicon layers (a silicon layer not belonging to the first semiconductor substrate 7), which the SOI substrate has. That is, the SOI substrate includes a silicon substrate, a buried oxide film layer, and a silicon layer.

[0028] The first semiconductor substrate 7 has a photodiode 31 that is a buried photodiode, and transfer transistors and reset transistors. Therefore, the surface of the first semiconductor substrate 7 on the side of the insulating portion 9 (i.e., the surface on the side opposite to the incident side of the incident light) is of a conduction type opposite to that of the first semiconductor substrate 7. For example, if the first semiconductor substrate 7 is an N-type semiconductor layer, a P-type semiconductor layer having a high concentration and a small thickness is provided on the surface on the side of the insulating portion 9. A ground voltage (GND) is applied to the first semiconductor substrate 7 as a substrate voltage. The photodiode 31 is provided on the light incident surface side of the first semiconductor substrate 7, and the transfer transistors and the reset transistors are provided on the surface on the side of the second semiconductor substrate 8.

[0029] The second semiconductor substrate 8 has, among various circuits for reading a signal from the photodiode 31, circuits that operate at a voltage higher than the substrate voltage of the first semiconductor substrate 7. Specifically, the second semiconductor substrate 8 has, among the A / D conversion portion 302, the sampling portion 303, the pixel value holding portion 304, the operation portion 305, and the individual pixel control portion 306, and a part of the pixel drive portion 307 (i.e., the circuits that operate at a voltage higher than the substrate voltage of the first semiconductor substrate 7, namely, the first reset signal supply portion 307b and the expanded capacity signal supply portion 307d) described below. A ground voltage (GND) is applied to the second semiconductor substrate 8 as a substrate voltage.

[0030] The insulating portion 9 has, among various circuits for reading a signal from the photodiode 31, circuits that process a negative voltage. Specifically, the insulating portion 9 has, among the pixel drive portion 307 described below, a part that processes a transfer signal supply portion 307a and a second reset signal supply portion 307c that process a voltage lower than the substrate voltage of the first semiconductor substrate 7.

[0031] A plurality of photodiodes 31 are two-dimensionally arranged on the first semiconductor substrate 7. A plurality of color filters 73 corresponding to the plurality of photodiodes 31 are provided on the incident side of the incident light in the first semiconductor substrate 7. The color filters 73 are, for example, of a plurality of types that transmit wavelength regions corresponding to red (R), green (G), and blue (B). The color filters 73 are, for example, arranged in a Bayer array of three color filters corresponding to red (R), green (G), and blue (B).

[0032] A plurality of microlenses 74 corresponding to the plurality of color filters 73 are provided on the incident side of the incident light of the color filters 73. The microlenses 74 condense the incident light toward the corresponding photodiodes 31. The incident light that has passed through the microlenses 74 is filtered by the color filters 73 only for a part of the wavelength regions, and is incident on the photodiodes 31. The photodiodes 31 photoelectrically convert the incident light and generate electric charges.

[0033] A plurality of bumps 75 are arranged on the surface of the insulating portion 9 opposite the second semiconductor substrate 8. A plurality of bumps 76 corresponding to the plurality of bumps 75 are arranged on the surface of the second semiconductor substrate 8 opposite the insulating portion 9. The plurality of bumps 75 and the plurality of bumps 76 engage with each other. The insulating portion 9 and the second semiconductor substrate 8 are electrically connected via the plurality of bumps 75 and the plurality of bumps 76.

[0034] The imaging device 3 has a plurality of pixels 30, the details of which will be described later. One pixel 30 includes a first pixel 30x provided on the first semiconductor substrate 7, a second pixel 30y provided on the second semiconductor substrate 8, and a third pixel 30z provided on the insulating portion 9. In one first pixel 30x, a microlens 74, a color filter 73, a photodiode 31, and the like are included. In the first pixel 30x, various circuits (described below) provided on the first semiconductor substrate 7 are further included. In the second pixel 30y, various circuits (described below) provided on the second semiconductor substrate 8 are included. In the third pixel 30z, various circuits (described below) provided on the insulating portion 9 are included.

[0035] Figure 3 is a block diagram schematically showing the structure of the pixel 30. The pixel 30 includes an analog circuit portion 301, an A / D conversion portion 302, a sampling portion 303, a pixel value holding portion 304, a pixel drive portion 307, an individual pixel control portion 306, and an arithmetic portion 305.

[0036] The analog circuit portion 301 outputs, as an analog signal, a result of photoelectric conversion of incident light to the A / D conversion portion 302. The A / D conversion portion 302 samples the analog signal output from the analog circuit portion 301 and outputs a digital signal to which a prescribed gain is applied. The A / D conversion portion 302 repeatedly samples the pixel reset signal and the pixel signal and individually outputs the results of sampling of the pixel reset signal and the pixel signal as digital signals.

[0037] The sampling portion 303 calculates and holds the integral value of the results of sampling of the pixel reset signal and the pixel signal. The sampling portion 303 includes a first adder 308 and a first memory 309 for the pixel reset signal and a second adder 310 and a second memory 311 for the pixel signal.

[0038] The sampling portion 303 performs an addition operation on the integral value of the result of sampling of the pixel reset signal output from the A / D conversion portion 302 and the past result of sampling held in the first memory 309 by the first adder 308. The sampling portion 303 stores the result of the addition operation in the first memory 309. The sampling portion 303 updates the value stored in the first memory 309 each time the result of sampling of the pixel reset signal is output from the A / D conversion portion 302.

[0039] The sampling section 303 adds the sampling result of the pixel signal output by the A / D conversion section 302 and the integrated value of the past sampling result held in the second memory 311 by the second adder 310. The sampling section 303 stores the addition result in the second memory 311. The sampling section 303 updates the value stored in the second memory 311 each time the sampling result of the pixel signal is output by the A / D conversion section 302.

[0040] As described above, the A / D conversion section 302 and the sampling section 303 perform a process of repeatedly sampling the pixel reset signal and the pixel signal and integrating the sampling result. This process is a so-called correlated double sampling process.

[0041] If the predetermined number of samplings is completed by the individual pixel control section 306, the sampling section 303 outputs a digital value based on the value stored in the first memory 309 and the value stored in the second memory 311 to the pixel value holding section 304. The pixel value holding section 304 stores this digital value as the photoelectric conversion result of the pixel 30. The pixel value holding section 304 is connected to the signal line 340. The digital value stored in the pixel value holding section 304 can be read from the outside via the signal line 340.

[0042] The operation section 305 performs an operation of the number of repetitions, the exposure time, the gain, and the like in the correlated double sampling process based on the exposure time instructed from the outside or the last photoelectric conversion result held in the pixel value holding section 304. The individual pixel control section 306 outputs the number of repetitions and the gain operated by the operation section 305 to the A / D conversion section 302. The individual pixel control section 306 outputs the exposure time and the gain operated by the operation section 305 to the pixel drive section 307. The pixel drive section 307 outputs various signals (described below) for driving each section of the analog circuit section 301 to the analog circuit section 301.

[0043] Figure 4 is a circuit diagram of the analog circuit section 301, the individual pixel control section 306, and the pixel drive section 307. Furthermore, in Figure 4 , only a part of the individual pixel control section 306 and the pixel drive section 307 are illustrated for convenience of understanding. A part of the individual pixel control section 306 is denoted by the reference numerals 306a and 306b, and a part of the pixel drive section 307 is denoted by the reference numerals 307a and 307b.

[0044] The analog circuit section 301 has a photodiode 31, a transfer transistor Tx, a floating diffusion section FD, a first reset transistor RST1, a second reset transistor RST2, an amplification transistor AMI, a selection transistor SEL, an expansion capacity transistor FDS, and a capacitor C1.

[0045] The photodiode 31 is a photoelectric conversion section that photoelectrically converts incident light to generate an amount of electric charge corresponding to the amount of light of the incident light. The transfer transistor Tx is a transfer section that transfers the electric charge generated by the photodiode 31 to the floating diffusion section FD based on a transfer signal supplied from the transfer signal supply section 307a described below. The floating diffusion section FD is an accumulation section that accumulates the electric charge transferred by the transfer transistor Tx. The amplification transistor AMI outputs a signal corresponding to the amount of electric charge accumulated in the floating diffusion section FD. The signal output by the amplification transistor AMI is input to the A / D conversion section 302 when the selection transistor SEL is turned on.

[0046] The analog circuit section 301 has two reset transistors, a first reset transistor RST1 and a second reset transistor RST2. The first reset transistor RST1 receives supply of a first reset signal from the first reset signal supply section 307b described below when resetting the floating diffusion section FD. The first reset signal supply section 307b described below supplies a signal of the voltage VDD as the first reset signal. The first reset transistor RST1 resets the floating diffusion section FD based on this first reset signal. The second reset transistor RST2 receives supply of a second reset signal from the second reset signal supply section 307c described below when resetting the photodiode 31. The second reset signal supply section 307c described below supplies a signal of the voltage VDD as the second reset signal. The second reset transistor RST2 resets the photodiode 31 based on this second reset signal.

[0047] The expansion capacity transistor FDS switches the connection of the floating diffusion section FD and the capacitor Cl based on an expansion capacity signal supplied from the expansion capacity signal supply section 307d described below. For example, in a case where the amount of incident light to the photodiode 31 is large and the floating diffusion section FD is saturated, the floating diffusion section FD and the capacitor Cl are connected by turning on the expansion capacity transistor FDS. Thus, the capacitance of the floating diffusion section FD is substantially increased only by the amount of the capacitor Cl, and a larger amount of light can be dealt with.

[0048] The first reset signal supply section 307b is a CMOS circuit composed of a pMOS transistor Tr7 and an nMOS transistor Tr8. The first reset signal supply section 307b supplies, as a first reset signal, a voltage of either one of a voltage VDD (a prescribed power supply voltage. The same applies hereinafter) and a ground voltage (GND) to a gate of the first reset transistor RST1, based on an output signal of the first reset control section 306b. As described above, the first reset control section 306b is part of the individual pixel control section 306, and the first reset signal supply section 307b is part of the pixel drive section 307. Further, when over drive is performed, the first reset control section 306b can supply, instead of the voltage VDD, a voltage VRST1H higher than the voltage VDD to the gate of the first reset transistor RST1.

[0049] The expansion capacity signal supply section 307d is a CMOS circuit composed of a pMOS transistor Tr11 and an nMOS transistor Tr12. The expansion capacity signal supply section 307d supplies, as an expansion capacity signal, a voltage of either one of the voltage VDD and the ground voltage (GND) to a gate of the expansion capacity transistor FDS, based on an output signal of the expansion capacity control section 306d. As described above, the expansion capacity control section 306d is part of the individual pixel control section 306, and the expansion capacity signal supply section 307d is part of the pixel drive section 307. Further, when over drive is performed, the expansion capacity signal supply section 307d can supply, instead of the voltage VDD, a voltage VFDSH higher than the voltage VDD to the gate of the expansion capacity transistor FDS.

[0050] The transfer signal supply section 307a is a CMOS circuit composed of a pMOS transistor Tr2 and an nMOS transistor Tr1. The transfer signal supply section 307a supplies, as a transfer signal, a voltage of either one of a voltage VTxH supplied from a first power supply section and a voltage VTxL supplied from a second power supply section to a gate of the transfer transistor Tx, based on an output signal of the transfer control section 306a. The voltage VTxH supplied from the first power supply section is a voltage (i.e., a positive voltage) higher than a substrate voltage of the first semiconductor substrate 7, i.e., a ground voltage, and the voltage VTxL supplied from the second power supply section is a voltage (i.e., a negative voltage) lower than the substrate voltage of the first semiconductor substrate 7, i.e., the ground voltage. As described above, the transfer control section 306a is part of the individual pixel control section 306, and the transfer signal supply section 307a is part of the pixel drive section 307.

[0051] The first reset signal or the second reset signal described above is a voltage of either one of the voltage VDD and the ground voltage, and, in contrast thereto, the transmission signal output from the transmission signal supply section 307a is a voltage of either one of the voltage VTxH and the voltage VTxL. The voltage VTxH is a voltage (i.e., a positive voltage) higher than the substrate voltage of the first semiconductor substrate 7, i.e., the ground voltage, and the voltage VTxL is a voltage (i.e., a negative voltage) lower than the substrate voltage of the first semiconductor substrate 7, i.e., the ground voltage. Further, the voltage VTxH and the voltage VDD are both positive voltages, but can be either the same voltage or different voltages.

[0052] The output signal of the transmission control section 306a is a voltage of either one of the voltage VDD and the ground voltage (GND). The nMOS transistor Trl is turned on when the voltage VDD is output from the transmission control section 306a, and supplies the voltage VTxL to the gate of the transmission transistor Tx. The pMOS transistor Trl is turned off when the voltage VDDD is output from the transmission control section 306a. The nMOS transistor Trl is turned off when the ground voltage is output from the transmission control section 306a. The pMOS transistor Trl is turned on when the ground voltage is output from the transmission control section 306a, and supplies the voltage VTxH to the gate of the transmission transistor Tx. That is, the transmission signal supply section 307a converts the signal supplied from the transmission control section 306a, which includes the voltage VDD and the ground voltage, into a signal including the voltage VTxH and the voltage VTxL, and supplies it to the gate of the transmission transistor Tx. The voltage VTxH is a voltage (i.e., a positive voltage) higher than the substrate voltage of the first semiconductor substrate 7, i.e., the ground voltage, and the voltage VTxL is a voltage (i.e., a negative voltage) lower than the substrate voltage of the first semiconductor substrate 7, i.e., the ground voltage. Further, the threshold voltage Vth of the nMOS transistor Trl is set to be relatively high so that current does not flow between the drain and the source even in a state where the ground voltage is supplied from the transmission control section 306a. For example, in a case where the voltage VTxL is -2 V, a voltage of 2 V is applied between the gate and the source of the nMOS transistor Trl in a state where the ground voltage is supplied from the transmission control section 306a. The threshold voltage Vth of the nMOS transistor Trl is set to be, for example, about 3 to 4 V so that the nMOS transistor Trl is not turned on even when a voltage of 2 V is applied between the gate and the source.

[0053] The transmission transistor Tx transfers the charge generated by the photodiode 31 to the floating diffusion section FD when the transmission signal is the voltage VTxH. The transmission transistor Tx does not transfer the charge generated by the photodiode 31 to the floating diffusion section FD when the transmission signal is the voltage VTxL. Further, the voltage VTxL, which is lower than the substrate voltage of the first semiconductor substrate 7, is applied to the gate of the transmission transistor Tx in order to not transfer the charge from the photodiode 31 to the floating diffusion section FD when the transmission transistor Tx is turned off.

[0054] The second reset signal supply section 307c is a CMOS circuit composed of a pMOS transistor Tr9 and an nMOS transistor Tr10. The second reset signal supply section 307c supplies either of the voltage VTxH and the voltage VTxL as a second reset signal to the gate of the second reset transistor RST2 based on the output signal of the second reset control section 306c. The structure of the second reset signal supply section 307c is omitted because it is the same as that of the transfer signal supply section 307a. As described above, the second reset control section 306c is a part of the individual pixel control section 306, and the second reset signal supply section 307c is a part of the pixel drive section 307.

[0055] Figure 5 Fig. 13 is a diagram schematically showing the well structure of the first semiconductor substrate 7 and the second semiconductor substrate 8. Incident light is incident on the first semiconductor substrate 7 from the direction of the paper surface. The first semiconductor substrate 7 is a P-type semiconductor substrate having an SOI structure. The substrate voltage of the first semiconductor substrate 7 is set to the ground voltage (GND). The second semiconductor substrate 8 is a general P-type semiconductor substrate not having an SOI structure. The substrate voltage of the second semiconductor substrate 8 is set to the ground voltage (GND).

[0056] The buried insulating film 77 is provided on the surface of the first semiconductor substrate 7 opposite to the second semiconductor substrate 8. The buried insulating film 77 is an insulating film buried in the silicon substrate. The transfer signal supply section 307a is formed on the buried insulating film 77. That is, the CMOS circuit composed of the pMOS transistor Tr2 and the nMOS transistor Trl is formed on the buried insulating film 77.

[0057] The pMOS transistor Tr2 has a p-type region 325, an n-type region 326, a p-type region 327, and a gate electrode 332. The p-type regions 325 and 327 are drain and source regions formed by ion-implanting a high concentration of impurities into a silicon layer formed on the buried insulating film 77. The n-type region 326 is a channel region formed by ion-implanting impurities into the silicon layer formed on the buried insulating film 77 so as to have a prescribed threshold voltage Vth.

[0058] The nMOS transistor Trl has an n-type region 322, a p-type region 323, an n-type region 324, and a gate electrode 331. The n-type regions 322 and 324 are source and drain regions formed by ion-implanting a high concentration of impurities into a silicon layer formed on the buried insulating film 77. The p-type region 323 is a channel region formed by ion-implanting impurities into the silicon layer formed on the buried insulating film 77 so as to have a prescribed threshold voltage Vth.

[0059] The pMOS transistor Tr2 and the nMOS transistor Trl are isolated from other circuit elements by element isolation structures 328, 329, 330 of STI (Shallow Trench Isolation).

[0060] The p-type region 327 of the pMOS transistor Tr2 is connected to a power supply section not shown. The power supply section supplies a voltage VTxH (i.e., a voltage higher than the substrate voltage of the first semiconductor substrate 7) to the p-type region 327 of the pMOS transistor Tr2 included in all the pixels 30. The n-type region 322 of the nMOS transistor Trl is connected to a power supply section not shown. The power supply section supplies a voltage VTxL (i.e., a voltage lower than the substrate voltage of the first semiconductor substrate 7) to the n-type region 322 of the nMOS transistor Trl included in all the pixels 30.

[0061] The transfer signal supply section 307a is connected to the gate electrode of the transfer transistor Tx. The transfer signal supply section 307a is electrically insulated from other elements provided in the first semiconductor substrate 7.

[0062] The buried insulating film 77 in the present embodiment exists only in a region of the first semiconductor substrate 7 in which the transfer signal supply section 307a is provided. The first semiconductor substrate 7 is manufactured using a wafer having an SOI structure (i.e., in a state in which a buried insulating film 77 is buried in the entire surface). At the time of manufacturing the first semiconductor substrate 7, the buried insulating film 77 existing in a region different from the region in which the transfer signal supply section 307a is provided, and a silicon layer formed on the buried insulating film 77 are removed.

[0063] A region in which the buried insulating film 77 does not exist (has been removed) in the entire first semiconductor substrate 7 is provided with the analog circuit section 301 shown in Fig. 1. Further, in the region in which the buried insulating film 77 does not exist, the first semiconductor substrate 7 is provided with a transfer signal supply section 307b, a transfer signal supply section 307c, and a transfer signal supply section 307d. Figure 4 The analog circuit section 301 shown in Fig. 1. Further, in the region in which the buried insulating film 77 does not exist, the first semiconductor substrate 7 is provided with a transfer signal supply section 307b, a transfer signal supply section 307c, and a transfer signal supply section 307d. Figure 5 In Fig. 1, only the photodiode 31, the transfer transistor Tx, the first reset transistor RSTl, and the floating diffusion section FD among the respective sections possessed by the analog circuit section 301 are illustrated due to the paper surface.

[0064] The photodiode 31 photoelectrically converts incident light incident from above the paper surface. As shown in Fig. 1, the photodiode 31 is provided in the first semiconductor substrate 7. Figure 5As illustrated, in the present embodiment, a part of the photodiode 31 is located under the buried insulating film 77. In other words, a part of the photodiode 31 opposes a part of the transfer signal supply portion 307a via the buried insulating film 77. This is to make the photodiode 31 receive a wider range of incident light. For the pMOS transistor Tr2 and the nMOS transistor Tr1 formed in the buried insulating film 77, the silicon layer under the buried insulating film 77 functions as a support base material. That is, the silicon layer under the buried insulating film 77 is irrelevant to the electrical operation of the pMOS transistor Tr2 and the nMOS transistor Tr1 on the buried insulating film 77. Therefore, in the present embodiment, by extending the photodiode 31 to the region under the buried insulating film 77, a larger opening of the photodiode 31 is obtained.

[0065] Further, in the photodiode 31, a concentration gradient is provided in the impurity concentration, and the closer to the region of the transfer transistor Tx, the higher the impurity concentration. This is to reliably transfer the charge in the photodiode 31 through the transfer transistor Tx. The photodiode 31 is formed in the first semiconductor substrate 7 by ion implantation, for example, before the transfer signal supply portion 307a is formed.

[0066] The transfer control portion 306a, the first reset control portion 306b, and the first reset signal supply portion 307b are provided in the second semiconductor substrate 8. Figure 4 The transfer control portion 306a, the first reset control portion 306b, and the first reset signal supply portion 307b are provided in the second semiconductor substrate 8. Figure 5 The other portions illustrated in FIG. 8 are omitted from the illustration, but Figure 4 The other portions illustrated in FIG. 8 are provided in the second semiconductor substrate 8.

[0067] Figure 6 is a time chart indicating the timing of photographing using the imaging element 3. The imaging element 3 selectively performs multiple exposure and correlated double sampling. First, the multiple exposure control is performed using Figure 6 The multiple exposure control is described with reference to (a) of FIG. 10.

[0068] Figure 6 (a) of FIG. 10 is a time chart at the time of multiple exposure for each pixel 30. Figure 6 The horizontal axis of (a) of FIG. 10 is time, and time advances in the right direction. Figure 6 The quadrangle on which "Dark" is written in (a) of FIG. 10 indicates the timing at which the A / D conversion portion 302 performs sampling of the pixel reset signal. Figure 6 The quadrangle on which "Sig" is written in (a) of FIG. 10 indicates the timing at which the A / D conversion portion 302 performs sampling of the pixel signal. Figure 6 The quadrangle on which "Out" is written in (a) of FIG. 10 indicates the timing at which the digital value (photoelectric conversion result) stored in the pixel value holding portion 304 is output to the peripheral circuit via the signal line 340. In Figure 6In (a), pixel 30 is classified into four pixels, from pixel 30a to pixel 30d, based on the amount of incident light, and multiple exposures are performed.

[0069] The reset operation of the photodiode 31 and the floating diffuser FD at the beginning of exposure T1 is the same for all pixels 30. Then, in pixels 30a with very little incident light, the floating diffuser FD is reset at time t3, and the pixel reset signal is sampled. Time t3 is obtained by subtracting the time required for the reset of the floating diffuser FD and the sampling of the pixel reset signal from the end of exposure T1, time t4. At the end of exposure T1, time t4, the charge accumulated in the photodiode 31 from time t0 to t4 is transferred to the floating diffuser FD, and the pixel signal is sampled. Then, at time t5, the photoelectric conversion result is stored in the pixel value holding unit 304.

[0070] In pixel 30b, where the incident light intensity is slightly lower, the externally specified exposure period T1 is divided into two periods, T2 and T3, and the aforementioned operation is performed twice. Specifically, at times t1 and t3, the floating diffuser FD is reset, and the pixel reset signal is sampled. Time t1 is obtained by subtracting the time required for resetting the floating diffuser FD and sampling the pixel reset signal from the end time t2 of period T2. Then, at time t2, the charge accumulated in the photodiode 31 is transferred to the floating diffuser FD, and the pixel signal is sampled. The operation from times t3 to t5 is the same as that of pixel 30a.

[0071] In pixel 30c, which has a slightly higher incident light intensity, the externally specified exposure period T14 is divided into four equal parts, and the above operation is performed four times. In pixel 30d, which has an extremely high incident light intensity, the externally specified exposure period T18 is divided into eight equal parts, and the above operation is performed eight times.

[0072] As described above, based on multiple exposure control, it is possible to individually vary the exposure time of pixels 30 with higher incident light and pixels 30 with lower incident light to take pictures. In normal shooting, even when the floating diffuser (FD) is more saturated and has a higher incident light, the dynamic range can be expanded by finely dividing the exposure time and taking pictures repeatedly.

[0073] Secondly, use Figure 6 (b) provides an explanation of the relevant double sampling control. Figure 6 (b) is a time map of the correlation double sampling control for each pixel 30. Figure 6 The horizontal axis of (b) represents time, which moves to the right. Figure 6 The quadrilateral marked "Dark" in (b) indicates the timing of the A / D conversion unit 302 sampling the pixel reset signal.Figure 6 The quadrilateral marked with "Sin" in (b) indicates the timing of the A / D conversion unit 302 sampling the pixel signal. Figure 6 The quadrilateral marked "Out" in (b) indicates the timing of the A / D conversion unit 302 outputting the sampling result to the sampling unit 303. Figure 6 In (b), pixel 30 is classified into four pixels, 30a to 30d, based on the amount of incident light, and then correlated double sampling is performed.

[0074] Pixel 30a has the longest exposure time, while pixel 30d has the shortest. In the correlated dual-sampling control, the longer the exposure time of pixel 30, the earlier the floating diffuser FD is reset. For pixels 30 with longer exposure times, there is a time interval between the reset of the multiple floating diffusers FD and the sampling of the pixel signal. During this period, the pixel reset signal is repeatedly sampled.

[0075] For example, in Figure 7 In (b), pixel 30a has the longest exposure time. The floating diffuser FD is reset at time t7, which is 1 hour earlier than the end of exposure time T4 for pixel 30a. As a result, the pixel reset signal is sampled four times up to time t6. The pixel signal is repeatedly sampled during the period from the end of exposure time T4 to the end of the next exposure time T6.

[0076] A longer exposure time means less incident light, and also means greater noise in the pixel signal's amplification transistor (AMI), selection transistor (SEL), and A / D converter 302. In other words, the greater the noise affecting a pixel 30, the more times the pixel reset signal and pixel signal are sampled, resulting in higher sensitivity for image capture.

[0077] The imaging element 3 performs the above operations in parallel for each of the pixels 30. That is, each pixel 30 performs operations in parallel from photoelectric conversion via the photodiode 31 to storage of digital values ​​in the pixel value holding unit 304. The imaging results from the pixel value holding unit 304 are read sequentially for each pixel 30.

[0078] As described above, the imaging device 3 of the present embodiment can control the exposure time for each pixel. In order to control the exposure time for each pixel, it is necessary to be able to control the timing of turning on and off of the transfer transistor Tx for each pixel. That is, it is necessary to be able to control the voltage (voltage VTXH and voltage VTXL in the present embodiment) supplied to the gate of the transfer transistor Tx for each pixel. That is, it is necessary to provide a supply portion of the voltage VTXH and voltage VTXL to be supplied to the gate of the transfer transistor Tx for each pixel. The voltage handled by the first semiconductor substrate 7 is different from the voltage VTXH or voltage VTXL, so if the supply portion of the voltage VTXH or voltage VTXL to be handled is provided within the pixel 30, the supply portion occupies a large area. As a result, the area of the photodiode 31 in the pixel 30 is greatly reduced. That is, the aperture ratio of the photodiode 31 is greatly reduced. In the present embodiment, by providing the transfer signal supply portion 307a to the insulating portion 9, it is possible to control the exposure time for each pixel without individually providing the supply portion of the voltage VTXH or voltage VTXL to be handled near the photodiode 31 of the first semiconductor substrate 7 (without reducing the aperture ratio of the photodiode 31).

[0079] According to the above-described embodiment, the following advantageous effects are obtained.

[0080] (1) The plurality of pixels 30 provided to the first semiconductor substrate 7 each have a transfer transistor Tx that inputs a transfer signal composed of a voltage VTXH higher than the substrate voltage, i.e., ground voltage, of the first semiconductor substrate 7 and a voltage VTXL lower than the substrate voltage, i.e., ground voltage, of the first semiconductor substrate 7. The A / D conversion portion 302 and the sampling portion 303 provided to the second semiconductor substrate 8 output a digital signal based on the amount of charge accumulated in the floating diffusion portion FD. In the insulating portion 9 provided between the first semiconductor substrate 7 and the second semiconductor substrate 8, a transfer signal supply portion 307a that supplies a transfer signal to the transfer transistor Tx is provided for each of the plurality of pixels 30. Therefore, it is possible to reliably turn off the transfer transistor Tx without reducing the area of the photodiode 31, and to suppress an increase in dark current. In addition, since a circuit that handles a negative power source is not present in the first semiconductor substrate 7, it is not necessary to provide a diffusion layer or the like for handling a negative power source on the first semiconductor substrate 7, and it is possible to increase the aperture ratio of the photodiode 31. The same effects can be obtained for the second reset transistor RST2 as well.

[0081] (2) Some of the plurality of transfer signal supply portions 307a transfer the electric charges generated by the photodiode 31 in a first period to the floating diffusion portion FD. The other of the plurality of transfer signal supply portions 307a transfers the electric charges generated by the photodiode 31 in a second period different in length from the first period to the floating diffusion portion FD. Thus, it is possible to make the exposure time different for each pixel 30, and to expand the dynamic range of the imaging device 3.

[0082] (3) The photodiode 31 photoelectrically converts incident light incident to one face of the first semiconductor substrate 7. The insulating portion 9 is provided opposite to the other face of the first semiconductor substrate 7. Thus, it is possible to improve the photoelectric conversion efficiency of the photodiode 31.

[0083] (4) The transfer signal supply portion 307a has a p-type region 327 that receives a voltage VTxH from a power supply portion of a voltage higher than the substrate voltage of the first semiconductor substrate 7, and an n-type region 322 that receives a voltage VTxL from a power supply portion of a voltage lower than the substrate voltage of the first semiconductor substrate 7. The transfer signal supply portion 307a inputs the voltage VTxH received from the former power supply portion and the voltage VTxL received from the latter power supply portion to the transfer transistor Tx as a transfer signal. Thus, the transfer signal supply portion 307a can handle signals having different voltages from each circuit disposed in the first semiconductor substrate 7 and the second semiconductor substrate 8. The same effect can be obtained also for the second reset signal supply portion 307c.

[0084] (5) A part of the photodiode 31 opposes a part of the transfer transistor Tx via the buried insulating film 77. Thus, it is possible to make the area of the photodiode 31 larger, and to more effectively use incident light.

[0085] (6) The first semiconductor substrate 7 is formed with the buried insulating film 77, and the substrate voltage is set to the ground voltage. On the first semiconductor substrate 7, there are provided the photodiode 31 that photoelectrically converts incident light, the transfer transistor Tx that transfers electric charges obtained by the photoelectric conversion by the photodiode 31 to the floating diffusion portion FD based on a transfer signal, and the transfer signal supply portion 307a that supplies a transfer signal including a voltage corresponding to a voltage VTxH higher than the substrate voltage of the first semiconductor substrate 7 and a voltage corresponding to a voltage VTxL lower than the substrate voltage of the first semiconductor substrate 7 to the transfer transistor Tx, and is electrically insulated from the first semiconductor substrate 7 by the buried insulating film 77. Thus, it is possible to reliably turn off the transfer transistor Tx, and to suppress the increase in dark current. The same effect can be obtained also for the second reset transistor RST2.

[0086] (Second Embodiment)

[0087] The imaging element 3 of the first embodiment has a semiconductor substrate having an SOI configuration. The imaging element 3 of the second embodiment differs from the first embodiment in that it has a semiconductor substrate having a general configuration other than an SOI configuration and is composed of thin film transistors for the transfer signal supply section 307a. Hereinafter, the imaging element 3 of the second embodiment will be described focusing on the differences from the imaging element 3 of the first embodiment. Further, the same reference numerals are assigned to the same parts as those of the first embodiment, and the description thereof will be omitted.

[0088] Figure 8 is a circuit diagram of the transfer signal supply section 307a, Figure 7 is a plan view of the transfer signal supply section 307a. As Figure 8 and Figure 9 indicated, the transfer signal supply section 307a of the present embodiment has an nMOS transistor Tr21, an nMOS transistor Tr22, a pMOS transistor Tr23, an nMOS transistor Tr24, an nMOS transistor Tr25, and a pMOS transistor Tr26. These transistors are thin film transistors (TFTs). In addition, the pixel 30 of the present embodiment also has an inverter circuit 312.

[0089] The nMOS transistor Tr22 and the pMOS transistor Tr23 constitute a CMOS circuit. The source of the pMOS transistor Tr23 is supplied with a voltage VTxH by a prescribed power supply. The gates of the nMOS transistor Tr22 and the pMOS transistor Tr23 are supplied with a transfer control signal by the transfer control section 306a. The source of the nMOS transistor Tr22 is connected to the drain of the nMOS transistor Tr21. The source of the nMOS transistor Tr21 is supplied with a voltage VTxL by a prescribed power supply. The voltage VTxH is a voltage (i.e., a positive voltage) higher than the substrate voltage of the first semiconductor substrate 7, i.e., a ground voltage, and the voltage VTxL is a voltage (i.e., a negative voltage) lower than the substrate voltage of the first semiconductor substrate 7, i.e., a ground voltage.

[0090] The nMOS transistor Tr25 and the pMOS transistor Tr26 constitute a CMOS circuit. The source of the pMOS transistor Tr26 is supplied with a voltage VTxH by a prescribed power supply. The gates of the nMOS transistor Tr25 and the pMOS transistor Tr26 are supplied with a signal inverting the high level and the low level of the transfer control signal by the inverter circuit 312. The source of the nMOS transistor Tr25 is connected to the drain of the nMOS transistor Tr24. The source of the nMOS transistor Tr24 is supplied with a voltage VTxL by a prescribed power supply.

[0091] The gate of nMOS transistor Tr24 is connected to the drain of nMOS transistor Tr22 and pMOS transistor Tr23. The gate of nMOS transistor Tr21 is connected to the drain of nMOS transistor Tr25 and pMOS transistor Tr26. The voltage from the drains of nMOS transistor Tr25 and pMOS transistor Tr26 is supplied to the transmission transistor Tx as a transmission signal.

[0092] The transmission signal supply unit 307a, configured as described above, supplies either a voltage VTxH (higher than the substrate voltage of the first semiconductor substrate 7) or a voltage VTxL (lower than the substrate voltage of the first semiconductor substrate 7) as a transmission signal to the gate of the transmission transistor Tx, based on the output signal of the transmission control unit 306a. That is, the circuit composed of nMOS transistors Tr21, Tr22, Tr23, Tr24, Tr25, and Tr26 is a level conversion circuit that converts a signal composed of voltage VTxH and ground voltage into a signal composed of voltage VTxH and voltage VTxL.

[0093] The inverter circuit 312 is a CMOS circuit composed of a pMOS transistor Tr28 and an nMOS transistor Tr27. The inverter circuit 312 is disposed on the first semiconductor substrate 7. Based on the output signal of the transmission control unit 306a, the inverter circuit 312 supplies either voltage VDD or ground voltage (GND) to the gate of the nMOS transistor Tr25 and the gate of the pMOS transistor Tr26.

[0094] Figure 8 (a) is the A-A' section representing the transmission signal supply unit 307a. Figure 9 A schematic diagram of ) Figure 8 (b) is the B-B' section representing the signal transmission supply unit 307a. Figure 9 A schematic diagram of the above. A signal transmission supply unit 307a is formed in an insulating portion 9 disposed between a first semiconductor substrate 7 and a second semiconductor substrate 8. The transmission and reception of signals between the first semiconductor substrate 7 and the second semiconductor substrate 8 are performed via bonding pads 90.

[0095] exist Figure 5 In this structure, a signal transmission supply unit 307a is disposed on an insulating portion 9. An insulating layer is formed at the interface between the insulating portion 9 and the second semiconductor substrate 8, and the signal transmission supply unit 307a is formed on this insulating layer.

[0096] As described above, the imaging device 3 of the present embodiment can control the exposure time for each pixel. In order to control the exposure time for each pixel, it is necessary to control the timing of turning on and off of the transfer transistor Tx for each pixel. That is, it is necessary to control the voltage (voltage VTxH and voltage VTxL in the present embodiment) supplied to the gate of the transfer transistor Tx for each pixel. That is, it is necessary to provide a supply unit that supplies the voltage VTxH and the voltage VTxL to the gate of the transfer transistor Tx for each pixel. Since the voltage handled by the first semiconductor substrate 7 is different from the voltage VTxH or the voltage VTxL, if the supply unit that handles the voltage VTxH or the voltage VTxL is provided within the pixel 30, the supply unit occupies a large area. In particular, the supply unit that supplies the voltage VTxL lower than the substrate voltage needs to be a three-well structure so as not to be forward-biased with respect to the substrate. Therefore, the supply unit that supplies the voltage VTxL needs a particularly wide area. As a result, the area of the photodiode 31 on the pixel 30 is significantly reduced. That is, the aperture ratio of the photodiode 31 is significantly reduced, and the miniaturization of the imaging device becomes difficult. In the present embodiment, by providing the transfer signal supply unit 307a to the insulating portion 9, it is possible to control the exposure time for each pixel without individually providing the supply unit that handles the voltage VTxH or the voltage VTxL near the photodiode 31 of the first semiconductor substrate 7 (without reducing the aperture ratio of the photodiode 31).

[0097] According to the above-described embodiment, in addition to the effects described in the first embodiment, the following effects are further obtained.

[0098] (7) The transfer signal supply unit 307a has a level conversion circuit that converts a drive signal composed of a ground voltage and a voltage VTxH higher than the ground voltage into a transfer signal composed of a voltage VTxL and a voltage VTxH. Therefore, the transfer signal supply unit 307a can supply a signal having a voltage different from each circuit disposed on the first semiconductor substrate 7 and the second semiconductor substrate 8 to the transfer transistor Tx.

[0099] (8) An inverter circuit 312 that outputs a signal supplied from the transfer control unit 306a to the level conversion circuit is provided on the first semiconductor substrate 7. The level conversion circuit includes six transistors Tr21 to Tr26, and outputs the voltage VTxL as a transfer signal when the signal supplied from the transfer control unit 306a is a ground voltage, and outputs the voltage VTxH as a transfer signal when the signal supplied from the transfer control unit 306a is the voltage VTxH. Therefore, the transfer control unit 306a can supply the voltage VTxL to the transfer transistor Tx without handling the voltage VTxL.

[0100] (9) The transmission signal supply section 307a includes thin film transistors, i.e., six transistors Tr21 to Tr26, formed in the insulating layer 9 laminated on the first semiconductor substrate 7. Therefore, the first semiconductor substrate 7 as the main body of the semiconductor substrate can reduce manufacturing costs.

[0101] The following modifications are also included in the scope of the present application, and one or more modifications can be combined with the above-described embodiments.

[0102] (Modification 1)

[0103] The level conversion circuit described in the second embodiment can be added to the front stage of the transmission signal supply section 307a described in the first embodiment. That is, the level conversion circuit can be inserted between the gate electrodes 331, 332 and the transmission control section 306a as shown in FIG. 6. Therefore, it is not necessary to set the threshold voltage Vth of the nMOS transistor Trl to be higher. Figure 9

[0104] (Modification 2)

[0105] In the second embodiment, as shown in FIG. 5, the transmission signal supply section 307a is provided on the insulating layer provided on one surface of the second semiconductor substrate 8, but the transmission signal supply section 307a can be provided on the first semiconductor substrate 7 side. In this case, the insulating layer is formed only on the surface of the first semiconductor substrate 7 opposite to the second semiconductor substrate 8, and the transmission signal supply section 307a is formed on the insulating layer. ​

[0106] The above-described embodiments and modifications are described, but the present application is not limited to these. Other modes considered within the scope of the technical idea of the present application are also included in the scope of the present application.

[0107] The above-described embodiments and modifications also include a photographing apparatus and an electronic camera as follows.

[0108] (1) An image pickup element including: a first semiconductor layer provided with a plurality of pixels, the pixel having a photoelectric conversion section that photoelectrically converts incident light, an accumulation section that transfers and accumulates electric charges obtained by the photoelectric conversion by the photoelectric conversion section, and a transfer section that transfers the electric charges generated by the photoelectric conversion section to the accumulation section; a second semiconductor layer provided with a supply section for each of the plurality of pixels, the supply section supplying a transfer signal for transferring the electric charges from the photoelectric conversion section to the accumulation section to the transfer section; and a third semiconductor layer input with a signal based on the electric charges transferred to the accumulation section.

[0109] ​​(2) The imaging device of (1), wherein the second semiconductor layer has a thin film transistor.

[0110] (3) The imaging device of (2), wherein the first semiconductor layer and the third semiconductor layer are composed of a semiconductor substrate.

[0111] (4) The imaging device of (2) or (3), wherein the second semiconductor layer is disposed at an insulating portion provided between a semiconductor substrate that is the first semiconductor layer and a semiconductor substrate that is the third semiconductor layer.

[0112] (5) The imaging device of (1), wherein the first semiconductor layer is one of a silicon substrate and a silicon layer of an SOI substrate having the silicon substrate, a buried oxide film layer, and the silicon layer, and the second semiconductor layer is the other of the silicon substrate and the silicon layer.

[0113] (6) The imaging device of (5), wherein the third semiconductor layer is composed of a semiconductor substrate.

[0114] (7) The imaging device of any one of (1) to (6), wherein some of the plurality of supply portions transfer, to the accumulation portion, charges generated by the photoelectric conversion portion during a first period, and the other of the plurality of supply portions supplies, to the transfer portion, a transfer signal for transferring, to the accumulation portion, charges generated by the photoelectric conversion portion during a second period different in length from the first period.

[0115] (8) The imaging device of any one of (1) to (7), wherein the supply portion has a first diffusion portion to which a voltage higher than a voltage of the first semiconductor layer is applied by a first power supply portion, and a second diffusion portion to which a voltage lower than the voltage of the first semiconductor layer is applied by a second power supply portion, supplies a first voltage based on a voltage applied by the first power supply portion to the transfer portion, and supplies a second voltage based on a voltage applied by the second power supply portion to the transfer portion.

[0116] (9) The imaging device of (8), wherein the photoelectric conversion portion is a buried photodiode, the transfer portion transfers, to the accumulation portion, charges obtained by photoelectric conversion by the photoelectric conversion portion when the transfer signal is the first voltage, and does not transfer, to the accumulation portion, charges obtained by photoelectric conversion by the photoelectric conversion portion when the transfer signal is the second voltage.

[0117] (10) The imaging device of (9), wherein the supply portion has a level conversion circuit that converts a drive signal composed of a third voltage of or above a ground voltage and a fourth voltage of or above the ground voltage and higher than the third voltage into the transfer signal composed of the first voltage and the second voltage.

[0118] (11) The imaging device of (10), further comprising an inverter circuit that outputs the drive signal to the level conversion circuit, the level conversion circuit including at least six transistors, the transfer signal being output as the first voltage when the drive signal is the third voltage, and the transfer signal being output as the second voltage when the drive signal is the fourth voltage.

[0119] (12) The imaging device of any one of (1) to (11), wherein the photoelectric conversion section is provided on a light-incident surface of the first semiconductor layer, and the transfer section and the accumulation section are provided on a surface of the first semiconductor layer on the second semiconductor layer side.

[0120] (13) An imaging device comprising: a first semiconductor substrate provided with a plurality of pixels, the pixels each having a photoelectric conversion section that photoelectrically converts incident light, an accumulation section that transfers and accumulates electric charges obtained by photoelectrically converting the incident light by the photoelectric conversion section, and a transfer section that transfers the electric charges generated by the photoelectric conversion section to the accumulation section; and a semiconductor layer that is laminated on the first semiconductor substrate and provided with a supply section for each of the plurality of pixels, the supply section supplying a transfer signal for transferring the electric charges from the photoelectric conversion section to the accumulation section to the transfer section.

[0121] (14) An imaging device comprising: a first semiconductor substrate formed with an insulating section and provided with a prescribed substrate voltage; a photoelectric conversion section provided on the first semiconductor substrate and photoelectrically converting incident light; a transfer section provided on the first semiconductor substrate and transferring electric charges obtained by photoelectrically converting the incident light by the photoelectric conversion section to an accumulation section based on a transfer signal; and a supply section that supplies the transfer signal including a first signal voltage as a positive voltage and a second signal voltage as a negative voltage to the transfer section and is electrically insulated from the first semiconductor substrate by the insulating section.

[0122] (15) An electronic camera having the imaging device of (1) to (14).

[0123] Further, the embodiment and the modified example also include an imaging device as follows.

[0124] (1) An imaging element comprising: a first semiconductor layer provided with a plurality of pixels, the pixels each having a photoelectric conversion section that photoelectrically converts incident light, an accumulation section that accumulates electric charges obtained by photoelectric conversion by the photoelectric conversion section, and a transfer section to which a transfer signal composed of a first voltage higher than a ground voltage and a second voltage lower than the ground voltage is input; a second semiconductor substrate provided with an A / D conversion section that outputs a digital signal based on an amount of electric charges accumulated in the accumulation section for each of the plurality of pixels; and an insulating section provided between the first semiconductor substrate and the second semiconductor substrate and provided with a transfer signal supply section that supplies the transfer signal to the transfer section for each of the plurality of pixels.

[0125] (2) In the imaging element of (1), some of the plurality of transfer signal supply sections transfer electric charges generated by the photoelectric conversion section in a first period to the accumulation section, and the other transfer signal supply sections supply the transfer signal that transfers electric charges generated by the photoelectric conversion section in a second period different in length from the first period to the accumulation section.

[0126] (3) In the imaging element of (1) or (2), the transfer signal supply section has a first diffusion section that receives a positive voltage from a first power supply section of positive voltage and a second diffusion section that receives a negative voltage from a second power supply section of negative voltage, the first voltage is input to the transfer section based on the positive voltage received from the first power supply section, and the second voltage is input to the transfer section based on the negative voltage received from the second power supply section.

[0127] (4) In the imaging element of (1) to (3), the photoelectric conversion section is a buried photodiode, and the transfer section transfers electric charges obtained by photoelectric conversion by the photoelectric conversion section to the accumulation section when the transfer signal is the first voltage and does not transfer electric charges obtained by photoelectric conversion by the photoelectric conversion section to the accumulation section when the transfer signal is the second voltage.

[0128] (5) In the imaging element of (4), the transfer signal supply section has a level shift circuit that shifts a drive signal composed of a third voltage of ground voltage or higher and a fourth voltage of ground voltage or higher and higher than the third voltage to the transfer signal composed of the first voltage and the second voltage.

[0129] (6) The imaging device of (5) further includes an inverter circuit that outputs the drive signal to the level conversion circuit, the level conversion circuit including at least six transistors, the level conversion circuit outputting the transfer signal as the first voltage when the drive signal is the third voltage and outputting the transfer signal as the second voltage when the drive signal is the fourth voltage.

[0130] (7) The imaging device of (1) to (6) includes the photoelectric conversion section provided on a surface of the first semiconductor substrate on which light is incident, and the transfer section and the accumulation section provided on a surface of the first semiconductor substrate on the side of the second semiconductor substrate.

[0131] (8) The imaging device of (1) to (7) includes the first semiconductor substrate being an SOI substrate, and the insulating section including a buried insulating film.

[0132] (9) The imaging device of (1) to (8) includes the insulating section including an insulating layer laminated on the first semiconductor substrate or the second semiconductor substrate, and the transfer signal supply section including a thin film transistor formed on the insulating layer.

[0133] (10) An imaging device including: a first semiconductor substrate formed with an insulating section and provided with a prescribed substrate potential; a photoelectric conversion section provided on the first semiconductor substrate and performing photoelectric conversion on incident light; a transfer section provided on the first semiconductor substrate and transferring electric charges obtained by the photoelectric conversion performed by the photoelectric conversion section to an accumulation section based on a transfer signal; and a transfer signal supply section supplying the transfer signal including a first signal potential as a positive potential and a second signal potential as a negative potential to the transfer section and electrically insulated from the first semiconductor substrate by the insulating section.

[0134] The disclosure of the following priority basis application is incorporated herein by reference.

[0135] Japanese Patent Application No. 2015-195281 (filed on September 30, 2015).

Claims

1. A camera element, characterized in that, have: A first semiconductor layer is provided with multiple pixels, each of which has a photoelectric conversion unit for generating charge by photoelectric conversion of light and a reset unit for resetting the charge generated by the photoelectric conversion unit. as well as A second semiconductor layer is provided with a supply section, which supplies a signal for resetting the charge generated by the photoelectric conversion section to the reset section. The supply section has a first diffusion section that is subjected to a voltage greater than or equal to the ground voltage, and a second diffusion section that is subjected to a voltage less than the ground voltage. It supplies a first voltage based on the voltage applied to the first diffusion section to the reset section, and supplies a second voltage based on the voltage applied to the second diffusion section to the reset section.

2. The imaging element according to claim 1, characterized in that, The second semiconductor layer has a thin-film transistor.

3. The imaging element according to claim 2, characterized in that, It has a third semiconductor layer, and outputs a signal based on the charge generated by the photoelectric conversion unit to the third semiconductor layer.

4. The imaging element according to claim 3, characterized in that, The first semiconductor layer and the third semiconductor layer are composed of a semiconductor substrate.

5. The imaging element according to claim 4, characterized in that, The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer.

6. The imaging element according to claim 5, characterized in that, The second semiconductor layer is disposed in an insulating portion between the first semiconductor layer and the third semiconductor layer.

7. The imaging element according to any one of claims 1 to 6, characterized in that, When a first voltage signal is supplied from the supply unit to the reset unit, the reset unit resets the charge; when a second voltage signal is supplied from the supply unit to the reset unit, the reset unit does not reset the charge.

8. The imaging element according to claim 7, characterized in that, The second semiconductor layer has a first voltage source supplied with the first voltage and a second voltage source supplied with the second voltage.

9. The imaging element according to claim 8, characterized in that, The first voltage source supplies a voltage above the ground voltage. The second voltage source supplies a voltage less than the ground voltage.

10. The imaging element according to claim 9, characterized in that, The supply unit is configured for each pixel.

11. The imaging element according to claim 10, characterized in that, The supply section of some of the pixels will supply a signal for resetting the charge generated by the photoelectric conversion unit during the first period to the reset section, while the supply section of other pixels will supply a signal for resetting the charge generated by the photoelectric conversion unit during a second period of a different length than the first period to the reset section.

12. The imaging element according to claim 10, characterized in that, It has multiple supply units, The timing of the signal supplied to the reset unit for resetting the charge generated by the photoelectric conversion unit differs between the supply units of some pixels and the supply units of other pixels.

13. The imaging element according to claim 1, characterized in that, The supply unit has a level conversion circuit that converts a drive signal based on a third voltage that is above ground voltage and a fourth voltage that is above ground voltage and above the third voltage into a signal of the first voltage or a signal of the second voltage.

14. The imaging element according to claim 13, characterized in that, The level conversion circuit converts the driving signal into a signal with the first voltage when the driving signal is the third voltage, and converts the driving signal into a signal with the second voltage when the driving signal is the fourth voltage.

15. A camera device, characterized in that, The camera element is provided with any one of claims 1 to 14.

Images