Semiconductor structure and method for forming the same

Abstract

The present invention relates to a semiconductor structure and a method for forming the same, wherein a deep trench capacitor is formed in a substrate, a fin-shaped contact portion located above an internal electrode of the deep trench capacitor is connected to a fin on the surface of the substrate, at least one word line formed on the substrate is located on the internal electrode via a word line isolation layer, the word line isolation layer covers the internal electrode between the buried oxide layer and the fin contact portion and exposes the fin, the word line isolation layer not only serves to insulate and isolate the word line and the internal electrode, but also prevents the internal electrode between the buried oxide layer and the fin contact portion from being exposed and forming epitaxial growth during an epitaxial process, thereby improving the reliability of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] DRAM (dynamic random access memory) is a key memory in precision computing systems. Driven by size reduction and advanced chip design, it is developing towards high speed, high density and low power consumption. For example, eDRAM (embedded DRAM) is embedded in chips with logic functions and can replace traditional SRAM (static random access memory) in some situations to reduce power consumption.

[0003] Deep trench capacitors and stacked capacitors are the two most important DRAM capacitor technologies. Among them, the deep trench of the deep trench capacitor can be formed before the CMOS transistor is constructed, which is more suitable for the integration of eDRAM and logic. When making deep trench capacitors and CMOS transistors, a deep trench can be formed in the substrate first, and the internal electrode of the capacitor can be formed in the deep trench. Then the CMOS transistor can be made so that one source and drain region of the CMOS transistor is connected to the internal electrode of the deep trench capacitor. However, the existing process is prone to defects at the opening of the deep trench, which affects the performance of the device. For example, after the internal electrode of the capacitor is formed in the deep trench and the gate of the CMOS transistor and the sidewalls located on the side of the gate are formed outside the deep trench, the surface of the internal electrode (for example, doped polysilicon) is exposed. When the source and drain epitaxial process of the CMOS transistor is subsequently performed, the exposed surface of the internal electrode also forms an epitaxial structure, and the epitaxial structure partially formed on the surface of the internal electrode is easy to touch the electrical structure on the substrate that should be isolated from the internal electrode (such as the source and drain epitaxial structure of another CMOS transistor), causing the device to short circuit.

[0004] Therefore, the reliability of current eDRAM technology is low and needs to be improved. Summary of the Invention

[0005] In order to improve the existing eDRAM technology, the present invention provides a method for forming a semiconductor structure and a semiconductor structure.

[0006] In one aspect, the present invention provides a method for forming a semiconductor structure, the method comprising:

[0007] Providing a substrate, the substrate comprising a doped substrate layer, a buried oxide layer located on the doped substrate layer, and a device layer located on the buried oxide layer;

[0008] forming a deep trench in the substrate, the deep trench penetrating the device layer and the buried oxide layer and extending into the doped substrate layer;

[0009] forming a deep trench capacitor in the deep trench, the deep trench capacitor comprising a node dielectric layer covering a portion of an inner surface of the deep trench and an inner electrode filled in the deep trench, the node dielectric layer separating the inner electrode from the doped substrate layer;

[0010] Etching the device layer and the internal electrode to expose the buried oxide layer thereunder, wherein the etched device layer forms a fin, and a portion of the etched internal electrode forms a fin-shaped contact portion connected to the fin;

[0011] forming a word line isolation layer on the substrate, wherein the word line isolation layer exposes the fin;

[0012] forming word lines on the substrate, wherein at least one word line intersects the fin and forms a gate of a transistor on a surface of the fin, and at least one word line is separated from the word line isolation layer and is located on the internal electrode;

[0013] forming sidewall spacers on both sides of the word line so that the word line isolation layer covers the internal electrode surface between the buried oxide layer and the fin contact portion; and

[0014] An epitaxial process is performed to form source and drain epitaxial structures on the surfaces of the fins on both sides of the gate.

[0015] In one aspect, the present invention provides a semiconductor structure comprising:

[0016] A substrate comprising a doped substrate layer, a buried oxide layer on the doped substrate layer, and a device layer on the buried oxide layer, wherein the device layer is formed into a fin;

[0017] a deep trench capacitor formed in the substrate, the deep trench capacitor comprising an internal electrode formed in a deep trench of the substrate and a node dielectric layer between the internal electrode and the doped substrate layer, the deep trench and the internal electrode penetrating the device layer and the buried oxide layer and extending deep into the doped substrate layer, the internal electrode having a fin-shaped contact portion connected to the fin;

[0018] word lines formed on the substrate, at least one of the word lines intersecting the fin and forming a gate of a transistor on the surface of the fin, with both sides of the word line being covered by sidewalls;

[0019] a word line isolation layer formed on the substrate, wherein at least one word line is spaced apart from the word line isolation layer and is located on the internal electrode, the word line isolation layer covers the surface of the internal electrode between the buried oxide layer and the fin contact portion and exposes the fin; and

[0020] Source and drain epitaxial structures are respectively formed on the surfaces of the fins on both sides of the gate.

[0021] In the semiconductor structure and the method for forming the semiconductor structure provided by the present invention, a deep trench capacitor is formed in the substrate, and a fin-shaped contact portion located on the upper portion of the internal electrode of the deep trench capacitor is connected to the fin formed by the device layer. At least one word line formed on the substrate is spaced apart, and the word line isolation layer is located on the internal electrode. The word line isolation layer covers the internal electrode between the buried oxide layer and the fin contact portion and exposes the fin. The word line isolation layer can not only insulate and isolate the word line and the internal electrode, but also can avoid the internal electrode between the buried oxide layer and the fin contact portion from being exposed to form epitaxial growth during the epitaxial process, which helps to improve the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A FIG. 1 is a plan view of a deep trench capacitor formed in a substrate and fins and fin-shaped contacts formed in accordance with an embodiment of the present invention.

[0023] Figure 1B It is a schematic cross-sectional view along line AA' in FIG1 .

[0024] Figure 1C It is a schematic cross-sectional view along line BB' in FIG1 .

[0025] Figure 2 FIG. 1 is a schematic diagram of performing ion implantation on the upper portion of the internal electrode according to an embodiment of the present invention.

[0026] Figure 3 FIG. 1 is a plan view of forming a word line isolation layer on a substrate in one embodiment of the present invention.

[0027] Figure 4 FIG. 1 is a plan view of forming a word line isolation layer on a substrate in another embodiment of the present invention.

[0028] Figure 5 FIG. 1 is a cross-sectional diagram of forming a word line isolation layer on a substrate in one embodiment of the present invention.

[0029] Figure 6 FIG. 1 is a cross-sectional diagram of forming a word line isolation layer on a substrate in another embodiment of the present invention.

[0030] Figure 7A FIG. 1 is a plan view of forming word lines on a substrate according to an embodiment of the present invention.

[0031] Figure 7B yes Figure 7A Schematic cross-section of line DD'.

[0032] Figure 8AFIG. 1 is a plan view of a sidewall spacer formed on both sides of a word line according to an embodiment of the present invention.

[0033] Figure 8B yes Figure 8A Schematic cross-section of line EE'.

[0034] Figure 9A It is a plan view schematically showing a state in which source and drain epitaxial structures are formed on the surfaces of the fins on both sides of the word line in one embodiment of the present invention.

[0035] Figure 9B yes Figure 9A Schematic cross-section of line EE'.

[0036] Figure 9C yes Figure 9A Schematic cross-section of line FF'.

[0037] 10A to 10C FIG. 4 is a cross-sectional diagram of forming a word line isolation layer on a substrate in another embodiment of the present invention.

[0038] Figure 11 FIG. 1 is a cross-sectional diagram of forming word lines and spacers on a substrate in another embodiment of the present invention.

[0039] Figure 12A It is a cross-sectional schematic diagram in one direction after source and drain epitaxial structures are respectively formed on the surfaces of the fins on both sides of the gate in another embodiment of the present invention.

[0040] Figure 12B It is a cross-sectional schematic diagram in another direction after source and drain epitaxial structures are respectively formed on the surfaces of the fins on both sides of the gate in another embodiment of the present invention. DETAILED DESCRIPTION

[0041] The semiconductor structure and the method for forming the same of the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the drawings in the specification are all in a very simplified form and are not in precise proportions, and are only used to facilitate and clearly assist in illustrating the purpose of the embodiments of the present invention. In addition, spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the structure in the drawing is inverted or positioned in other different ways (such as rotated), the exemplary term "on..." may also include "under..." and other orientation relationships.

[0042] An embodiment of the present invention relates to a method for forming a semiconductor structure. The formation method can be used to manufacture eDRAM. The eDRAM uses deep trench capacitors to provide large capacitance. In the formation method, a passing wordline above the deep trench capacitor is isolated from the internal electrode of the deep trench capacitor by forming a wordline isolation layer. The wordline isolation layer is also used to cover at least the surface of the internal electrode in the same deep trench around the fin contact end during the epitaxial process to control the epitaxial growth area of ​​the internal electrode surface, prevent the epitaxial structure formed on the internal electrode surface from touching the electrical structure on the substrate that should be isolated from the internal electrode, and cause a short circuit, thereby helping to improve the reliability and performance of the semiconductor structure.

[0043] Figure 1A FIG. 1 is a plan view of a deep trench capacitor formed in a substrate and fins and fin-shaped contacts formed in accordance with an embodiment of the present invention. Figure 1B It is a schematic cross-sectional view along line AA' in FIG1 . Figure 1C It is a cross-sectional schematic diagram of line BB' in Figure 1. Figures 1A to 1C As shown, in a method for forming a semiconductor structure according to an embodiment of the present invention, a substrate 10 is first provided. The substrate 10 includes a doped substrate layer 101, a buried oxide layer 102 located on the doped substrate layer 101, and a device layer 103 located on the buried oxide layer 102. In one embodiment, the substrate 10 is a silicon-on-insulator (SOI) substrate. The doped substrate layer 101 is, for example, an N-type heavily doped silicon substrate, the buried oxide layer 102 is, for example, a silicon oxide layer, and the device layer 103 is, for example, a P-type silicon layer. The thickness of the doped substrate layer 101 is, for example, in the range of 50 μm to 500 μm, the thickness of the buried oxide layer 102 is, for example, in the range of 100 nm to 500 nm, and the thickness of the device layer 103 is, for example, in the range of 50 nm to 500 nm, but are not limited thereto.

[0044] like Figures 1A to 1CAs shown, a deep trench capacitor TC is formed in a substrate 10. The process of forming the deep trench capacitor TC includes, for example: forming a deep trench DT in the substrate 10 by a photolithography process and an etching process, wherein the deep trench DT penetrates the device layer 103 and the buried oxide layer 102 and can extend to a predetermined depth (for example, several microns) in the doped substrate layer 101; forming a deep trench capacitor in the deep trench DT, first forming a node dielectric layer 201 in the deep trench DT, wherein the node dielectric layer 201 conformally covers the surface of the doped substrate layer 101 exposed by the deep trench DT and can cover a portion of the surface of the buried oxide layer 102 exposed by the deep trench DT; and then forming a node dielectric layer 201 in the deep trench DT. To form the internal electrode IE, for example, a barrier layer 202 is first formed in the deep trench DT. The barrier layer 202 may include titanium nitride (TiN), tantalum nitride (TaN) or other metals with low ohmic contact resistance. The barrier layer 202 is formed along the surface of the node dielectric layer 201, and the top of the barrier layer 202 may be lower than the top of the node dielectric layer 201. Then, a doped polysilicon layer 203 is deposited to fill the deep trench DT. Then, the doped polysilicon layer 203 outside the deep trench DT is removed by an etch-back process or a planarization process. The barrier layer 202 and the doped polysilicon layer 203 in the deep trench DT form the internal electrode IE.

[0045] In this embodiment, the internal electrode IE penetrates the device layer 103 and the buried oxide layer 102 in the substrate 10 and penetrates into the doped substrate layer 101. The deep trench capacitor TC includes a deep trench DT, a node dielectric layer 201 covering a portion of the inner surface of the deep trench DT, and the internal electrode IE. The doped substrate layer 101 serves as the other electrode (or external electrode) of the deep trench capacitor TC.

[0046] like Figures 1A to 1C As shown, the device layer 103 in the substrate 10 and the internal electrode IE in the deep trench TC are etched to perform patterning on the device layer 103 and the internal electrode IE to expose the buried oxide layer 102. During the etching process, part of the buried oxide layer 102 may also be removed. After etching, the device layer 103 forms a fin 103a, and a part of the internal electrode IE forms a fin-shaped contact portion 203a connected to the fin 103a.

[0047] In order to reduce the contact resistance between the fin contact portion 203a and the doped region of the transistor to be formed subsequently, refer to Figure 2 (and Figure 1B(The cross-sectional position shown is the same as that shown in FIG. 3 ). Optionally, after forming the deep trench capacitor TC and before or after forming the fin 103 a, ion implantation can be performed using a photoresist as a mask to form a highly doped region 203 b on top of the internal electrode IE. This increases the ion doping concentration of the fin contact 203 a, thereby helping to reduce the contact resistance. The depth of the highly doped region 203 b is, for example, less than or equal to the thickness of the device layer 103.

[0048] Then, a word line isolation layer is formed on the substrate 10. The word line isolation layer is used to insulate and isolate the internal electrode IE from the word line subsequently formed on the substrate 10, and to prevent the internal electrode IE from short-circuiting with other subsequently formed electrical components (such as the source and drain epitaxial structures of transistors) that should be isolated from it. Figure 3 As shown, in one embodiment, the word line isolation layer 30 covers the top surface of the substrate 10 after the fin 103a and the fin contact portion 203a are formed, and the opening in the word line isolation layer 30 exposes the fin 103a and a portion of the surrounding area. Figure 4 As shown in FIG. 1 , in another embodiment, the word line isolation layer 30 is formed corresponding to the deep trench capacitor TC and the buried oxide layer 102 around the deep trench capacitor TC, while the fin 103a and other areas on the substrate 10 are exposed. Figure 4 The structure shown is used as an example for explanation.

[0049] Figure 5 and Figure 6 For example, along Figure 4 The cross section taken from CC'. Figure 5 and Figure 6 The word line isolation layer 30 is formed on the surface of the buried oxide layer 102, the surface of the fin contact 203a, and the surface of the internal electrode IE between the buried oxide layer 102 and the fin contact 203a (that is, the surface of the internal electrode IE in the same deep trench DT around the fin contact 203a) is covered by the word line isolation layer 30, and the word line isolation layer 30 exposes the fin 103a.

[0050] The word line isolation layer 30 comprises, for example, multiple layers of material, one of which is a high-k dielectric layer 302. The technical effect is that, in the subsequent etching process for forming the sidewall, the high-k dielectric layer 302 can be used to protect the internal electrode IE between the fin contact portion 203a and the buried oxide layer 102, thereby preventing this portion of the internal electrode IE from being exposed and causing reliability problems. The dielectric constant of the high-k dielectric layer 302 is, for example, greater than 3.9. Specifically, the high-k dielectric layer 302 comprises, for example, HfO, HfSiO xand Al2O3, which have good etching selectivity with silicon oxide and silicon nitride. However, the present invention is not limited to using the high-k dielectric layer 302 to protect the internal electrode IE from exposure, and other materials can also be used.

[0051] like Figure 5 As shown, the word line isolation layer 30 may include a bottom dielectric layer 301 and a high-k dielectric layer 302 stacked on the surface of the bottom dielectric layer 301. The bottom dielectric layer 301 is, for example, an ONO (silicon oxide-silicon nitride-silicon oxide) layer or a silicon oxide layer. Figure 6 As shown, in one embodiment, the word line isolation layer 30 includes a bottom dielectric layer 301, a high-k dielectric layer 302 stacked on the bottom dielectric layer 301, and a top dielectric layer 303 stacked on the high-k dielectric layer 302. The bottom dielectric layer 301 and the top dielectric layer 303 are made of silicon oxide, for example. Figure 5 The structure shown is used as an example for explanation.

[0052] Exemplarily, forming the wordline isolation layer 30 on the substrate 10 includes the following steps: forming a multi-layer dielectric film on the substrate 10; removing portions of the multi-layer dielectric film, and using the remaining portions of the multi-layer dielectric film as the wordline isolation layer 30. In the wordline isolation layer 30 obtained through this process, the coverage of each layer of dielectric material is substantially the same. When removing portions of the multi-layer dielectric film, the top dielectric layer can be patterned using a photolithography process and a dry or wet etching process. The patterned top dielectric layer is then used as a mask to dry or wet etch the underlying dielectric film. During this process, the buried oxide layer 102 surrounding the fin 103a and the deep trench capacitor TC may also be etched.

[0053] Figure 7A FIG. 1 is a plan view of forming word lines on a substrate according to an embodiment of the present invention. Figure 7B yes Figure 7A Schematic diagram of the cross section along the DD' line. Figure 7A and Figure 7B Then, word lines WL are formed on the substrate 10, wherein at least one word line WL intersects the fin 103a and forms a gate of a transistor on the surface of the fin 103a, and at least one word line WL is spaced apart from the word line isolation layer 30 and is located on the internal electrode IE. Figure 7A The dotted box in the middle shows two word lines WL. The word line isolation layer 30 insulates the word line WL from the internal electrode IE. The material of the word line WL is, for example, polysilicon, which can be formed by depositing a polysilicon layer and etching the polysilicon layer. When etching the polysilicon layer, a hard mask (such as Figure 7BBefore forming word lines WL on the substrate 10, a gate dielectric layer (not shown) may be formed on the fins 103a.

[0054] In one embodiment, the word line WL formed here is a dummy word line (dummyWL). After forming sidewalls and source-drain epitaxial structures on both sides of the word line WL, the word line WL can be removed to form a gate deep trench, and a replacement metal gate (RMG) process is used to form a metal word line in the gate deep trench.

[0055] Figure 8A FIG. 1 is a plan view of a sidewall spacer formed on both sides of a word line according to an embodiment of the present invention. Figure 8B yes Figure 8A Schematic diagram of the cross section along line EE'. Figure 8A and Figure 8B , forming spacers SP on both sides of the word line WL, and the word line isolation layer 30 still covers the surface of the internal electrode IE between the buried oxide layer 102 and the fin contact 203a. Exemplarily, forming the spacers SP includes the following process: conformally depositing a silicon oxide layer on the top surface of the substrate 10 after the word line WL is formed; then, etching the silicon oxide layer using an anisotropic etching process to expose the silicon oxide hard mask HM2 and the top surface of the fin 103a. The remaining silicon oxide layer covers both sides of the word line WL, forming the spacers SP.

[0056] like Figure 8B As shown, during the formation of the sidewall spacer SP, the wordline isolation layer 30 can protect the internal electrode IE. In particular, because the wordline isolation layer 30 covers the surface of the internal electrode IE between the buried oxide layer 102 and the fin contact 203a, it insulates the wordline WL from the internal electrode IE while preventing the internal electrode IE located between the buried oxide layer 102 and the fin contact 203a from being exposed. This prevents subsequent epitaxial growth on this portion of the internal electrode IE, which could affect the reliability of the semiconductor structure. According to some embodiments of the present invention, the wordline isolation layer 30 utilizes a high-k dielectric layer 302 that has excellent selectivity with the sidewall spacer SP material, thereby preventing etching of the wordline isolation layer 30 during the sidewall spacer process. After the sidewall spacer SP is formed, source and drain ion implantation can be performed on the fins on both sides of the wordline WL to form the source and drain regions of the transistor on the surface of the fin 103a.

[0057] Figure 9A FIG. 1 is a cross-sectional view of an embodiment of the present invention after forming source and drain epitaxial structures on the fin surfaces on both sides of the word line. Figure 9AAs shown, an epitaxial process is then performed to form source-drain epitaxial structures 40 on the surfaces of the fins 103a on both sides of the word line. Each source-drain epitaxial structure 40 is connected to the source region or drain region on the side of the word line, which can increase the range of the source region and drain region of the transistor on the surface of the fin 103a.

[0058] Figure 9B yes Figure 9A Schematic cross-section of line FF'. Figure 9C yes Figure 9A Schematic diagram of the cross section of the GG' line. Figures 9A to 9C In one embodiment, before the epitaxial growth process is performed, except for the top surface of the internal electrode IE between the fin contact 203a and the buried oxide layer 102 (i.e., the internal electrode IE in the same deep trench DT around the fin contact 203a) being covered by the word line isolation layer 30, the top surface of the fin contact 203a on the side in contact with the fin 103 and where the word line WL and the sidewall SP are not formed is also almost entirely covered by the word line isolation layer 30. Therefore, on the one hand, since the top surface of the internal electrode IE in the same deep trench DT around the fin contact 203a is covered by the word line isolation layer 30, epitaxial growth will not form in these areas during the epitaxial growth process, which can avoid the internal electrode IE being exposed and causing the formation of difficult-to-control Epitaxial growth may cause the aforementioned short-circuit problem. Furthermore, the top surface of the fin contact 203a, which contacts the side of the fin 103 and is not formed with the word line WL and sidewall spacer SP, is almost entirely covered by the word line isolation layer 30. This results in a smaller epitaxial growth area on the top surface of the fin contact 203a connected to the source-drain epitaxial structure 40, which is not conducive to improving the current collection capability of the internal electrode IE. For example, in an eDRAM, covering the top surface of the fin contact 203a connected to the source-drain epitaxial structure 40 with the word line isolation layer 30 reduces the drain saturation current Idsat of the transistor, compared to allowing more epitaxial growth on the top surface of the fin contact 203a connected to the source-drain epitaxial structure 40. To improve the current collection capability of the internal electrode IE, the extent of the word line isolation layer 30 covering the top surface of the fin contact 203a connected to the source-drain epitaxial structure 40 needs to be reduced.

[0059] 10A to 10C FIG. 1 is a cross-sectional view of forming a word line isolation layer on a substrate in another embodiment of the present invention. Specifically, Figure 10A Shown in the formation of Figure 5 The cross section of the substrate 10 after a planarization layer 304 is formed on the basis of the patterned multi-layer dielectric film shown. Figure 10A According to another embodiment, when forming Figure 5Based on the patterned multilayer dielectric film shown, a planarization layer 304 is formed on the multilayer dielectric film. For example, a planarization material is first applied to the substrate 10 and the deep trench capacitor TC, and then the planarization material is etched back to form the planarization layer 304. The top surface of the resulting planarization layer 304 is lower than the top surfaces of the fin 103a and the fin contact 203a. The planarization layer 304 covers the multilayer dielectric film located between the buried oxide layer 102 and the fin contact 203a, leaving the portion of the multilayer dielectric film located on the top surface of the fin contact 203a exposed.

[0060] Figure 10B Shown in Figure 10A The cross section after selectively etching the word line isolation layer 30 based on the reference Figure 10B , using the planarization layer 304 as a mask, etching away the exposed high-k dielectric layer 302 in the word line isolation layer 30 . Figure 10C Shown in Figure 10B The cross section after removing the planarization layer 304. Figure 10C , and then remove the planarization layer 304. In this embodiment, 10A to 10C The multi-layer dielectric film processed as shown serves as a word line isolation layer 30 .

[0061] Through the above process, the number of dielectric layers stacked in different areas of the word line isolation layer 30 varies. For example, the word line isolation layer 30 located on the top surface of the fin contact 203a is an ONO layer, while the word line isolation layer 30 located on the top surface of the internal electrode IE between the fin contact 203a and the buried oxide layer 102 includes an ONO layer and a high-k dielectric layer 302 stacked on the ONO layer. Compared to the word line isolation layer 30 covering the top surface of the internal electrode IE within the same deep trench DT surrounding the fin contact 203a, the word line isolation layer 30 covering the top surface of the fin contact 203a is thinner, resulting in a poorer etch selectivity with the spacer material.

[0062] Figure 11 FIG. 1 is a cross-sectional diagram of forming word lines and sidewalls on a substrate in another embodiment of the present invention. Figure 11 According to yet another embodiment, Figure 10C Based on the structure shown, word lines WL are formed on the substrate 10. At least one word line WL intersects the fin 103a and forms the gate of the transistor on the surface of the fin 103a. At least one word line WL is located on the internal electrode IE, separated by a word line isolation layer 30. The word line isolation layer 30 insulates the word line WL from the internal electrode IE. Before forming the word line WL on the substrate 10, a gate dielectric layer (not shown) can be formed on the fin 103a.

[0063] Furthermore, spacers SP are formed on both sides of the word line WL, and the word line isolation layer 30 still covers the surface of the internal electrode IE between the buried oxide layer 102 and the fin contact 203a. The process for forming the word line WL and the spacer SP can refer to the previous embodiment. In this embodiment, due to the poor etch selectivity between the word line isolation layer 30 and the spacer SP material located on the top surface of the fin contact 203a, the word line isolation layer 30 on the top surface of the fin contact 203a in contact with the fin 103, where the word line WL and spacer SP are not formed, is removed during the etching process for forming the spacer SP, leaving the top surface of the fin contact 203a in contact with the fin 103 fully exposed. Furthermore, the word line isolation layer 30 covering the top surface of the internal electrode IE within the same deep trench DT surrounding the fin contact 203a has a good etch selectivity with the spacer material, and this portion of the word line isolation layer 30 remains after the spacer SP is formed.

[0064] Figure 12A It is a cross-sectional schematic diagram in one direction after source and drain epitaxial structures are respectively formed on the surfaces of the fins on both sides of the gate in another embodiment of the present invention. Figure 12B It is a cross-sectional schematic diagram in another direction after source and drain epitaxial structures are respectively formed on the surfaces of the fins on both sides of the gate in another embodiment of the present invention. Figure 12A and Figure 11 The cross-sections shown are at the same location, Figure 12B For example, the Figure 12A The middle HH' line is intercepted and Figure 12A The cross section shown is perpendicular to the cross section. Figure 12A and Figure 12B ,exist Figure 11Based on the structure shown, an epitaxial process is then performed to form source and drain epitaxial structures 40 on the surfaces of the fins 103a on both sides of the word line. Each source and drain epitaxial structure 40 is connected to the source region or drain region on the side of the word line. In this embodiment, since the word line isolation layer 30 on the top surface of the fin contact portion 203a on the side in contact with the fin 103 and where the word line WL and the side wall SP are not formed is removed, during the epitaxial growth process, the top surface of the fin contact portion 203a on the side in contact with the fin 103 and the portion of the side surface of the fin contact portion 203a connected to the top surface form epitaxial growth, so that the contact area between the fin contact portion 203a and the corresponding source region or drain region of the connected transistor is increased, and the contact resistance is reduced, which is beneficial to improving the current collection capability of the internal electrode IE and increasing the drain saturation current Idsat of the eDRAM. In addition, since the internal electrode IE in the same deep trench DT around the fin contact portion 203a is covered by the word line isolation layer 30, the epitaxial growth area of ​​the internal electrode is effectively controlled, which can prevent the epitaxial structure formed on the surface of the internal electrode from being connected to the electrical structure that should be isolated from the internal electrode IE (such as the source and drain epitaxial structure of other transistors) to cause a short circuit, thereby affecting the reliability of the device.

[0065] Embodiments of the present invention also relate to a semiconductor structure. The semiconductor structure is used, for example, in a device using eDRAM. The semiconductor structure can be fabricated using the semiconductor structure forming method described in the above embodiment.

[0066] Refer to Figures 1 to Figure 12B , the semiconductor structure comprises:

[0067] A substrate 10 comprising a doped substrate layer 101, a buried oxide layer 102 on the doped substrate layer 101, and a device layer 103 on the buried oxide layer 102, wherein the device layer 103 is formed into fins 103a;

[0068] a deep trench capacitor TC formed in the substrate 10, the deep trench capacitor TC comprising an internal electrode IE formed in a deep trench DT of the substrate 10 and a node dielectric layer 201 between the internal electrode IE and the doped substrate layer 101, the deep trench DT and the internal electrode IE penetrating the device layer 103 and the buried oxide layer 102 and extending deep into the doped substrate layer 101, the internal electrode IE having a fin-shaped contact portion 203a connected to the fin 103a;

[0069] Word lines WL are formed on the substrate 10 . At least one word line WL intersects the fin 103 a and forms a gate of a transistor on the surface of the fin 103 a . Both sides of the word line WL are covered by spacers SP.

[0070] a word line isolation layer 30 formed on the substrate 10, with at least one word line WL separating the word line isolation layer 30 and located on the internal electrode IE; the word line isolation layer 30 covers the surface of the internal electrode IE between the buried oxide layer 102 and the fin contact 203a and exposes the fin 103a; and

[0071] The source-drain epitaxial structures 40 are respectively formed on the surfaces of the fins 103 a on both sides of the word line WL.

[0072] In the semiconductor structure, the word line isolation layer 30 not only isolates the word line WL and the internal electrode IE, thereby insulating the word line WL and the internal electrode IE, but also covers the surface of the internal electrode IE between the buried oxide layer 102 and the fin contact portion 203a, thereby protecting this portion of the internal electrode IE from being exposed. During the epitaxial growth process, the epitaxial structure formed on the surface of the internal electrode is prevented from being connected to the electrical structure that should be isolated from the internal electrode IE (such as the source-drain epitaxial structure of other transistors), thereby preventing a short circuit and thus affecting the reliability of the device.

[0073] The internal electrode IE may include, for example, doped polysilicon. In one embodiment, the internal electrode IE is made of doped polysilicon, and the fin contact portion 203a may have a higher doping concentration than other regions of the internal electrode IE. In one embodiment, the word line WL may include polysilicon or metal. A gate dielectric layer (not shown) may be formed between the word line WL and the fin 103a, with the sides of the gate dielectric layer covered by sidewall spacers SP.

[0074] Optionally, the wordline isolation layer 30 includes a bottom dielectric layer 301 and a high-k dielectric layer 302 stacked on the bottom dielectric layer 301. The bottom dielectric layer 301 is, for example, an ONO layer or a silicon oxide layer. The wordline isolation layer 30 may further include a top silicon oxide layer stacked on the high-k dielectric layer 302.

[0075] Furthermore, in some embodiments, the word line isolation layer 30 also covers at least a portion of the top surface of the fin contact 203a, and the structure of the word line isolation layer 30 on the top surface of the fin contact 203a is different from that of the word line isolation layer 30 covering the surface of the internal electrode IE between the buried oxide layer 102 and the fin contact 203a. The word line isolation layer 30 located on the top surface of the fin contact 203a includes a bottom dielectric layer 301 (for example, an ONO layer or a silicon oxide layer) but does not include a high-k dielectric layer 302, while the word line isolation layer 30 located on the surface of the internal electrode IE between the buried oxide layer 102 and the fin contact 203a includes a bottom dielectric layer 301 and a high-k dielectric layer. The high-k dielectric layer 302, that is, the dielectric layer below the high-k dielectric layer 302 in the word line isolation layer 30, also extends to cover at least a portion of the top surface of the fin contact 203a, to ensure that the surface of the internal electrode IE between the buried oxide layer 102 and the fin contact 203a is not exposed during the spacer process. At the same time, the top surface of the fin contact 203a on the side in contact with the fin 103a and where the word line WL and the spacer SP are not formed is exposed, so that an epitaxial structure connected to the source-drain epitaxial structure is formed on the top surface of the fin contact 203a on the side in contact with the fin 103a, which can improve the current collection capability of the internal electrode IE and increase the drain saturation current Idsat of the eDRAM.

[0076] It should be noted that the embodiments in this specification are described in a progressive manner. For the semiconductor structure in the embodiment, the formation method of the semiconductor structure disclosed in the other embodiments corresponds to it, so the description is less. For relevant points, please refer to the formation method of the semiconductor structure in the embodiment.

[0077] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a doped substrate layer, a buried oxide layer located on the doped substrate layer, and a device layer located on the buried oxide layer; forming a deep trench in the substrate, the deep trench penetrating the device layer and the buried oxide layer and extending into the doped substrate layer; forming a deep trench capacitor in the deep trench, the deep trench capacitor comprising a node dielectric layer covering a portion of an inner surface of the deep trench and an inner electrode filled in the deep trench, the node dielectric layer separating the inner electrode from the doped substrate layer; Etching the device layer and the internal electrode to expose the buried oxide layer thereunder, wherein the etched device layer forms a fin, and a portion of the etched internal electrode forms a fin-shaped contact portion connected to the fin; forming a word line isolation layer on the substrate, wherein the word line isolation layer exposes the fin; forming word lines on the substrate, wherein at least one word line intersects the fin and forms a gate of a transistor on a surface of the fin, and at least one word line is separated from the word line isolation layer and is located on the internal electrode; forming sidewall spacers on both sides of the word line so that the word line isolation layer covers the surface of the internal electrode between the buried oxide layer and the fin contact portion; as well as An epitaxial process is performed to form source and drain epitaxial structures on the surfaces of the fins on both sides of the gate.

2. The forming method according to claim 1, wherein: Forming the word line isolation layer on the substrate includes: forming a multi-layer dielectric film on the substrate, the multi-layer dielectric film comprising a bottom dielectric layer and a high-k dielectric layer stacked on the bottom dielectric layer; as well as The multi-layer dielectric film in a partial area is removed, and the remaining multi-layer dielectric film is used as the word line isolation layer.

3. The forming method according to claim 2, wherein: After removing the multilayer dielectric film in a portion of the area, forming the word line isolation layer on the substrate further comprises: forming a planarization layer on the multilayer dielectric film, wherein a top surface of the planarization layer is lower than top surfaces of the fin and the fin-shaped contact portion, the planarization layer covers the multilayer dielectric film located between the buried oxide layer and the fin contact portion, and a portion of the multilayer dielectric film located on the top surface of the fin contact portion is exposed; removing the high-k dielectric layer in a portion of the multilayer dielectric film located on a top surface of the fin-shaped contact portion; and The planarization layer is removed.

4. The forming method according to claim 2, wherein: The multi-layer dielectric film includes an ONO layer and the high-k dielectric layer stacked on the ONO layer.

5. The forming method according to claim 2, wherein: The multi-layer dielectric film includes a silicon oxide layer and the high-k dielectric layer stacked on the silicon oxide layer.

6. The forming method according to claim 2, wherein: The multi-layer dielectric film includes a bottom silicon oxide layer, the high-k dielectric layer stacked on the bottom silicon oxide layer, and a top silicon oxide layer stacked on the high-k dielectric layer.

7. The forming method according to claim 1, wherein: The internal electrode includes doped polysilicon.

8. The forming method according to claim 7, wherein: After forming the deep trench capacitor and before forming the fin or after forming the fin, the forming method further includes: Ion implantation is performed to increase the ion doping concentration of the fin-shaped contact portion.

9. A semiconductor structure, characterized in that include: A substrate comprising a doped substrate layer, a buried oxide layer on the doped substrate layer, and a device layer on the buried oxide layer, wherein the device layer is formed into a fin; a deep trench capacitor formed in the substrate, the deep trench capacitor comprising an internal electrode formed in a deep trench of the substrate and a node dielectric layer between the internal electrode and the doped substrate layer, the deep trench and the internal electrode penetrating the device layer and the buried oxide layer and extending deep into the doped substrate layer, the internal electrode having a fin-shaped contact portion connected to the fin; word lines formed on the substrate, at least one of the word lines intersecting the fin and forming a gate of a transistor on the surface of the fin, with both sides of the word line being covered by sidewalls; a word line isolation layer formed on the substrate, wherein at least one word line is spaced apart from the word line isolation layer and is located on the internal electrode, the word line isolation layer covers the surface of the internal electrode between the buried oxide layer and the fin contact portion and exposes the fin; and Source and drain epitaxial structures are respectively formed on the surfaces of the fins on both sides of the gate.

10. The semiconductor structure according to claim 9, wherein: The internal electrode includes doped polysilicon.

11. The semiconductor structure according to claim 9, wherein: The word line isolation layer includes an ONO layer and a high-k dielectric layer stacked on the ONO layer.

12. The semiconductor structure according to claim 9, wherein The word line isolation layer includes a silicon oxide layer and a high-k dielectric layer stacked on the silicon oxide layer.

13. The semiconductor structure according to claim 9, wherein: The word line isolation layer includes a bottom silicon oxide layer, a high-k dielectric layer stacked on the bottom silicon oxide layer, and a top silicon oxide layer stacked on the high-k dielectric layer.

14. The semiconductor structure according to any one of claims 11 to 13, wherein: In the word line isolation layer, the dielectric layer located below the high-k dielectric layer further extends to cover at least a portion of the top surface of the fin-shaped contact portion.

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