Thin-film capacitors and electronic circuit boards incorporating them

Abstract

The present invention provides a thin-film capacitor with high adhesion to a circuit board. The thin-film capacitor (1) comprises: a metal foil (10) having a roughened upper surface (11); a dielectric film (D) covering the upper surface (11) of the metal foil (10) and having an opening that partially exposes the metal foil (10); a first electrode layer connected to the metal foil (10) via the opening; and a second electrode layer connected to the dielectric film (D) but not connected to the metal foil (10). The first and second electrode layers do not cover the outer peripheral region (15) of the upper surface (11) of the metal foil (10), but are formed in the region surrounded by the outer peripheral region (15). In this way, the outer peripheral region (15) of the roughened upper surface (11) of the metal foil (10) is exposed, thereby increasing the adhesion to the circuit board.

Description

Technical Field

[0001] The present invention relates to thin film capacitors and electronic circuit boards having the same, and particularly to thin film capacitors using metal foil and electronic circuit boards having the same. Background Technology

[0002] In the circuit board on which an IC is mounted, decoupling capacitors are typically mounted to stabilize the potential of the power supplied to the IC. Multilayer ceramic chip capacitors are commonly used as decoupling capacitors, with multiple multilayer ceramic chip capacitors mounted on the surface of the circuit board, thereby ensuring the necessary decoupling capacitance.

[0003] In recent years, circuit boards have become miniaturized, sometimes resulting in insufficient space for mounting multiple stacked ceramic chip capacitors. Therefore, thin-film capacitors that can be embedded in the circuit board are sometimes used instead of stacked ceramic chip capacitors (see Patent Documents 1-4).

[0004] Patent Document 1 describes a thin-film capacitor with the following structure: a porous metal substrate is used, and an upper electrode is formed on its surface via a dielectric film. Patent Document 2 describes a thin-film capacitor with the following structure: a metal substrate with a roughened main surface is used, and an upper electrode is formed on the roughened surface via a dielectric film. Patent Documents 3 and 4 describe thin-film capacitors with the following structure: a conductive porous substrate is formed in the support portion, and an upper electrode is formed on the roughened surface via a dielectric film.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: International Publication No. WO2015-118901

[0008] Patent Document 2: International Publication No. WO2018-092722

[0009] Patent Document 3: International Publication No. WO2017-026247

[0010] Patent Document 4: International Publication No. WO2017-014020 Summary of the Invention

[0011] The problem that the invention aims to solve

[0012] However, the thin-film capacitor described in Patent Document 1 has a side electrode structure, resulting in a longer electrode line length. Therefore, it suffers from structural problems such as increased ESR (equivalent series resistance) and ESL (equivalent series inductance). Furthermore, because the thin-film capacitor described in Patent Document 1 uses a porous metal substrate, separating the lower electrode made of the metal substrate from the upper electrode covered by a dielectric film is difficult, leading to a tendency for short circuits. Additionally, the thin-film capacitor described in Patent Document 2 uses one main surface of the metal substrate as the upper electrode and the other as the lower electrode. To place a pair of terminal electrodes on the same surface, the electrodes need to be routed back through the side of the [0] element, resulting in a complex structure. Furthermore, the thin-film capacitors described in Patent Documents 3 and 4 place a pair of terminal electrodes on opposite sides of the metal substrate, preventing the connection of a pair of terminal electrodes from a single side. Moreover, the use of a support increases the overall thickness.

[0013] Therefore, the object of the present invention is to provide an improved thin-film capacitor and an electronic circuit board having the same.

[0014] Technical solutions for solving the problem

[0015] The present invention provides a thin-film capacitor comprising: a metal foil having a roughened main surface; a dielectric film covering a main surface of the metal foil and having an opening that partially exposes the metal foil; a first electrode layer in contact with the metal foil via the opening; and a second electrode layer in contact with the dielectric film but not with the metal foil, wherein the first and second electrode layers do not cover the outer peripheral region of a main surface of the metal foil, but are formed in a region surrounded by the outer peripheral region.

[0016] The present invention provides a method for manufacturing a thin-film capacitor, wherein a main surface of a metal foil is roughened, a dielectric film is formed on the roughened main surface of the metal foil, a portion of the metal foil is exposed by removing a portion of the dielectric film, and a first electrode layer in contact with a portion of the metal foil and a second electrode layer in contact with the dielectric film but not with a portion of the metal foil are formed in the area surrounded by the outer peripheral region of the main surface of the metal foil.

[0017] Invention Effects

[0018] According to the present invention, an opening is provided in a portion of the dielectric film, thus enabling a pair of terminal electrodes to be disposed on the same surface without the use of side electrodes or the like. Furthermore, since the outer peripheral region of one main surface of the metal foil is not covered by the first and second electrode layers, the adhesion to the circuit board is improved, and short circuits and open circuits are less likely to occur. Attached Figure Description

[0019] Figure 1A This is a general cross-sectional view illustrating the structure of a thin-film capacitor 1 according to an embodiment of the present invention. Figure 1B This is a rough top view of film capacitor 1.

[0020] Figure 1B This is a rough top view of film capacitor 1.

[0021] Figure 1C This is a rough cross-sectional view showing an example where the conductive component 32 is omitted from the film capacitor 1.

[0022] Figure 1D yes Figure 1C A general top view of the thin-film capacitor 1 shown.

[0023] Figure 2 This is a general cross-sectional view used to illustrate the shape of the side 13 of the film capacitor 1.

[0024] Figure 3 This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0025] Figure 4 This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0026] Figure 5A This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0027] Figure 5B This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0028] Figure 6 This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0029] Figure 7A This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0030] Figure 7B yes Figure 7A A rough top view.

[0031] Figure 8A This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0032] Figure 8B yes Figure 8A A rough top view.

[0033] Figure 9 This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0034] Figure 10 This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0035] Figure 11A This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0036] Figure 11B yes Figure 11A A rough top view.

[0037] Figure 12A This is a general cross-sectional view showing an example of the location where the insulating component 21 is formed.

[0038] Figure 12B This is a general cross-sectional view showing another example of the location where the insulating component 21 is formed.

[0039] Figure 13 This is a general cross-sectional view showing an example of the shape of the insulating component 21.

[0040] Figure 14A This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0041] Figure 14B yes Figure 14A A rough top view.

[0042] Figure 15A This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0043] Figure 15B yes Figure 15A A rough top view.

[0044] Figure 16A This is a schematic cross-sectional view showing the case where the crystal grain size of the metal foil 10 is relatively large.

[0045] Figure 16B yes Figure 16A A rough top view.

[0046] Figure 17A This is a schematic cross-sectional view showing the case where the crystal grain size of the metal foil 10 is small.

[0047] Figure 17B yes Figure 17A A rough top view.

[0048] Figure 18 This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0049] Figure 19 yes Figure 18 A rough top view.

[0050] Figure 20A This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0051] Figure 20B yes Figure 20A A rough top view.

[0052] Figure 21 This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0053] Figure 22A This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0054] Figure 22B yes Figure 22A A rough top view.

[0055] Figure 23A This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0056] Figure 23B yes Figure 23A A rough top view.

[0057] Figure 24A This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0058] Figure 24B yes Figure 24A A rough top view.

[0059] Figure 25A This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0060] Figure 25B yes Figure 25A A rough top view.

[0061] Figure 26A This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0062] Figure 26B yes Figure 26A A rough top view.

[0063] Figure 27 This is a process diagram illustrating the manufacturing method of film capacitor 1.

[0064] Figure 28 This is a general cross-sectional view of an electronic circuit board having a structure in which a thin-film capacitor 1 is embedded in a multilayer substrate 100.

[0065] Figure 29 This is a general cross-sectional view of an electronic circuit board having a structure in which a thin-film capacitor 1 is mounted on the surface of a multilayer substrate 300.

[0066] Figure 30 This is a table that represents the evaluation results of the samples. Detailed Implementation

[0067] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0068] Figure 1A This is a general cross-sectional view illustrating the structure of a thin-film capacitor 1 according to an embodiment of the present invention. Figure 1B This is a rough top view of film capacitor 1.

[0069] like Figure 1A and Figure 1B As shown, the film capacitor 1 includes: a metal foil 10; annular or polygonal annular insulating members 21 and 22 formed on the upper surface 11 of the metal foil 10; conductive members 31 and 32 formed on the upper surface 11 of the metal foil 10 and divided by the insulating members 21 and 22; a terminal electrode 51 connected to the conductive member 31 via a seed layer 40; and a terminal electrode 52 connected to the conductive member 32 via the seed layer 40. The metal foil 10 is made of a metallic material such as aluminum, copper, chromium, nickel, or tantalum, and at least a portion of the main surfaces located on opposite sides, namely the upper surface 11 and the lower surface 12, is roughened. Aluminum is most preferably used as the material of the metal foil 10. A dielectric film D is formed on the upper surface 11 and the lower surface 12 of the metal foil 10. The insulating members 21 and 22 are made of resin, for example. The conductive members 31 and 32 are made of conductive polymer material, for example. The seed layer 40 and the terminal electrodes 51 and 52 are made of materials such as copper, nickel or gold and their alloys or layer structures.

[0070] An annular or polygonal annular insulating member 21 is disposed within a slit that electrically separates the electrode layer composed of terminal electrode 51 and conductive member 31 from the electrode layer composed of terminal electrode 52 and conductive member 32. Terminal electrode 52 and conductive member 32 are located within a region surrounded by insulating member 21, and outside the region surrounded by insulating member 21, within a region surrounded by insulating member 22. In the region surrounded by insulating member 21, part or all of the dielectric film D formed on the upper surface 11 of metal foil 10 is removed, and an opening is formed on the dielectric film D. Thus, terminal electrode 52 is electrically connected to metal foil 10 via conductive member 32. Alternatively, as... Figure 1C and Figure 1DAs shown, the conductive component 32 can also be omitted, and the metal foil 10 can be directly connected to the terminal electrode 52 or via the seed layer 40. Conversely, the dielectric film D formed on the upper surface 11 of the metal foil 10 is not removed outside the area surrounded by the insulating component 21. That is, the conductive component 31 is not in contact with the metal foil 10 but is in contact with the dielectric film D, and the terminal electrode 51 and the metal foil 10 are mutually insulated. Thus, the terminal electrodes 51 and 52 function as a pair of capacitor electrodes facing each other via the dielectric film D. Furthermore, since the dielectric film D is formed on the roughened upper surface 11 of the metal foil 10, the surface area of ​​the upper surface 11 is increased, thereby enabling a large capacitance.

[0071] In the outer peripheral region 15, outside the area surrounded by the insulating component 22, the dielectric film D disposed on the upper surface 11 of the metal foil 10 is exposed. This exposes a roughened surface in the outer peripheral region 15 of the film capacitor 1, thereby improving the fit when embedded in the multilayer substrate. Consequently, even after thermal shock testing, the stress is dispersed after embedding the film capacitor 1 in the multilayer substrate, reducing the likelihood of short circuits and open circuits, thus improving product reliability. The width W of the outer peripheral region 15 is preferably 10 μm or more and 100 μm or less. This is because setting the width W of the outer peripheral region 15 to 10 μm or more sufficiently improves the fit, while setting it to 100 μm or less ensures sufficient capacitance. While it is not necessary for the outer peripheral region 15 to be covered by the dielectric film D, and the roughened upper surface 11 of the metal foil 10 can be directly exposed, it is preferable for the outer peripheral region 15 to be covered by the dielectric film D to improve the fit to the multilayer substrate.

[0072] The side surface 13 of the metal foil 10 is not roughened, and its surface is covered by an insulating film 14. Here, there is an annular or polygonal annular insulating member 22 between the conductive member 31 and the side surface 13 of the metal foil 10, and a gap region without conductive members is provided in the outer peripheral region 15 located outside the annular or polygonal annular insulating member 22. Therefore, even if the insulating film 14 is thin, short circuit between the conductive member 31 and the metal foil 10 is prevented.

[0073] Regarding the grain size of the central portion (non-coarsened portion) of the metal foil 10, it is preferably less than 15 μm in the planar direction (parallel to the upper surface 11 and lower surface 12) and less than 5 μm in the thickness direction (perpendicular to the upper surface 11 and lower surface 12), and preferably the crystal orientation is aligned as much as possible in the planar direction. Accordingly, as described later, the positional accuracy of the side surface 13 can be improved.

[0074] The thin-film capacitor 1, by being embedded in a multilayer substrate, can be used as a decoupling capacitor. The thickness of the thin-film capacitor 1 is, for example, 50 μm or less, which is very thin. Therefore, when the terminal electrode 51 and conductive component 31 are formed on the upper surface 11 side, it is easy to form a shape that convexes towards the lower surface 12 side. Therefore, when mounting to suppress element warping during embedding in the multilayer substrate, Figure 2 In the cross-section shown, when the straight line L1 along the upper surface 11, the straight line L2 along the lower surface 12, and the straight line L3 along the side surface 13 are defined, the angle θa formed by the straight lines L2 and L3 is preferably 20° < θa < 80°. That is, it is preferable that the area of ​​the lower surface 12 is larger than the area of ​​the upper surface 11. Accordingly, the adhesion between the side surface 13 of the film capacitor 1 and the multilayer substrate is improved, thereby improving the strength and reliability of the film capacitor 1. In this case, it is more preferable that 30° ≤ θa ≤ 60° is satisfied. By designing the angle θa within the above range, the warping of the film capacitor 1 during installation can be reduced, and since the contact area between the side surface 13 and the insulating resin constituting the multilayer substrate is optimally controlled, the strength and reliability of the film capacitor 1 can be further improved. In addition, the side surface 13 of the film capacitor 1 may also have a curved shape in which the angle θa is larger as it approaches the upper surface 11 and smaller as it approaches the lower surface 12. In this way, when the angle θa is not constant, the value of the angle θa is defined by the average value.

[0075] Next, an example of a method for manufacturing the film capacitor 1 will be described.

[0076] First, prepare 10 metal foils (e.g., aluminum) with a thickness of approximately 50 μm. Figure 3 ), roughened by etching its upper surface 11 and lower surface 12 ( ). Figure 4 Alternatively, the metal foil 10 can be formed by sintering metal powder, instead of roughening the flat metal foil 10. This forms a porous layer 11a on the upper surface 11 and a porous layer 12a on the lower surface 12 of the metal foil 10. Between the porous layers 11a and 12a is an unroughened non-porous layer 10a. In this case, it is sufficient to roughen at least the upper surface 11; it is not necessary to roughen the lower surface 12. However, roughening both surfaces prevents warping of the metal foil 10. Furthermore, for the upper surface 11, etching is preferably performed under conditions that maximize the surface area. Even when both the upper and lower surfaces 11 and 12 are roughened, the etching conditions for the upper and lower surfaces 11 can differ. For example, for the lower surface 12, etching can be performed under conditions that maximize the adhesion to the multilayer substrate.

[0077] Next, a dielectric film D is formed on the surface of the metal foil 10. Figure 5AThe dielectric film D can also be formed by oxidizing the metal foil 10, or by using film-forming methods with excellent coverage, such as ALD, CVD, or atomized CVD. Materials for the dielectric film D can include Al2O3, TiO2, Ta2O5, SiNx, TiNx, and TaNx. The material of the dielectric film D can also be amorphous. In this case, the composition ratio of the dielectric film D may not necessarily be the stated composition ratio. At this time, it is sufficient to form the dielectric film D at least on the upper surface 11; it is not necessary to form the dielectric film D on the lower surface 12. However, by also forming the dielectric film D on the lower surface 12, the insulation of the lower surface 12 can be ensured. Figure 5B As shown, the dielectric film D formed on the lower surface 12 can have the same composition as the dielectric film D formed on the upper surface 11, or it can be a barrier film E with a different composition, or it can be a stacked structure of dielectric film D and barrier film E. Furthermore, if a barrier film E is present on the lower surface 12 of the metal foil 10, the intrusion of reaction-generated gases produced by the resin constituting the multilayer substrate can be suppressed during the curing of the multilayer substrate. After forming the dielectric film D or the barrier film E, a transport substrate 60 is attached to the lower surface 12 of the metal foil 10. Figure 6 ).

[0078] Next, a photosensitive resist layer is formed on the upper surface 11 of the metal foil 10, and then exposed and developed to form a patterned resist layer 61. Figure 7A , 7B An opening 62 is provided on the resist layer 61 to expose the dielectric film D. The resist layer can be positive or negative.

[0079] Next, by using the resist layer 61 as a mask to remove part or all of the dielectric film D, the metal foil 10 is exposed at the opening 62. Figure 8A , 8B As a method for removing the dielectric film D, reverse sputtering, ion polishing, RIE, wet etching, etc., can be used. Furthermore, the upper surface 11 of the metal foil 10 is roughened in this stage; therefore, by using reverse sputtering, ion polishing, RIE, etc., the spread of the etchant caused by capillary action can be prevented. Liquid etchant can also be used in this process. Furthermore, in... Figure 8A In the example shown, the surface of the exposed metal foil 10 and the dielectric film D form approximately the same plane, but depending on the etching conditions, such as Figure 9 As shown, it can also sometimes be a roughened metal foil 10 with a prominent shape.

[0080] Next, after removing the anti-corrosion layer 61 ( Figure 10 Insulating components 21 and 22 are formed on the upper surface 11 of the metal foil 10. Figure 11A , 11BThe insulating components 21 and 22 can be formed using photolithography, screen printing, gravure printing, inkjet printing, etc. Therefore, the cross-sections of the insulating components 21 and 22 are as follows: Figure 11A As shown, the side surface is conical. Here, the location of the insulating component 21 can be as follows: Figure 12A The portion shown overlaps with the exposed portion of the metal foil 10, and can also be as follows: Figure 12B The portion shown does not overlap with the exposed portion of the metal foil 10. Furthermore, the cross-sections of the insulating components 21 and 22 do not need to be bilaterally symmetrical, such as... Figure 13 As shown, taking the centerline C in the thickness direction of the metal foil 10 as a reference, the angle θc of the outer portion is smaller than the angle θb of the inner portion of the ring. Therefore, the tapered surface of the outer portion of the ring can be wider than the tapered surface of the inner portion. In the insulating component 21, the side forming the inner portion is connected to the conductive component 32 or the terminal electrode 52, and the side forming the outer portion is connected to the conductive component 31 or the terminal electrode 51. By adopting the above structure, abnormal stress is not generated during the shrinkage process when forming the insulating components 21 and 22, cracks in the roughened portions can be reduced, and the yield rate is improved.

[0081] Next, a photosensitive resist layer is formed on the upper surface 11 of the metal foil 10, and then exposed and developed to form a patterned resist layer 64. Figure 14A , 14B An opening 65 is provided on the resist layer 64 to expose a region located on the outer side of the insulating member 22. The resist layer 64 is larger than the insulating member 22, thereby covering a portion of the outer side of the insulating member 22. The resist layer can be positive or negative.

[0082] Next, the metal foil 10 is removed by using the resist layer 64 as a mask, thus monolithizing the metal foil 10. Figure 15A , 15B As a method for removing the metal foil 10, wet etching using an etchant such as an acid can be employed. In this case, even if a liquid etchant is used, the etchant will not extend beyond the insulating member 22. As a result, the outer peripheral region 15 of the metal foil 10 remains outside the insulating member 22.

[0083] To achieve higher precision in monolithic fabrication, as described above, it is preferable that the grain size of the central portion (non-coarsened portion) of the metal foil 10 is less than 15 μm in the planar direction and less than 5 μm in the thickness direction. This is because when the grain size of the metal foil 10 is 15 μm or more in the planar direction and 5 μm or more in the thickness direction, such as... Figure 16A , 16BAs shown, the grains protrude from the inner wall of side 13, increasing the dimensional inhomogeneity of the monolithic metal foil 10. Conversely, if the grain size of the metal foil 10 is less than 15 μm in the planar direction and less than 5 μm in the thickness direction, such as Figure 17A , 17B As shown, the grains appearing on the side 13 are small, thus also reducing the size unevenness of the monolithic metal foil 10.

[0084] Next, after removing the anti-corrosion layer 64 ( Figure 18 , 19 Conductive components 31 and 32, made of conductive polymer material, are formed in the region surrounded by insulating component 22, and are in a paste or liquid form. Figure 20A , 20B In this configuration, conductive component 32 is located in the region surrounded by insulating component 21, and conductive component 31 is located outside the region surrounded by insulating component 21 and within the region surrounded by insulating component 22. No conductive component is formed in the outer peripheral region 15, allowing the dielectric film D to be directly exposed. Conductive components 31 and 32 are in a paste or liquid state, and thus, through capillary action, fill to the bottom of the porous layer 11a. Therefore, conductive component 31 is not in contact with the metal foil 10 but is in contact with the dielectric film D, while conductive component 32 is in contact with the metal foil 10. Alternatively, the terminal electrode 52 can be formed directly without forming conductive component 32.

[0085] Next, a seed layer 40 is formed on the entire surface. Figure 21 Seed layer 40 can be formed using methods such as sputtering. Next, a patterned resist layer 67 is formed by forming a photosensitive resist layer on the upper surface 11 of the metal foil 10, followed by exposure and development. Figure 22A , 22B An opening 68 is provided on the resist layer 67, located outside the region surrounded by the insulating member 22 and the region surrounded by the insulating member 21, and an opening 69 is provided in the region surrounded by the insulating member 21. Thus, in the seed layer 40, the portion covering the conductive member 31 is exposed through the opening 68, and the portion covering the conductive member 32 is exposed through the opening 69. The resist layer can be either positive or negative.

[0086] By performing electroplating in this state, terminal electrodes 51 and 52 are formed. Figure 23A , 23B Next, the resist layer 67 is removed by ashing or other methods. Figure 24A , 24B ), remove seed layer 40 ( Figure 25A , 25BFurthermore, after forming an insulating film 14 on the side 13 of the metal foil 10 (Fig. 26), the transport substrate 60 is removed by peeling or etching. Figure 27 ),but Figure 1A , 1B The thin-film capacitor 1 shown is now complete. Here, the insulating film 14 can be formed by oxidizing the side surface 13 of the metal foil 10 through an ashing process for removing the resist layer 67 and other heat treatment processes. Multiple terminal electrodes 51 and 52 can each be formed, as long as at least one pair is formed.

[0087] The thin-film capacitor 1 in this embodiment can be as follows: Figure 28 The multilayer substrate 100 shown can also be embedded as follows: Figure 29 It is shown mounted on the surface of the multilayer substrate 300.

[0088] Figure 28 The illustrated electronic circuit board has a structure in which a semiconductor IC 200 is mounted on a multilayer substrate 100. The multilayer substrate 100 is a multilayer substrate comprising multiple insulating layers and multiple wiring patterns. The multiple insulating layers include insulating layers 101 to 104, and the multiple wiring patterns include wiring patterns 111 and 112. The number of insulating layers is not particularly limited. Figure 28 In the example shown, a thin-film capacitor 1 is embedded between insulating layers 102 and 103. Multiple bonding patterns, including bonding patterns 141 and 142, are provided on the surface of the multilayer substrate 100. The semiconductor IC 200 has multiple pad electrodes, including pad electrodes 201 and 202. For example, one of the pad electrodes 201 and 202 is a power terminal, and the other is a ground terminal. The pad electrode 201 and bonding pattern 141 are connected via solder 211, and the pad electrode 202 and bonding pattern 142 are connected via solder 212. Furthermore, bonding pattern 141 is connected to the terminal electrode 51 of the thin-film capacitor 1 via via conductor 121, wiring pattern 111, and via conductor 131. On the other hand, bonding pattern 142 is connected to the terminal electrode 52 of the thin-film capacitor 1 via via conductor 122, wiring pattern 112, and via conductor 132. Thus, the thin-film capacitor 1 functions as a decoupling capacitor relative to the semiconductor IC 200.

[0089] Figure 29 The illustrated electronic circuit board has a structure in which a semiconductor IC 400 is mounted on a multilayer substrate 300. The multilayer substrate 300 is a multilayer substrate comprising multiple insulating layers and multiple wiring patterns. The multiple insulating layers include insulating layers 301 and 302, and the multiple wiring patterns include wiring patterns 311 and 312. The number of insulating layers is not particularly limited. Figure 29In the example shown, a thin-film capacitor 1 is mounted on the upper surface of the surface 300a of the multilayer substrate 300. Multiple bonding patterns, including bonding patterns 341 to 344, are provided on the surface 300a of the multilayer substrate 300. The semiconductor IC 400 has multiple pad electrodes, including pad electrodes 401 and 402. For example, one of the pad electrodes 401 and 402 is a power terminal, and the other is a ground terminal. The pad electrode 401 and bonding pattern 341 are connected via solder 411, and the pad electrode 402 and bonding pattern 342 are connected via solder 412. Furthermore, bonding pattern 341 is connected to the terminal electrode 51 of the thin-film capacitor 1 via via conductor 321, wiring pattern 311, via conductor 331, and solder 413. On the other hand, bonding pattern 342 is connected to the terminal electrode 52 of the thin-film capacitor 1 via via conductor 322, wiring pattern 312, via conductor 332, bonding pattern 344, and solder 414. Therefore, the thin-film capacitor 1 functions as a decoupling capacitor relative to the semiconductor IC400.

[0090] The above describes preferred embodiments of the present invention, but the present invention is not limited to the above embodiments. Various modifications can be made without departing from the spirit of the present invention, and these modifications are also included within the scope of the present invention.

[0091] Example

[0092] Multiple thin-film capacitor samples were fabricated, each having the same structure as the thin-film capacitor 1 shown in Figure 1, with varying surface roughness of the upper and lower surfaces 11 and 12 of the various metal foils 10, and different thicknesses and materials of the dielectric film D. The sample had a planar dimension of 1.0 mm × 0.5 mm, and the width W of the outer peripheral region located outside the insulating component 22 was 30 μm. Furthermore, the thin-film capacitor samples were mounted on an evaluation multilayer substrate and subjected to thermal shock testing to evaluate the probability of connection failures. Connection failures included both short-circuit failures and open-circuit failures. The results were then presented in… Figure 30 As shown in the image.

[0093] like Figure 30As shown, in sample B1, where the outer periphery of the upper surface 11 of the metal foil 10 is not exposed, the probability of connection failure is 56%. In sample B2, where the outer periphery is not roughened, the probability of connection failure is 45%. In contrast, in samples A1 to A20, where the outer periphery of the upper surface 11 of the metal foil 10 is roughened and exposed from the terminal electrodes 51 and 52, the probability of connection failure is less than 25%. As the evaluation results of samples A1 to A5 show, the greater the surface roughness of the upper surface 11 of the metal foil 10, the lower the probability of connection failure. Furthermore, in samples A6 to A9, where not only the upper surface 11 of the metal foil 10 is roughened, but also the lower surface 12 is roughened, the probability of connection failure is less than 18%. As the evaluation results of samples A6 to A9 show, the greater the surface roughness of both the upper surface 11 and the lower surface 12 of the metal foil 10, the lower the probability of connection failure.

[0094] Furthermore, in samples A10 to A17 where the outer periphery of the upper surface 11 of the metal foil 10 is covered by the dielectric film D, the probability of poor bonding is less than 17%. In particular, in samples A12 to A17 where the upper surface 11 and lower surface 12 of the metal foil 10 are roughened, the probability of poor bonding is 6% to 8%. The same results were obtained in samples A18 to A20 where the dielectric film D is a multilayer film with multiple dielectric materials stacked on it.

[0095] Explanation of reference numerals in the attached figures

[0096] 1. Thin film capacitor

[0097] 10 metal foil

[0098] 10a non-porous layer

[0099] 11. The upper surface of the metal foil

[0100] 11a porous layer

[0101] 12 Lower surface of metal foil

[0102] 12a porous layer

[0103] 13. Side of metal foil

[0104] 14 insulating film

[0105] 15 peripheral areas

[0106] 21, 22 Insulating components

[0107] 31, 32 Conductive components

[0108] 40 seed layers

[0109] 51 and 52 terminal electrodes

[0110] 60 Conveyor Base Material

[0111] Anti-corrosion layers 61, 64, and 67

[0112] Openings at points 62, 65, 68, and 69

[0113] 100 and 300 multilayer substrates

[0114] Insulation layers 101-104, 301, and 302

[0115] Wiring patterns 111, 112, 311, 312

[0116] 121, 122, 131, 132, 321, 322, 331, 332 through-hole conductors

[0117] 141, 142, 341-344 joining patterns

[0118] 200, 400 semiconductor ICs

[0119] 201, 202, 401, 402 pad electrodes

[0120] Solders 211, 212, and 411-414

[0121] Surface of 300a multilayer substrate

[0122] D dielectric film

[0123] E-blocking membrane.

Claims

1. A thin-film capacitor comprising: Metal foil, one of its main surfaces is roughened; A dielectric film covering one main surface of the metal foil, having an opening that partially exposes the metal foil; A first electrode layer, which is in contact with the metal foil via the opening; and The second electrode layer is not in contact with the metal foil but is in contact with the dielectric film. The first and second electrode layers do not cover the outer peripheral region of one main surface of the metal foil, but are formed in the region surrounded by the outer peripheral region. The first and second electrode layers are separated by an annular slit. The first electrode layer is disposed in the first region surrounded by the slit. The second electrode layer is disposed in a second region located outside the slit. It also includes a first insulating component and a second insulating component. The first insulating component is disposed inside the slit, located between the first and second electrode layers. The second insulating component is disposed on one main surface of the metal foil, surrounding the second electrode layer. The second electrode layer and the outer peripheral region are separated by the second insulating component. In the outer peripheral region, the dielectric film disposed on one main surface of the metal foil is exposed.

2. The thin-film capacitor according to claim 1, wherein, The dielectric membrane is composed of one or more membranes selected from Al2O3, TiO2, Ta2O5, SiNx, TiNx, and TaNx.

3. The thin-film capacitor according to claim 1, wherein, The other main surface of the metal foil is roughened.

4. The film capacitor according to claim 1, wherein, The second electrode layer includes a first conductive component made of a conductive polymer material and in contact with the dielectric film, and a second conductive component made of a metallic material and in contact with the first conductive component.

5. The film capacitor according to claim 4, wherein, The first electrode layer includes a third conductive component that is in contact with the metal foil and is made of a conductive polymer material, and a fourth conductive component that is in contact with the third conductive component and is made of a metallic material.

6. The thin-film capacitor according to claim 4, wherein, The first electrode layer includes a fourth conductive component that is in contact with the metal foil and is made of a metallic material.

7. An electronic circuit board, comprising: A substrate having a wiring pattern; and The semiconductor IC disposed on the substrate and the thin film capacitor according to any one of claims 1 to 6 The first and second electrode layers of the thin-film capacitor are connected to the semiconductor IC via the wiring pattern.

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