Carrier substrate for soi structure and associated production method

Abstract

The invention relates to a carrier substrate (10) made of monocrystalline silicon, the carrier substrate (10) having a front face (10a) and a back face (10b) and comprising: - a surface area (1) extending from the front face (10a) to a depth of between 800 nm and 2 microns and having less than 10 crystal originated particles (COP) detected by surface inspection based on dark field reflection microscopy, - an upper area (2) extending from the front face (10a) to a depth of between several microns and 40 microns and having an interstitial oxygen (Oi) content lower than or equal to 7.5E17 Oi / cm 3 and a resistivity higher than 500 ohm.cm, and - a lower area (3) extending between the upper area (2) and the back face (10b) and having a density of microdefects (BMD) higher than or equal to 1E8 / cm 3 The invention also relates to a method for manufacturing such a carrier substrate (10).

Description

TECHNICAL FIELD

[0001] The field of the invention is that of semiconductors and microelectronics. The invention relates to a carrier substrate made of silicon for a silicon-on-insulator (SOI) structure, in particular a fully depleted SOI (FD-SOI) structure, suitable for logic and radiofrequency applications. The invention also relates to a method for manufacturing such a carrier substrate. BACKGROUND

[0002] The advantages of FD-SOI technology have been widely documented for radiofrequency and low-power logic applications.

[0003] To meet the stringent specifications of these applications, the FD-SOI structure must meet a number of criteria.

[0004] Firstly, the very thin working layer made of silicon, typically of the order of 20 nm, must exhibit excellent thickness uniformity and high crystal quality. To achieve this, it must be able to withstand high-temperature processing, in particular during its production; said processing is needed to smooth the free surface of the working layer and to repair crystal defects present in this layer. This involves the carrier substrate of the SOI structure being resistant to slip line failure modes, and in particular, exhibiting a density of microdefects (BMD for bulk microdefects) that is sufficient and uniform throughout the process. These microdefects are generally present in sufficient quantities in substrates with a high interstitial oxygen content ("high-Oi" substrates), typically corresponding to an Oi concentration higher than 1 E18 / cm 3 (ASTM'79 standard): these high-Oi carrier substrates are particularly robust with respect to slip line defects.

[0005] Secondly, the SOI structure must be compatible with very low inspection thresholds, so as to allow detection of defects with a size less than 50 nm on and / or in the working layer. High-Oi carrier substrates are known to include defects called "crystal-originated particles" (COPs) that limit the inspectability of the working layer of the SOI structure; in particular, COP defects located in the surface region of the carrier substrate can be detected during the inspection of the working layer with very thorough detection thresholds, even if the COP defects remain below the buried oxide layer of the SOI structure, due to the penetration of the inspection signal, which will probe slightly below the buried oxide. High-Oi carrier substrates are therefore not compatible with such applications.

[0006] Finally, to meet the radiofrequency requirements, the carrier substrate of the SOI structure must exhibit a stable and high resistivity (higher than 500 ohm.cm, higher than 1000 ohm.cm, or even higher than 5000 ohm.cm). To obtain these properties, the usual practice is to use a high-resistivity carrier substrate with a low Oi content ("low Oi" substrate, generally corresponding to an Oi concentration lower than 8E17 Oi / cm 3 , as those with a high Oi content exhibit instabilities of the resistivity at depth, in particular due to the smoothing thermal treatments required for the working layers. Unfortunately, low Oi carrier substrates are extremely sensitive to long-time treatments at high temperature, and subsequently exhibit high-density slip lines detrimental to the SOI structure.

[0007] Subject matter of the invention

[0008] The invention provides a solution to overcome all or some of the above-mentioned drawbacks. In particular, the invention relates to a carrier substrate compatible with the thermal treatments applied on SOI structures and with the stringent specifications of logic and radiofrequency applications. The invention also relates to a method for producing such a carrier substrate. SUMMARY

[0009] The invention relates to a carrier substrate made of monocrystalline silicon, having a front face and a back face, and comprising:

[0010] - a surface region from the front face down to a depth of between 800 nm and 2 microns, the surface region having less than 10 crystal native particles (COP) detected by using dark field microscopy to inspect the surface,

[0011] - an upper region extending from the front face down to a depth of between a few microns and 40 microns, the upper region having an interstitial oxygen (Oi) content lower than or equal to 7.5E17 Oi / cm 3 and a resistivity higher than 500 ohm.cm, and

[0012] - a lower region extending between the upper region and the back face, the lower region having a density of microdefects (BMD) higher than or equal to 1E8 / cm 3 .

[0013] Some advantageous features according to the invention, taken separately or in any feasible combination:

[0014] • the resistivity of the upper region is higher than or equal to 750 ohm.cm, or even higher than or equal to 1000 ohm.cm;

[0015] • the upper region extends down to a depth of between 10 microns and 30 microns;

[0016] • the density of the microdefects (BMD) in the lower region is between 1 E8 / cm 3 and 3 E10 / cm 3 and preferably between 1 E9 / cm 3 and 2 E10 / cm 3 .

[0017] The application also relates to an SOI structure comprising a working layer arranged on a dielectric layer itself arranged on the above-mentioned carrier substrate.

[0018] The thickness of the working layer can be less than 50 nm, preferably between 4 nm and 25 nm; and the thickness of the dielectric layer can be between 10 nm and 150 nm.

[0019] The application also relates to an electronic component for radiofrequency and low-power logic applications, said electronic component comprising at least one transistor arranged on and / or in the working layer of the above-mentioned SOI structure.

[0020] Finally, the application relates to a method for producing a carrier substrate as described above. The production method comprises the following steps:

[0021] a) providing an initial substrate made of monocrystalline silicon, said initial substrate having an interstitial oxygen content between 12 E17 Oi / cm 3 and 16 E17 Oi / cm 3 and a resistivity higher than 500 ohm.cm, said initial substrate being intended to form, after having undergone the subsequent steps b) and c), the carrier substrate,

[0022] b) applying a first heat treatment under a neutral or reducing atmosphere at a temperature between 1150°C and 1250°C for a duration longer than or equal to 30 minutes, to form the surface region and the upper region of the carrier substrate,

[0023] c) applying a second heat treatment comprising a first annealing sequence at a temperature between 600°C and 900°C and a second annealing sequence at a temperature between 950°C and 1100°C, to form the lower region of the carrier substrate.

[0024] Advantageously, the first sequence of the second heat treatment comprises two temperature plateaus, the first plateau being between 650°C and 700°C and the second plateau being at about 800°C. BRIEF DESCRIPTION OF DRAWINGS

[0025] Other features and advantages of the application will become apparent from the following detailed description, made with reference to the attached drawings, in which:

[0026] - Figure 1 A carrier substrate according to the application is shown;

[0027] - Figure 2 An SOI structure comprising a carrier substrate according to the application is shown;

[0028] - Figures 3a to 3c Steps of a method for producing a carrier substrate according to the application are shown;

[0029] - Figure 4 Two figures resulting from surface inspection using a dark field microscope of the surface of an initial substrate (a) not treated by the production method according to the application and of the surface of an intermediate substrate (b) after the first heat treatment of the production method according to the application are shown;

[0030] - Figure 5 An edge of a carrier substrate according to the application after chemical revelation of BMD type microdefects is shown;

[0031] - Figure 6 A plot of the resistivity of a carrier substrate according to the application as a function of depth is shown.

[0032] In the attached drawings, identical references can be used for identical nature elements.

[0033] The attached drawings are schematic representations not drawn to scale for readability. In particular, the thickness of the layers along the z axis is not to scale with respect to the lateral dimensions along the x and y axes. DETAILED DESCRIPTION

[0034] The application relates to a monocrystalline silicon carrier substrate 10 having a front face 10a and a back face 10b substantially parallel to a main plane (x, y). It is advantageously in the form of a circular wafer having a diameter between 200 mm and 450 mm. Its total thickness along the z axis perpendicular to the main plane (x, y) can range between a few hundred microns and 1000 microns.

[0035] The carrier substrate 10 comprises a surface area 1 from the front face 10a down to a depth of the order of microns, generally between 800 nm and 2 microns. This surface area 1 exhibits the particularity of a very low density of crystal native particles (COP). A direct means of detecting these COPs is the use of a surface inspection instrument based on dark field microscopy, which is generally implemented as a measurement of the surface defect density. For example, a device known in the microelectronics field such as the KLA-Tencor Surfscan SP2 (registered trademark) can be used. According to the application, less than 10 COPs are detected on the front face 10a of the carrier substrate 10 in a tilted incidence mode (narrow tilted channel) and with a detection threshold of 44 nm.

[0036] The carrier substrate 10 comprises an upper region 2 extending down from the front face 10a to a depth of between a few microns and 40 microns, preferably to a depth of between 10 microns and 30 microns. The upper region 2 thus comprises the surface region 1.

[0037] The upper region 2 has an interstitial oxygen (Oi) content lower than or equal to 7.5E17 Oi / cm 3 This corresponds to a content lower than or equal to 15 ppma (according to the ASTM'79 standard). Furthermore, it has a resistivity higher than 500 ohm.cm, corresponding to a low concentration of p-type dopant (boron). Advantageously, its resistivity is even higher than or equal to 750 ohm.cm, or even higher than or equal to 1000 ohm.cm. The resistivity level is defined according to the targeted application and the electronic component that will be produced later on the top of the carrier substrate 10. The resistivity range of the upper region 2 is particularly suitable for radiofrequency components targeting applications in the 30 GHz to 300 GHz frequency band, involving millimeter wavelengths ("mmWave"), and notably for supporting the 5G network of the next generation of mobile telephones.

[0038] The carrier substrate 10 finally comprises a lower region 3 extending between the upper region 2 and the back face 10b, the thickness of the lower region 3 being of the order of a few hundred microns. This lower region 3 has a density of microdefects (BMD) higher than or equal to 1E8 / cm 3 This confers to it a high mechanical robustness with respect to heat treatments at high temperature. The density of microdefects (BMD) in the lower region 3 is preferably between 1E8 / cm 3 and 3E10 / cm 3 and more preferentially between 1E9 / cm 3 and 2E10 / cm 3 .

[0039] The lower region 3 has a resistivity generally higher than or equal to 250 ohm.cm and possibly fluctuating, which has no real impact on future radiofrequency components, since the electromagnetic field generated by said components does not reach or only very little reaches the lower region 3. It is only the resistivity of the upper region 2 that must present a stable and sufficiently high value.

[0040] In order to allow the production of a component, it is necessary to transfer the working layer on or in which said component will be located onto the carrier substrate 10.

[0041] The application thus also relates to a silicon-on-insulator (SOI) structure 100 comprising a working layer 30 arranged on a dielectric layer 20 itself arranged on the above-mentioned carrier substrate 10 Figure 2 .

[0042] The working layer 30 is made of high-quality single-crystalline silicon and has a thickness less than 50 nm, preferably between 4 nm and 25 nm. This thickness range is particularly suitable for electronic components based on FD-SOI architecture and technology. The dielectric layer 20, made of silicon oxide for example, has a thickness itself between 10 nm and 150 nm.

[0043] The presence of the surface region 1 of the carrier substrate 10 (exhibiting a very low density of crystal native particles (COP)) provides excellent inspectability of the SOI substrate 100 at very low detection thresholds (< 50 nm). Therefore, the quality of the working layer 30 can be finely and reliably controlled without hindrance and / or false detections due to the presence of COPs at the surface of the carrier substrate 10.

[0044] The present invention also relates to an electronic component for radiofrequency and low-power logic applications. In particular, such a component comprises at least one transistor arranged on and / or in the working layer 30 of the SOI structure 100. The properties of the upper region 2 of the carrier substrate 10 (i.e. resistivity and low Oi concentration) confer very good insulating properties to this region: in particular, in addition to its high level, the resistivity is stable in this region 2 as it does not undergo fluctuations due to the presence of oxygen thermal donors and small BMDs which compensate the initial p-type doping. Therefore, the resistivity of the upper region 2 does not undergo any drop or large fluctuations during a heat treatment at high temperature (> 1100°C) applied to the SOI structure 100. In addition, the high density of microdefects (BMDs) in the lower region 3 of the carrier substrate 10 confer excellent mechanical strength and insensitivity to slip line defects during said heat treatment.

[0045] The present invention further relates to a method for producing a carrier substrate 10 as described above.

[0046] Said production method comprises a step a) of providing an initial substrate 10' made of single-crystalline silicon, said initial substrate 10' having an interstitial oxygen content between 12E17 Oi / cm 3 and 16E17 Oi / cm 3 It is noted that a substrate having a content between 24 ppma and 28 ppma (ASTM'79) is generally considered as a substrate having a medium Oi content ("medium Oi" substrate); a substrate having a content between 27 ppma and 32 ppma (ASTM'79) is generally considered as a substrate having a high Oi content ("high Oi" substrate).

[0047] The initial substrate 10' has a resistivity higher than 500 ohm.cm, i.e. a concentration of p-type dopant (boron) lower than or equal to 2.6E13 / cm 3 . It is intended to form the carrier substrate 10 after the subsequent steps b) and c) of the method have been undergone. Thus, the resistivity of the initial substrate 10' is chosen to have the required value for the upper region 2 of the carrier substrate 10, according to the targeted application. Advantageously, the resistivity of the initial substrate 10' is higher than or equal to 750 ohm.cm, or even higher than or equal to 1000 ohm.cm.

[0048] During the next step b) of the method, a first heat treatment is applied to the initial substrate 10' under a neutral or reducing atmosphere, at a temperature between 1150°C and 1250°C. The duration of this treatment is longer than or equal to 30 minutes, for example between 5 and 10 hours.

[0049] The role of this first heat treatment is to dissolve the crystalline native particles (COP) in the surface region of the initial substrate 10' over a depth between 800 nm and 2 microns. This leads to the formation of the surface region 1 of the future carrier substrate 10.

[0050] The COPs can be dissolved, for example, by a rapid thermal annealing (RTA) (with fast rising and falling ramps (50°C / min)) at a temperature of about 1250°C for 10 seconds under a neutral (argon) or reducing (argon and hydrogen) atmosphere. Alternatively, in a conventional oven, for example, annealing at 1200°C for 30 minutes or 1 hour, still under a neutral or reducing atmosphere, also allows the dissolution of the COPs in the surface region 1.

[0051] Another role of the first heat treatment is to diffuse the interstitial oxygen (Oi) outwards and to deplete the initial substrate 10' of Oi, according to the duration of the heat treatment, in a region going down from its front face 10a to a greater or lesser depth. Typically, for a treatment temperature of 1200°C and a duration of 10h, the substrate is depleted of Oi over a depth of the order of 20 microns. This leads to the formation of the upper region 2 of the future carrier substrate 10.

[0052] The first heat treatment can thus consist of a single annealing that will perform both roles described above, or of a series of annealings in the same device or in different devices, in order to dissolve the COPs and to diffuse the interstitial oxygen outwards sequentially.

[0053] At the end of the first heat treatment, an intermediate substrate 10" is obtained comprising a surface region 1 going down from the front face 10a to a depth between 800 nm and 2 microns. This surface region 1 exhibits, compared to the initial substrate 10' corresponding to before any treatment Figure 4 (a) a very low density of crystalline native particles (COP) as illustrated in Figure 4 (b).Figure 4 The image was generated on a wafer with a diameter of 300 mm, in oblique incidence mode and with a detection threshold of 44 nm, using a device such as the KLA-Tencor SP2: more than 1000 COPs were detected on the front side 10a of the initial substrate 10' provided in step a) of the method; after the first heat treatment in step b), less than 10 COPs or even less than 5 COPs were detected on the front side 10a of the intermediate substrate 10”. Figure 4 (b) Example has only one COP.

[0054] After removing approximately 1 micrometer of material from the front side 10a of the intermediate substrate 10", it was observed that the detected COP remained very low, still below or equal to 10. This allows for the assessment of the thickness of the surface region 1 with low COP density.

[0055] The intermediate substrate 10” also includes an upper region 2 extending downward from the front side 10a to a depth between a few micrometers and 40 micrometers, preferably extending downward to a depth between 10 micrometers and 30 micrometers. The upper region 2 has a depth of less than or equal to 7.5E17Oi / cm. 3 The interstitial oxygen (Oi) content, relative to the Oi content of the initial substrate 10', is depleted due to the first heat treatment. The resistivity of the upper region 2 is the same as that of the initial substrate 10', i.e., higher than 500 ohm·cm. This upper region 2 can be compared to silicon with a low Oi content (“low-Oi” silicon), which gives it excellent stability in resistivity, even when the substrate is subjected to very high temperatures.

[0056] Next, the manufacturing method includes step c), during which a second heat treatment is applied to the intermediate substrate 10”. This treatment includes a first annealing sequence at a temperature between 600°C and 900°C, and a second annealing sequence at a temperature between 950°C and 1100°C.

[0057] The first annealing sequence comprises two temperature plateaus. The first plateau is between 650°C and 700°C, under a neutral atmosphere or with a low oxygen flow (typically about 0.075 standard liters per minute (slm) of O2 and about 0.015 slm of O2 in the oven for 300 mm wafers and in the oven for 200 mm wafers, respectively), for a duration between 30 minutes and 10 hours. The role of this first plateau is to promote the nucleation of "core" defects of small size (typically less than 10 nm, or even 5 nm), in particular in the lower region of the intermediate substrate 10" comprising a high Oi concentration (below the upper region 2). These cores are small SiOx precipitates which either start heterogeneously, i.e. on a pre-existing defect (vacancy) in the material, or homogeneously, i.e. by migration of oxygen atoms and formation of SiO2 and SiOx bonds. They do not form in the Oi-depleted upper region 2 or they do not form significantly in the Oi-depleted upper region 2. In addition, even if a small number of cores are formed in the upper region 2, they cannot grow in the second sequence of the second heat treatment (further described) due to the small amount of Oi, so they will be dissolved.

[0058] The second plateau is at about 800°C, under a neutral atmosphere or with a low oxygen flow, for a duration between 30 minutes and 10 hours: this allows to initiate a second nucleation phase, to form other cores between the first ones in the lower region of the intermediate substrate 10", and thus to increase their density. Note that an oxidizing atmosphere (wet or dry) can be used, preferably after half or even three quarters of the duration of the second plateau.

[0059] The second sequence of the second heat treatment (for a duration between 5 hours and 20 hours) will then cause the diffusion of interstitial oxygen Oi and its precipitation on the numerous cores present in the lower region of the substrate 10", which will make them grow and stabilize them in the material. The microdefects thus produced are called BMDs of bulk microdefects.

[0060] A lower region 3 of the carrier substrate 10 rich in BMD microdefects is thus formed Figure 3c . In particular, a BMD density in the lower region 3 between 1E8 / cm 3 and 3E10 / cm 3 is achieved, and preferably between 1E9 / cm 3 and 2E10 / cm 3 . Figure 5 Optical microscope image of the edge of the carrier substrate 10 after chemical etching for revealing the BMD microdefects: a defect-free region is observed in the upper region 2 on a thickness of the order of 20 to 25 microns. In contrast, the lower region 3 comprises a high density of BMD defects, of the order of several 1E9 / cm3 In this example, it is typically at 2E9 / cm 3 Up to 5E9 / cm 3 between.

[0061] Figure 6 An example is shown of the resistivity versus depth curve of the carrier substrate 10 according to the present invention. The initial substrate 10' has a resistivity on the order of 3500 ohm·cm and a high Oi content. After the manufacturing method of the present invention, the carrier substrate 10 has a resistivity greater than or equal to 3000 ohm·cm and is stable in the first 30 micrometers (upper region 2). Due to the high density of interstitial oxygen, the lower region 3 has a very high and fluctuating resistivity. Note that this resistivity may still change during the process used to manufacture SOI structures and microelectronic components, while the upper region 2 will maintain its resistivity level and its low COP content (surface region 1).

[0062] This carrier substrate 10 can be used for, for example Figure 2 In the illustrated method for producing SOI structure 100, the production of SOI structure 100 is preferably based on a method called Smart Cut. TM Thin-layer transfer process of the process.

[0063] A single-crystal silicon donor substrate is implanted via its front side to define a buried weakening surface that is substantially parallel to and together with the front side defines the thin layers 30, 20 to be transferred. Implantation is typically accomplished using a light substance such as hydrogen or helium ions, or a combination of both. The weakening surface is so named because it comprises lenticular nanocracks generated by the implanted light seeds.

[0064] According to a preferred option, the thin layers 30, 20 to be transferred, from the front side of the donor substrate to the buried weakening surface, comprise a dielectric layer 20 and a silicon layer 30, which will form the buried dielectric layer 20 and the silicon active layer 30 of the SOI structure 100, respectively. Therefore, it should be understood that, considering the finishing steps (mentioned below) that consume a portion of the material of the layer 30, the injection energy of the photonic seed is selected and adjusted to form a buried weakening surface (more or less located at the injection peak) at a depth corresponding to the desired thickness of the active layer 30.

[0065] The donor substrate and the carrier substrate 10 are then joined by direct bonding between the front sides of the substrates to form a bonded assembly. Surface cleaning and / or activation, known in the field of bonding by molecular adhesion, can be applied to the substrates prior to bonding to obtain excellent bonding quality. Bonding in a controlled atmosphere is also possible.

[0066] The separation at the buried weakened plane is preferably performed by applying a heat treatment at moderate temperature, typically between 350°C and 500°C, due to the growth of micro-cracks induced by the polymerization and pressurization of gaseous species. Alternatively or in combination, the separation can be achieved by applying mechanical stress to the bonded assembly.

[0067] At the end of this separation, an intermediate SOI structure is obtained on the one hand, and the rest of the donor structure on the other hand. Finishing processes including cleaning, surface treatment (etching, polishing, etc.) and / or heat treatment are typically applied to the intermediate SOI structure, and involve the removal of part of the material of the transferred working layer 30. This makes it possible to restore a good surface state (defect density and roughness) and a good crystal quality of the silicon working layer 30. Thereafter, the SOI structure 100 is available.

[0068] The finishing heat treatment described above is typically performed at a temperature between 900°C and 1250°C: the robustness of the lower region 3 of the carrier substrate 10 with respect to defects such as slip lines and other plastic deformations is a significant advantage during these treatments, and makes it possible to preserve a very good integrity of the SOI structure 100.

[0069] Although the production of the SOI structure 100 has been described here with reference to a smart-stripping process, such a structure can also be prepared by other thin layer transfer processes known in the art.

[0070] RF (e.g. "mmWave") electronic components can then be produced on or in the working layer 30, in particular based on at least one CMOS (Complementary Metal Oxide Semiconductor) transistor. Again, the properties of the carrier substrate 10 of the SOI structure 100 are advantageous for:

[0071] - the inspectability of the structure 100 during the various steps for producing components, due to the presence of the surface region 1 with very low density of COP;

[0072] - potentially, the production of all or some of the components at the surface region 1, for hybrid SOI / Bulk Si integration;

[0073] - the mechanical strength of the structure 100 during the multiple heat treatment sequences at high temperature implemented in CMOS technology for producing components, due to the high density of BMD micro-defects in the lower region 3 of the carrier substrate 10, which corresponds to a large part of the thickness of said substrate 10. By targeting advantageously a BMD density between 1E9 / cm 3 and 2E10 / cm 3 , slip lines and / or other plastic deformations in the carrier substrate 10 are avoided or largely minimized, which leads to alignment problems at various levels of lithography ("overlay");

[0074] - RF performance of the component: the high and stable resistivity of the upper region 2 of the carrier substrate 10, the low Oi content of which ensures a high stability of its resistivity despite multiple thermal treatments; its thickness is suitable for the penetration of the electromagnetic fields generated by the RF component and prevents them from reaching the lower region 3, the resistivity of which is poorly controlled and can be at a level that is too low for the target application.

[0075] The electronic component can in particular consist of an RF switch, a power amplifier (PA), a low noise amplifier (LNA), a transmitter / receiver, etc.

[0076] Needless to say, the application is not limited to the described embodiments and variants can be applied thereto without departing from the scope of the application as defined by the claims.

[0077] In particular, the working layer 30 for producing the component has been described in the context of an SOI structure, and thus consists of silicon; but it is entirely conceivable for the working layer 30 to comprise other types of materials, which can or can not be semiconductors. Similarly, the dielectric layer 20 can comprise various types of electrically insulating materials.

Claims

1. A carrier substrate (10) made of single crystal silicon, said carrier substrate (10) having a front face (10a) and a back face (10b), and comprising: - a surface region (1) from the front face (10a) down to a depth of between 800 nm and 2 microns, said surface region (1) having less than 10 crystal native particles COP detected by using dark field microscopy to inspect the surface, - an upper region (2) extending from the front face (10a) down to a depth of between a few microns and 40 microns, said upper region (2) having a gap oxygen Oi content lower than or equal to 7.5E17 Oi / cm 3 and a resistivity higher than 500 ohm.cm, wherein the depth of the upper region (2) is greater than 2 microns, and - a lower region (3) extending between said upper region (2) and said back face (10b), said lower region (3) having a microdefect BMD density higher than or equal to 1E8 / cm2. 3 of microdefects.

2. The carrier substrate (10) according to claim 1, wherein the resistivity of the upper region (2) being higher than or equal to 750 ohm.cm.

3. The carrier substrate (10) according to claim 2, wherein the resistivity of the upper region (2) being higher than or equal to 1000 ohm.cm.

4. The carrier substrate (10) according to one of claims 1 to 3, wherein the upper region (2) extends down to a depth of between 10 microns and 30 microns.

5. The carrier substrate (10) according to one of claims 1 to 3, wherein The microdefect BMD density in the lower region (3) is between 1E8 / cm 3 and 3E10 / cm 3 .

6. The carrier substrate (10) according to claim 5, wherein The microdefect BMD density in the lower region (3) is between 1E9 / cm 3 and 2E10 / cm 3 .

7. An SOI structure (100) comprising a working layer (30) arranged on a dielectric layer (20) itself arranged on a carrier substrate (10) according to one of claims 1 to 6.

8. The SOI structure (100) according to claim 7, wherein the thickness of the working layer (30) being less than 50 nm.

9. The SOI structure (100) according to claim 8, wherein, the thickness of the working layer (30) being between 4 nm and 25 nm.

10. The SOI structure (100) according to one of claims 7 to 9, wherein the thickness of the dielectric layer (20) being between 10 nm and 150 nm.

11. An electronic component for radio frequency and low power logic applications, said electronic component comprising at least one transistor arranged on and / or in the working layer (30) of an SOI structure (100) according to one of claims 7 to 10.

12. A method for producing a carrier substrate (10) according to one of claims 1 to 6, the production method comprising the following steps: a) providing an initial substrate (10') made of single crystalline silicon, said initial substrate (10') having an interstitial oxygen content between 12E17 Oi / cm 3 and 16E17 Oi / cm 3 and a resistivity higher than 500 ohm.cm, said initial substrate (10') being intended to form said carrier substrate (10) after having undergone the subsequent steps b) and c), b) applying a first heat treatment under a neutral or reducing atmosphere at a temperature of between 1150 °C and 1250 °C for a duration longer than or equal to 30 minutes to form the surface region (1) and the upper region (2), c) applying a second heat treatment comprising a first annealing sequence at a temperature of between 600 °C and 900 °C and a second annealing sequence at a temperature of between 950 °C and 1100 °C to form the lower region (3) of the carrier substrate (10).

13. The production method according to claim 12, wherein, the first sequence of the second heat treatment comprises two temperature plateaus, the first plateau being between 650 °C and 700 °C and the second plateau being at 800 °C.

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