Electrostatic chuck with improved temperature control

Abstract

Embodiments of the present disclosure provide electrostatic chucks for securing a substrate during processing. Some embodiments of the present disclosure provide methods and apparatuses for increasing temperature control across a radial profile of a substrate. Some embodiments of the present disclosure provide methods and apparatuses for controlling hydrogen concentration in a processed film during a high-density plasma (HDP) process.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to apparatus for fixing a substrate during processing. Specifically, the embodiments of this disclosure relate to apparatus and methods for fixing a substrate during high-density plasma (HDP) processes. Background Technology

[0002] Negative bias temperature instability (NBTI) is a critical reliability issue for metal-oxide-semiconductor field-effect transistors (MOSFETs). NBTI manifests as an increase in the MOSFET's threshold voltage, followed by a decrease in drain current and transconductance. Generally, more stable dynamic random-access memory (DRAM) refresh rates and NBTI performance are preferred for providing improved device yield.

[0003] Gate-induced drain leakage (GIDL) is leakage current that occurs due to a high electric field between the gate and drain. GIDL occurs when a MOSFET is biased in the accumulation region and when the drain bias voltage is much lower than the breakdown voltage.

[0004] Gate-induced drain leakage (GIDL) is an undesirable short-channel effect that occurs at high drain bias voltages when a transistor is overdriven off. GIDL results from deep depletion regions formed in the drain at high turn-off bias voltages (negative for NFETs and positive for PFETs). These depletion regions cause band bending, which in turn allows for interband tunneling that generates excessive current. GIDL can be detrimental to integrated circuits, especially non-volatile memory circuits such as flash EEPROMs.

[0005] The higher temperatures at the substrate edges during the MOSFET fabrication process result in lower hydrogen concentrations (H%) in the processed layers of the substrate. Conversely, lower temperatures provide higher H% and higher wet etch rates (WER) for the processed films.

[0006] The adjustability or controllability of substrate temperature (especially at the edges) is also limited by the design of the electrostatic chuck (ESC). Current designs limit the maximum gas pressure of the edge cooling channel between the wafer and the ESC before gas leakage issues arise. This design limitation restricts the available parameters for adjusting the temperature and H% at the wafer edges between the inner and outer channels.

[0007] Accordingly, there is a need in the art to achieve adjustability of the temperature and H% increase of the film treated by HDP at the edge of the wafer. Summary of the Invention

[0008] One or more embodiments of this disclosure relate to an electrostatic chuck including a top surface, a bottom surface, and a controller. The top surface includes: a central region including a plurality of substrate support platforms; an inner channel (IC) having an IC width and surrounding the central region; an inner band (IB) having an IB width and surrounding the inner channel; an outer channel (OC) having an OC width and surrounding the inner band; and an outer band (OB) having an OB width and surrounding the outer channel. The controller is configured to control the temperature of a wafer fixed to the top surface of the electrostatic chuck during processing.

[0009] Additional embodiments of this disclosure relate to an electrostatic chuck including a top surface and a bottom surface. The top surface includes: a central region including a plurality of substrate support platforms; an inner channel (IC) having an IC width and surrounding the central region; an inner band (IB) having an IB width and surrounding the inner channel; an outer channel (OC) having an OC width and surrounding the inner band; and an outer band (OB) having an OB width and surrounding the outer channel. The electrostatic chuck is configured to provide a range divided by 2 (R / 2) less than or equal to about 2% H% across the wafer during processing.

[0010] Further embodiments of this disclosure relate to a method for modifying an electrostatic chuck to improve temperature control across a wafer surface fixed to the top surface of the electrostatic chuck. The method includes one or more of the following steps: reducing the surface roughness of the top surface of the electrostatic chuck; changing the shape of a plurality of substrate support mesa surfaces; reducing the contact area of ​​the plurality of substrate support mesa surfaces; increasing the width of the inner band of the electrostatic chuck; increasing the width of the outer band of the electrostatic chuck; increasing the pressure within the outer channel; and reducing the pressure within the inner channel. Attached Figure Description

[0011] To gain a more detailed understanding of the features described above, reference can be made to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of the present disclosure and should not be construed as limiting the scope of the disclosure, as other equally effective embodiments are permissible.

[0012] Figure 1 A parallel projection view of an electrostatic chuck according to one or more embodiments of the present disclosure is shown;

[0013] Figure 2 A partial cross-sectional view of the outer peripheral edge of an electrostatic chuck according to one or more embodiments of the present disclosure is shown; and

[0014] Figure 3 A partial cross-sectional view of the outer peripheral edge of an electrostatic chuck according to one or more embodiments of the present disclosure is shown. Detailed Implementation

[0015] Before describing several exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the details of the construction or process steps set forth in the following description. This disclosure can have other embodiments and can be practiced or implemented in various ways.

[0016] As used in this specification and the appended claims, the term "substrate" refers to a surface or portion thereof on which a process has been performed. Those skilled in the art will also appreciate that, unless the context clearly indicates otherwise, the designation "substrate" may also refer to only a portion of the substrate. Furthermore, the designation "deposited on a substrate" can mean both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0017] As used herein, “substrate” refers to any substrate on which a film treatment is performed during a manufacturing process, or a material surface formed on a substrate. For example, depending on the application, substrate surfaces on which treatments can be performed include materials such as silicon, silicon oxide, silicon nitride, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, aluminum gallium arsenide, aluminum gallium nitride, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates can be exposed to pretreatment processes such as polishing, etching, reduction, oxidation, hydroxylation, annealing, UV curing, electron beam curing, and / or baking of the substrate surface. In addition to performing film treatments directly on the surface of the substrate itself, any of the disclosed film treatment steps may also be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term “substrate surface” is intended to include the underlayer as indicated by the context. Therefore, for example, in the case where a film / layer or part of a film / layer has already been deposited onto the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0018] One or more embodiments of this disclosure relate to an electrostatic chuck. Some embodiments of this disclosure advantageously provide an electrostatic chuck configured to adjust the hydrogen concentration (H%) across the wafer surface fixed to the electrostatic chuck. Some embodiments of this disclosure advantageously provide an electrostatic chuck having an H% variability range (range divided by 2; R / 2) of less than or equal to about 2%.

[0019] Many variability plots provide the mean of measurements across wafers, as well as the standard deviation and range of values ​​present on the wafer. The range of variability can be expressed as the mean plus or minus a certain range. Because the range of variability extends to both above and below the mean, it is sometimes simply expressed as R / 2, or variability from the mean in only one direction.

[0020] Reference Figure 1 and Figure 2 One or more embodiments of this disclosure relate to an electrostatic chuck 100. Figure 1 A parallel projection view of an electrostatic chuck 100 according to one or more embodiments is shown. Figure 2 A partial cross-sectional view of an electrostatic chuck 100 according to one or more embodiments is shown. The electrostatic chuck 100 shown is a generally dish-shaped body 101, which includes an upper coating 101A and a lower body 101B. The upper coating 101A has a thickness T defining the upper coating 101A. ESC The upper coating 101A has a top surface 102 and a bottom surface 104. The upper coating 101A contacts the lower body 101B such that the top surface of the lower body abuts the bottom surface 104 of the upper coating 101A. The lower body 101B has a bottom surface 105. The thickness of the body 101 (including the upper coating 101A and the lower body 101B) is in the range of about 1.5 inches to about 2.5 inches. In some embodiments, the thickness of the body 101 is about 2 inches.

[0021] In some embodiments, the thickness T of the upper coating 101A ESC It is in the range of about 7 mils to about 15 mils or about 8 mils to about 12 mils. In some embodiments, the thickness T of the upper coating 101A is... ESC It is about 10 mils.

[0022] The outer peripheral edge 106 forms the outer boundary of the body 101. The top surface 102 is configured to support the substrate during processing.

[0023] The top surface 102 of the electrostatic chuck 100 includes a central region 110, an inner channel 120, an inner band 130, an outer channel 140, and an outer band 150. The central region 110 (also referred to as the field of the electrostatic chuck 100) is surrounded by the inner channel 120 at its outer peripheral edge. The intersection 114 of the inner wall 121 of the inner channel 120 and the top surface 112 is the outer peripheral edge of the central region 110.

[0024] The diameter of the central region 110 can vary relative to the overall diameter of the upper coating 101A. The diameter of the central region 110 is measured through the center of the body 101 from the intersection 114 of the inner wall 121 of the inner channel 120 and the top surface 112 of the central region 110. In some embodiments, the ratio of the diameter of the central region 110 to the diameter of the body 101 is in the range of 80% to 95%, or in the range of 85% to 95%, or in the range of 85% to 92%, or in the range of 86% to 90%.

[0025] The inner passage 120 surrounding the central area 110 has a width W IC And with depth D IC It extends into the upper coating 101A of the electrostatic chuck 100. The width W... IC The measurement is the distance between the inner wall 121 and the outer wall 123 of the inner channel 120. Depth D IC The thickness T of the upper coating 101A at the inner channel 120 is measured from the top surface 102 of the upper coating 101A to the bottom surface 122 of the inner channel 120. IC The measurement is taken from the bottom surface 122 of the inner channel 120 to the bottom surface 104 of the upper coating 101A. Figure 2 In the embodiment shown, the depth of the inner channel 120 adjacent to the inner wall 121 is less than the depth D of the inner channel. IC In this embodiment, since the top surface 112 is lower than the supporting surface that serves as the top surface 102, the depth D adjacent to the field of the central region 110 is... IF Smaller.

[0026] According to some embodiments, the width W of the inner channel 120 IC It is in the range of 0.5mm to 5mm, or in the range of 1mm to 5mm, or in the range of 1.5mm to 5mm, or in the range of 2mm to 5mm, or in the range of 2mm to 4.5mm.

[0027] According to one or more embodiments, the depth D of the inner channel 120 IC Less than or equal to 1 mm, 0.75 mm, 0.5 mm, 0.3 mm, or 0.2 mm. In some embodiments, the depth D of the inner channel 120 is... IC The thickness T of the upper coating 101A ESC The range is 10% to 90%, 20% to 80%, 30% to 70%, or 40% to 60%.

[0028] The inner channel 120 is separated from the outer channel 140 by an inner band 130. The inner band 130 has a top surface 132, which is substantially coplanar with the top surface 102 of the upper coating 101A. When used in this way, the term "substantially coplanar" means that the principal plane formed by the top surface 102 of the upper coating 101A is within ±0.025 mm of the principal plane formed by the top surface 132 of the inner band 130.

[0029] The width W of the inner band can be changed by 130. IB This is to change the spacing between the inner channel 120 and the outer channel 140. A standard electrostatic chuck can have an IB width of approximately 2 mm to approximately 3 mm (more specifically, approximately 2.3 mm to approximately 2.7 mm). In some embodiments, the width W of the inner channel is... IB The IB width is increased by a percentage ranging from about 50% to about 60%, from about 90% to about 110%, or from about 50% to about 110%. In some embodiments, the IB width is increased by an amount ranging from about 1.2 mm to about 1.6 mm, from about 2.0 mm to about 3.0 mm, or from about 1.2 mm to about 3.0 mm.

[0030] The outer channel 140 surrounding the inner band 130 has a width W OC And with depth D OC It extends into the upper coating 101A of the electrostatic chuck 100. The width W... OC The measurement is the distance between the inner wall 141 and the outer wall 143 of the outer channel 140. Depth D OC The thickness T of the upper coating 101A at the outer channel 140 is measured from the top surface 102 of the upper coating 101A to the bottom surface 142 of the outer channel 140. OC The measurement is taken from the bottom surface 142 of the outer channel 140 to the bottom surface 104 of the upper coating 101A.

[0031] According to some embodiments, the width W of the outer channel 140 OC It is in the range of 0.5mm to 10mm, or in the range of 1mm to 8mm, or in the range of 2mm to 6mm, or in the range of 2.5mm to 5.5mm.

[0032] According to one or more embodiments, the depth D of the outer channel 140 OC Less than or equal to 1 mm, 0.75 mm, 0.5 mm, 0.3 mm, or 0.2 mm. In some embodiments, the depth D of the outer channel 140 is... OC The thickness T of the upper coating 101A ESC The range is 10% to 90%, 20% to 80%, 30% to 70%, or 40% to 60%.

[0033] The outer band 150 is the area of ​​the electrostatic chuck 100 between the outer wall 143 of the outer channel 140 and the outer peripheral edge 106 of the body 101. In some embodiments, the width W of the outer band 150 is... OB The width W of the outer band of a standard electrostatic chuck is within the ranges of 2mm to 5.5mm, 2.2mm to 5.2mm, 3.5mm to 4mm, 4mm to 4.5mm, and 4.75mm to 5.25mm. OB The (OB width) can be from about 1.7 mm to about 2.7 mm, more specifically from about 2.0 mm to about 2.4 mm. In some embodiments, the OB width is increased by a percentage in the range of about 45% to about 55%, about 65% to about 70%, about 45% to about 70%, about 90% to about 110%, about 110% to about 150%, about 120% to about 140%, or about 45% to about 150%. In some embodiments, the OB width is increased by an amount in the range of about 1.3 mm to about 1.7 mm, about 2.8 mm to about 3.1 mm, or about 1.3 mm to about 3.1 mm.

[0034] exist Figure 1 and Figure 2 In the illustrated embodiment, the central region 110 includes a plurality of substrate support platforms 115. The substrate support platforms 115 extend from the top surface 112 of the central region 110 to the top surface 116 of the substrate support platforms 115. In some embodiments, the top surfaces 116 of the plurality of substrate support platforms 115 are substantially coplanar with each other. In some embodiments, the top surface 116 of the substrate support platforms 115 is substantially coplanar with the top surface 102 of the upper coating 101A. The height of the substrate support platforms 115 depends on the height difference between the top surface 112 of the central region 110 and the top surface 102 of the upper coating 101A.

[0035] The substrate support platform 115 can be of any suitable shape. Although Figure 1 A rectangular tabletop is shown, but those skilled in the art will recognize that this is for illustrative purposes only, and the present disclosure is not limited to rectangular or square tabletops. In some embodiments, the substrate support tabletop 115 has a shape selected from one or more of the following: square, rectangle, circle, oval, triangle, polygon (e.g., pentagon, hexagon, etc.), star, rhombus, trapezoid, cross, flower, semicircle, or crescent.

[0036] Figure 3A partial cross-sectional view of an electrostatic chuck 100 according to one or more embodiments of the present disclosure is shown. The electrostatic chuck 100 shown includes a substrate 250 shown on a top surface 102. In some embodiments, the substrate 250 contacts a substrate support platform 115, an inner band 130, and an outer band 150. Although the substrate support platform 115 is shown with a shading different from that of the body 101 of the electrostatic chuck 100, those skilled in the art will recognize that this is for illustrative purposes only. In some embodiments, the substrate support platform 115 is made of the same material as the remainder of the electrostatic chuck 100. Shading is provided to easily distinguish the contact areas.

[0037] The electrostatic chuck 100 further includes a controller 160. In some embodiments, the controller 160 is coupled to the electrostatic chuck 100. In some embodiments, the controller 160 is coupled to one or more of the inner channel 120 or the outer channel 140. In some embodiments, there is more than one controller 160 connected to the respective channels, and a primary control processor is coupled to each of the individual processors to control the electrostatic chuck 100.

[0038] The controller 160 can be any form of general-purpose computer processor, microcontroller, microprocessor, etc., that can be used in an industrial environment to control various channels and subprocessors.

[0039] The controller 160 may include a processor 162, a memory 164 coupled to the processor 162, an input / output device 166 coupled to the processor 162, and support circuitry 168 for communication between different electronic components. The memory 164 may include one or more of temporary memory (e.g., random access memory) and non-temporary memory (e.g., storage).

[0040] The processor 162's memory 164 or computer-readable medium can be one or more readily available memories, such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of local or remote digital storage. The memory 164 can store an instruction set that can be operated by the processor 162 to control the parameters and components of the electrostatic chuck 100.

[0041] Support circuitry 168 is coupled to processor 162 to provide conventional support for processor 162. This circuitry may include, for example, cache, power supply, clock circuitry, input / output circuitry systems, subsystems, etc.

[0042] The process can typically be stored in memory as a software routine, which, when executed by processor 162, causes the electrostatic chuck to perform the process of this disclosure. The software routine can also be stored and / or executed by a second processor (not shown), which is remote from the hardware controlled by the processor. Some or all of the methods of this disclosure can also be executed in hardware. Thus, the process can be implemented in software and executed using a computer system, implemented in hardware such as application-specific integrated circuits or other types of hardware implementations, or implemented as a combination of software and hardware. When executed by the processor, the software routine transforms a general-purpose computer into a dedicated computer (controller) that controls the operation of the chamber to cause the process to be executed.

[0043] In some embodiments, controller 160 has one or more configurations to perform various processes or subprocesses to execute a method. Controller 160 can be connected to and configured to operate intermediate components to perform the functions of the method. For example, controller 160 can be connected to and configured to control one or more of a gas valve, heater, mass flow controller, etc.

[0044] The controller 160 in some embodiments has one or more configurations selected from: a configuration for clamping and / or declamping a substrate on an electrostatic chuck; a configuration for monitoring hydrogen concentration across a wafer; a configuration for monitoring surface temperature across a wafer; a configuration for controlling pressure within an inner channel; or a configuration for controlling pressure within an outer channel.

[0045] As previously discussed, current electrostatic chuck designs limit the maximum gas pressure in the external cooling channels before leakage issues arise. Accordingly, this disclosure identifies several methods for modifying current electrostatic chucks to provide better control over the temperature across the wafer, and thus better control over the hydrogen (H) concentration across the wafer.

[0046] One or more embodiments of this disclosure advantageously provide an electrostatic chuck with improved external cooling. Some embodiments provide an electrostatic chuck with improved cooling fluid leakage rate. Some embodiments provide an ESC with improved cooling at the ESC / wafer edge, resulting in a higher hydrogen percentage radial adjustment range, improved wet etch rate (WER), and / or minimized or eliminated gate-induced drain leakage.

[0047] In some embodiments, the cooling fluid comprises one or more of helium, neon, argon, krypton, or xenon. In some embodiments, the cooling fluid is substantially composed of helium.

[0048] Current ESC designs can achieve pressures of approximately 20 Torr at each of the inner and outer channels. Conventional ESCs with pressures of 4 Torr and 10 Torr at the inner and outer channels, respectively, have been observed to result in hydrogen non-uniformity of approximately 8.7%. The inventors were surprised to find that an inner-to-outer-channel pressure ratio of 6 Torr:14 Torr resulted in a hydrogen non-uniformity of only 0.5%. Without being bound by any particular operating theory, it is believed that GIDL is eliminated or minimized by varying the back-side pressures of the inner and outer channels. Some embodiments advantageously provide hydrogen percentage non-uniformity of less than approximately 5%, 4%, 3%, or 2% for processes at 315°C. Some embodiments provide improved wafer cooling efficiency. Some embodiments achieve higher outer channel setpoints, lower inner channel setpoints, and higher outer-to-inner-channel ratios for process tuning. Some embodiments reduce the helium leakage rate of the ESC / substrate. Some embodiments provide improved substrate temperature control.

[0049] One embodiment of this disclosure provides an electrostatic chuck with reduced surface roughness. Without being bound by theory, reducing the surface roughness of the top surface of the electrostatic chuck provides more efficient heat transfer between the substrate support mesa and the wafer. Furthermore, reducing the surface roughness of the top surface of the electrostatic chuck provides a larger surface area and stronger clamping force in both the inner and outer bands, thereby reducing gas leakage from the inner and / or outer channels.

[0050] In some embodiments, the surface roughness of one or more of the plurality of substrate support surfaces 115, inner band 130, or outer band 150 is reduced relative to a standard electrostatic chuck. In some embodiments, the surface roughness is reduced by soft polishing one or more of the plurality of substrate support surfaces 115, inner band 130, or outer band 150. In some embodiments, the surface roughness of the outer band is reduced by an amount ranging from about 70% to about 90% relative to a standard electrostatic chuck.

[0051] For example, a standard electrostatic chuck may have a surface roughness ranging from about 25 Ra to about 40 Ra. In some embodiments, the surface roughness of the outer band is reduced to less than or equal to about 25 Ra, less than or equal to about 20 Ra, less than or equal to about 15 Ra, less than or equal to about 10 Ra, or less than or equal to about 7 Ra. In some embodiments, the surface roughness is reduced to about 6 Ra. In some embodiments, the surface roughness is in the range of about 10 Ra to about 25 Ra or about 15 Ra to about 20 Ra. In some embodiments, the surface roughness is measured using a surface profilometer.

[0052] Another embodiment of this disclosure provides an electrostatic chuck with reduced substrate support platforms. In some embodiments, the number of substrate support platforms is reduced. In some embodiments, the contact area of ​​the substrate support platforms is reduced. In some embodiments, the percentage of the central region covered by the substrate support platforms is reduced. In some embodiments, the ratio between the perimeter and area of ​​each substrate support platform is reduced.

[0053] Unbound by theory, it is believed that each of the modifications proposed above reduces conductive heat transfer through the substrate support mesa. While convective heat transfer will still occur, a relatively large amount of heat transfer is expected to occur through the inner and outer bands, where heat transfer can be more easily controlled using inner and outer channels.

[0054] For example, a standard electrostatic chuck can have a square base plate support surface, where each surface has a diameter greater than or equal to approximately 11 mm. 2 The number of tables on a standard electrostatic chuck can result in a contact coverage of approximately 12% or more of the total area of ​​the top surface of the electrostatic chuck, or approximately 15% or more of the total area.

[0055] In some embodiments, the substrate support platform is circular in shape. In some embodiments, each platform has a diameter of less than or equal to approximately 10 mm. 2 The contact area. In some embodiments, the number of tabletops results in a contact coverage of about 10%, about 7%, or about 5% of the total area of ​​the electrostatic chuck, which is less than or equal to the total area.

[0056] Further embodiments of this disclosure provide electrostatic chucks with wider inner and / or outer bands. Without being bound by theory, it is believed that wider inner and / or outer bands provide increased heat transfer between the electrostatic chuck and the wafer. It is also believed that wider outer bands can help prevent cooling gas leakage from the outer channel. Furthermore, it is believed that wider inner bands can enable greater pressure variations between the inner and outer channels.

[0057] Additional embodiments of this disclosure provide an electrostatic chuck with increased pressure in the outer channel and / or decreased pressure in the inner channel. Without being bound by theory, it is believed that the increased pressure difference between the outer and inner channels provides greater control over the temperature uniformity of the wafer. It is also believed that the physical modifications to the standard electrostatic chuck outlined in this disclosure allow for even greater pressure differences.

[0058] In some embodiments, the maximum pressure of the coolant in the inner and outer channels is about 20 Torr. In some embodiments, the minimum pressure in the inner and outer channels is about 2 Torr.

[0059] In some embodiments, the pressure within the inner channel (IC pressure) is less than the pressure within the outer channel (OC pressure). In some embodiments, the IC pressure is less than or equal to about 6 Torr, less than or equal to about 5.5 Torr, or less than or equal to about 5 Torr. In some embodiments, the OC pressure is greater than or equal to about 14 Torr, greater than or equal to about 15 Torr, greater than or equal to about 17 Torr, or greater than or equal to about 19 Torr.

[0060] In some embodiments, the difference between IC pressure and OC pressure is greater than or equal to about 8 Torr, greater than or equal to about 10 Torr, greater than or equal to about 12 Torr, or greater than or equal to about 14 Torr. In some embodiments, the ratio of OC pressure to IC pressure is greater than or equal to about 2.5, greater than or equal to about 3, or greater than or equal to about 4. In some embodiments, the ratio of OC pressure to IC pressure is in the range of about 2.5 to about 4, in the range of about 3 to about 4, or in the range of about 3.5 to about 4.

[0061] Not bound by theory, various embodiments of this disclosure improve the control of wafer temperature (temperature uniformity) across wafers. Temperature is believed to be related to the hydrogen concentration (H%) in the film produced by the high-density plasma (HDP) deposition process. The increased H% is also related to the wet etch rate (WER) and wet etch rate ratio (WERR) of the deposited film.

[0062] Assuming that improved temperature control in some embodiments allows for increased temperature uniformity across the wafer surface during HDP processes, some embodiments of this disclosure also provide increased H% uniformity and increased WERR uniformity across the wafer. In some embodiments, the electrostatic chuck is configured to have an H% across the wafer with a range (R / 2) less than or equal to about 2%, less than or equal to about 1%, or less than or equal to about 0.5%.

[0063] Example

[0064] Five electrostatic chuck samples with a diameter of approximately 300 mm were prepared, exhibiting varying dimensions and properties as shown in Table 1. Unless otherwise specified, all dimensions are normalized to sample 1. Table 1

[0065] The average temperature of the wafers during processing was estimated for samples 1-4 at various setpoints under IC and OC pressures. Temperatures were measured using an infrared optical thermometer with a wavelength of approximately 1 μm. Temperatures were measured on the back side of the wafer through a small hole in the central region of an electrostatic chuck. The thermometer could not measure temperatures below 193°C. Temperatures of 193°C (or lower) are presented as "low" in Tables 2A-2D.

[0066] The data are grouped by IC pressure in Tables 2A-2D. In some cases, due to leakage, a higher OC pressure cannot be maintained. These cases are marked with a dash. Table 2A – IC pressure = 2 Torr Table 2B – IC pressure = 4 Torr Table 2C–IC pressure = 6 Torr Table 2D-IC pressure = 8 Torr

[0067] SiO2 samples were prepared using the HDP method on each of the electrostatic chuck samples, taking into account the varying pressure within the inner and outer channels. The substrate temperature was set at 315°C, but due to the cooling of the inner and outer channels, there was a significant temperature variation across the substrate surface.

[0068] The prepared SiO2 films were evaluated for wet etching rates across the wafer surface and normalized to form the radial profile for each sample. To evaluate the wet etching rate, the oxide film thickness on the wafer surface was measured before and after immersion in a 1% HF solution for a controlled time. A summary of the results for samples 1–4 is provided in Table 3. All pressures are provided in Torr. For each combination of IC and OC pressures, the average wet etching rate across the wafer has been normalized to 1. Standard deviation and R / 2 (copied as 1Sig / R / 2) are provided as indicators of the differences in wet etching rates across the wafer. For samples 1–3, higher OC pressures could not be maintained due to leakage. These cases are marked with dashes. Table 3 - Standard Deviation and Range of Normalized Wet Etching Rate

[0069] Throughout this specification, the references to "one embodiment," "some embodiments," "one or more embodiments," or "embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the described embodiment is included in at least one embodiment of this disclosure. Therefore, phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" appearing in various places throughout this specification do not necessarily refer to the same embodiment of this disclosure. Furthermore, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments.

[0070] Although the disclosure herein has been described with reference to specific embodiments, those skilled in the art will understand that the embodiments described are merely illustrative of the principles and applications of this disclosure. Those skilled in the art will understand that various modifications and variations can be made to the methods and apparatus of this disclosure without departing from the spirit and scope of this disclosure. Therefore, this disclosure may include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. An electrostatic chuck, comprising: A top surface and a bottom surface, the top surface comprising: The central region includes multiple substrate support platforms; An inner channel IC, the inner channel IC having an IC width and surrounding the central region; An inner band IB has an IB width and surrounds the inner channel, wherein the depth of the inner channel from the top surface of the central region to the bottom surface of the IC is less than the depth from the top surface of the IB to the bottom surface of the IC. An outer channel OC, the outer channel OC having a width of OC and surrounding the inner band; and Outer band OB, the outer band OB having a width of OB and surrounding the outer channel; and A controller configured to control the temperature of the wafer across the top surface fixed to the electrostatic chuck during processing.

2. The electrostatic chuck of claim 1, wherein the maximum pressure of the coolant in the IC and the OC is 20 Torr.

3. The electrostatic chuck as claimed in claim 1, wherein the pressure in the inner channel is IC pressure and the pressure in the outer channel is OC pressure, wherein the IC pressure is less than the OC pressure.

4. The electrostatic chuck of claim 3, wherein the difference between the IC pressure and the OC pressure is greater than or equal to 8 Torr.

5. The electrostatic chuck as claimed in claim 3, wherein the OC pressure is greater than or equal to 14 Torr.

6. The electrostatic chuck of claim 3, wherein the ratio of the OC pressure to the IC pressure is in the range of 2.5 to 4.

7. An electrostatic chuck, comprising: A top surface and a bottom surface, the top surface comprising: The central region includes multiple substrate support platforms; An inner channel IC, the inner channel IC having an IC width and surrounding the central region; An inner band IB has an IB width and surrounds the inner channel, wherein the depth of the inner channel from the top surface of the central region to the bottom surface of the IC is less than the depth from the top surface of the IB to the bottom surface of the IC. An outer channel OC, the outer channel OC having a width of OC and surrounding the inner band; and An outer band OB, the outer band OB having a width of OB and surrounding the outer channel. The electrostatic chuck is configured to have H% across the wafer during processing, the H% having an R / 2 of less than or equal to 2%, the R / 2 being a range of variability.

8. The electrostatic chuck of claim 7, wherein the R / 2 span across the wafer is less than or equal to 0.5%.

9. The electrostatic chuck of claim 7, wherein, relative to a standard electrostatic chuck, the surface roughness of one or more of the plurality of substrate support surfaces, the inner band, or the outer band is reduced.

10. The electrostatic chuck of claim 9, wherein the reduction in surface roughness of the outer strip is in the range of 70% to 90%.

11. The electrostatic chuck of claim 7, wherein the plurality of substrate support platforms are circular in shape.

12. The electrostatic chuck of claim 7, wherein the contact area of ​​the plurality of substrate support platforms is reduced relative to a standard electrostatic chuck.

13. The electrostatic chuck of claim 7, wherein the area of ​​the plurality of substrate support platforms is less than 10% of the total area of ​​the top surface.

14. The electrostatic chuck of claim 7, wherein the OB width is increased by a percentage in the range of 65% to 70% relative to a standard electrostatic chuck.

15. The electrostatic chuck of claim 7, wherein the OB width is increased by an amount ranging from 1.3 mm to 1.7 mm.

16. The electrostatic chuck of claim 7, wherein the OB width is increased by a percentage in the range of 110% to 150% relative to a standard electrostatic chuck.

17. The electrostatic chuck of claim 7, wherein the OB width is increased by an amount ranging from 2.8 mm to 3.1 mm.

18. The electrostatic chuck of claim 7, wherein the IB width is increased by a percentage in the range of 50% to 60% relative to a standard electrostatic chuck.

19. The electrostatic chuck of claim 7, wherein the IB width is increased by an amount ranging from 1.2 mm to 1.6 mm.

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