Timing adjustment circuit, timing asymmetry elimination method, and receiving circuit

Abstract

The present invention relates to a timing adjustment circuit, a timing asymmetry elimination method, and a receiving circuit. The timing adjustment circuit includes: N data synchronization circuits and a controller. The nth data synchronization circuit among the N data synchronization circuits includes: the nth instruction sensor and the nth buffer. When the nth input data stream meets the single-channel preset condition, the nth instruction sensor changes the level of the nth instruction sensing signal. The nth buffer stores the nth input data stream in response to the change in the level of the nth instruction sensing signal. The controller receives the nth instruction sensing signal and changes the level of the instantaneous signal when the full-channel preset condition is met. Among them, the nth buffer outputs the nth timing symmetric data stream in response to the change in the level of the instantaneous signal.

Description

Technical Field

[0001] The present invention relates to a timing adjustment circuit, a timing asymmetry elimination method, and a receiving circuit, and more particularly to a timing adjustment circuit, a timing asymmetry elimination method, and a receiving circuit for solving the problem of timing asymmetry of data transmitted through multiple data channels. Background Art

[0002] The Peripheral Component Interconnect Express (PCIe) specification is an important input / output (I / O) interface. Therefore, transmission and reception systems adopting the PCIe architecture are quite popular.

[0003] Please refer to Figure 1 , which is a schematic diagram of a PCIe transmission and reception system. A transmitter 11 transmits read data rxDAT to a receiver 13. The receiver 13 includes a Physical Layer (PHY) interface circuit 131 and a Media Access Control (MAC) circuit 133. After converting the read data rxDAT transmitted in a serial manner into an input data stream inDAT in a parallel format, the Physical Layer (PHY) interface circuit 131 transmits the input data inDAT to the Media Access Control (MAC) circuit 133.

[0004] PCIe supports a multi-lane architecture. The number N of data lanes is a positive integer and N is equal to a power of 2. In an ideal situation, when adopting a multi-lane architecture, the timings of the input data streams inDAT(L1) to inDAT(LN) transmitted through the respective data lanes Lane_1 to Lane_N can be kept consistent. However, in an actual circuit, when adopting a multi-lane architecture of Lane_1 to Lane_N, the input data streams inDAT(L1) to inDAT(LN) may be generated successively, resulting in inconsistent timings between the data lanes. This situation where the input data streams inDAT(L1) to inDAT(LN) cannot be kept consistent due to the adoption of a multi-lane architecture of Lane_1 to Lane_N is called lane-to-lane skew.

[0005] Please refer to Figure 2A, which is a schematic diagram of the input data streams inDAT(L1) to inDAT(L4) generated by the physical layer interface circuit (PHY) under ideal conditions. In this diagram, the vertical axis represents the input data streams inDAT(L1) to inDAT(L4) corresponding to data channels Lane_1 to Lane_4 respectively, and the horizontal axis represents time. The interval between each time point t1 to t9 on the horizontal axis is the symbol period Tsym required to transmit one byte (equivalent to one symbol). Each input data stream inDAT(L1) to inDAT(L4) contains multiple input bytes inByte. Among them, every four adjacent input bytes inByte in the same data channel Lane_1 to Lane_4 can be defined as a doubleword (abbreviated as DW). To indicate the bit order of the bytes, the most significant bit (abbreviated as MSB) and the least significant bit (abbreviated as LSB) are marked above each byte.

[0006] The input data stream inDAT(L1) corresponding to data channel Lane_1 includes: input bytes inByte1, inByte5, inByte9, inByte13, inByte17, inByte21, inByte25, inByte29, etc. Among them, the first input byte inByte1, the second input byte inByte5, the third input byte inByte9, and the fourth input byte inByte13 of the input data stream inDAT(L1) together form data doubleword DW11; and, the fifth input byte inByte17, the sixth input byte inByte21, the seventh input byte inByte25, and the eighth input byte inByte29 of the input data stream inDAT(L1) together form data doubleword DW12.

[0007] The input data stream inDAT(L2) corresponding to data channel Lane_2 includes: input bytes inByte2, inByte6, inByte10, inByte14, inByte18, inByte22, inByte26, inByte30, etc. Among them, the first input byte inByte2, the second input byte inByte6, the third input byte inByte10, and the fourth input byte inByte14 of the input data stream inDAT(L2) together form data double word DW21; and, the fifth input byte inByte18, the sixth input byte inByte22, the seventh input byte inByte26, and the eighth input byte inByte30 of the input data stream inDAT(L2) together form data double word DW22.

[0008] The input data stream inDAT(L3) corresponding to data channel Lane_3 includes: input bytes inByte3, inByte7, inByte11, inByte15, inByte19, inByte23, inByte27, inByte31, etc. Among them, the first input byte inByte3, the second input byte inByte7, the third input byte inByte11, and the fourth input byte inByte15 of the input data stream inDAT(L3) together form data double word DW31; and, the fifth input byte inByte19, the sixth input byte inByte23, the seventh input byte inByte27, and the eighth input byte inByte31 of the input data stream inDAT(L3) together form data double word DW32.

[0009] The input data stream inDAT(L4) corresponding to data channel Lane_4 includes: input bytes inByte4, inByte8, inByte12, inByte16, inByte20, inByte24, inByte28, inByte32, etc. Among them, the first input byte inByte4, the second input byte inByte8, the third input byte inByte12, and the fourth input byte inByte16 of the input data stream inDAT(L4) together form data double word DW41; and, the fifth input byte inByte20, the sixth input byte inByte24, the seventh input byte inByte28, and the eighth input byte inByte32 of the input data stream inDAT(L4) together form data double word DW42.

[0010] Ideally, the timing of the input data streams inDAT(L1) to inDAT(L4) can be kept consistent. For example, as Figure 2A shown, the data double words DW11 of the input data stream inDAT(L1), the data double words DW21 of the input data stream inDAT(L2), the data double words DW31 of the input data stream inDAT(L3), and the data double words DW41 of the input data stream inDAT(L4) are output simultaneously during time points t1 to t5. Also, the data double words DW12 of the input data stream inDAT(L1), the data double words DW22 of the input data stream inDAT(L2), the data double words DW32 of the input data stream inDAT(L3), and the data double words DW42 of the input data stream inDAT(L4) are output simultaneously during time points t5 to t9.

[0011] On the other hand, if there are signal delays of varying degrees in the transmission paths of data channels Lane_1 to Lane_4, the timing of the input data streams inDAT(L1) to inDAT(L4) cannot be kept consistent. In actual situations, the patterns in which the timing of the input data streams inDAT(L1) to inDAT(L4) cannot be kept consistent may be different. Figure 2B Shown is a possible case of timing inconsistency.

[0012] Please refer to Figure 2B , which is a schematic diagram of the input data streams inDAT(L1) to inDAT(L4) generated by a physical layer interface circuit (PHY) in an actual situation. In this diagram, the data double words DW11 of the input data stream inDAT(L1) and the data double words DW41 of the input data stream inDAT(L4) are aligned, and the data double words DW21 of the input data stream inDAT(L2) and the data double words DW31 of the input data stream inDAT(L3) are aligned. However, the data double words DW11 of the input data stream inDAT(L1) and the data double words DW41 of the input data stream inDAT(L4) are not aligned with the data double words DW21 of the input data stream inDAT(L2) and the data double words DW31 of the input data stream inDAT(L3).

[0013] In data channels Lane_1 and Lane_4, the data double-word groups aligned with the data double-word group DW21 of the input data stream inDAT(L2) are the data double-word group DW12 of the input data stream inDAT(L1) and the data double-word group DW42 of the input data stream inDAT(L4). That is, the reception time points (time point t5) of the data double-word group DW21 of the input data stream inDAT(L2) and the data double-word group DW31 of the input data stream inDAT(L3) lag behind the reception time points (time point t1) of the data double-word group DW11 of the input data stream inDAT(L1) and the data double-word group DW41 of the input data stream inDAT(L4) by a range of one double-word period Tdw. In this article, the time difference between data channels Lane_1 to Lane_4 for receiving the input data streams inDAT(L1) to inDAT(L4) is defined as the timing asymmetry period Tdiff between data channels Lane_1 to Lane_4.

[0014] Once the media access control circuit (MAC) 133 receives inconsistent timings of the input data streams inDAT(L1) to inDAT(L4), the media access control circuit (MAC) 133 cannot correctly parse the transaction layer packet (TLP) and the data link layer packet (DLLP). Therefore, in order to ensure the normal function of the receiver 13, it is urgent to improve the inconsistent timings of the input data streams inDAT(L1) to inDAT(L4). Summary of the Invention

[0015] The present invention relates to a timing adjustment circuit, a timing asymmetry elimination method, and a receiving circuit for synchronizing data transmitted via multiple data channels.

[0016] According to a first aspect of the present invention, a timing adjustment circuit is provided. The timing adjustment circuit includes: N data synchronization circuits and a controller. The N data synchronization circuits respectively convert N input data streams with inconsistent timings into N timing-symmetrical data streams with consistent timings. The n-th data synchronization circuit among the N data synchronization circuits includes: an n-th instruction sensor and an n-th buffer. When the n-th input data stream among the N input data streams meets a single-channel preset condition, the n-th instruction sensor changes the level of the n-th instruction sensing signal. The n-th buffer stores the n-th input data stream in response to the change in the level of the n-th push signal. The controller is electrically connected to the N data synchronization circuits. The controller receives the n-th instruction sensing signal and changes the level of the instantaneous signal connected to the n-th buffer when the all-channel preset condition is met. Wherein, the n-th buffer outputs the stored n-th input data stream in response to the change in the level of the instantaneous signal, as the n-th timing-symmetrical data stream among the N timing-symmetrical data streams. Wherein, n and N are positive integers, and n is less than or equal to N.

[0017] According to a second aspect of the present invention, a method for eliminating timing asymmetry applied to a timing adjustment circuit is provided. The method for eliminating timing asymmetry includes the following steps. First, receive N input data streams with inconsistent timings from a physical layer interface circuit. Secondly, when the n-th input data stream meets the single-channel preset condition, store the n-th input data stream (inDAT(Ln). And, when the all-channel preset condition is met, transmit the stored N input data streams as N timing-symmetrical data streams with consistent timings. Wherein, the all-channel preset condition is related to the single-channel preset condition. Thereafter, transmit the N timing-symmetrical data streams to a media access control circuit. Wherein, n and N are positive integers, and n is less than or equal to N.

[0018] According to a third aspect of the present invention, a receiving circuit is provided. The receiving circuit includes: a physical layer interface circuit, a media access control circuit, and a timing adjustment circuit. A physical layer interface circuit generates N input data streams with inconsistent timing. The media access control circuit receives N timing-symmetric data streams with consistent timing. The timing adjustment circuit is electrically connected to the physical layer interface circuit and the media access control circuit. The timing adjustment circuit includes: N data synchronization circuits and a controller. The N data synchronization circuits respectively convert the N input data streams into N timing-symmetric data streams. Wherein, the nth data synchronization circuit includes: an nth instruction sensor, and an nth buffer. The nth instruction sensor changes the level of the nth instruction sensing signal when the nth input data stream meets the single-channel preset condition. The nth buffer stores the nth input data stream in response to the change in the level of the nth back push signal. The controller is electrically connected to the N data synchronization circuits. The controller receives the nth instruction sensing signal and changes the level of the instantaneous signal connected to the nth buffer when the full-channel preset condition is met. Wherein, the nth buffer outputs the stored nth input data stream in response to the change in the level of the instantaneous signal as the nth timing-symmetric data stream. Where n and N are positive integers, and n is less than or equal to N. Brief Description of the Drawings

[0019] For a better understanding of the above and other aspects of the present invention, specific embodiments are given below and described in detail in conjunction with the accompanying drawings as follows:

[0020] Figure 1 , which is a schematic diagram of a PCIe transmission and reception system;

[0021] Figure 2A , which is a schematic diagram of the input data streams inDAT(L1)~inDAT(L4) generated by the physical layer interface circuit (PHY) under ideal conditions;

[0022] Figure 2B , which is a schematic diagram of the input data streams inDAT(L1)~inDAT(L4) generated by the physical layer interface circuit (PHY) in actual situations;

[0023] Figure 3 , which is a schematic diagram of providing a timing adjustment circuit between the physical layer interface circuit (PHY) and the media access control circuit (MAC);

[0024] Figure 4 , which is a schematic diagram of the timing-symmetric data streams algnDAT(L1)~algnDAT(L4) generated by the timing adjustment circuit;

[0025] Figure 5 , which is a block diagram of a timing adjustment circuit corresponding to data channels Lane_1~Lane_N;

[0026] Figure 6 , which is a block diagram of an instruction sensor;

[0027] Figure 7 , which is a waveform diagram of a timing adjustment circuit converting an input data stream inDAT with inconsistent timing into a timing-symmetrical data stream algnDAT with consistent timing;

[0028] Figure 8 , which is a flowchart of a timing adjustment circuit; and

[0029] Figures 9A - 9C , which is a schematic diagram illustrating the implementation manner of a timing adjustment circuit.

[0030] Among them, the reference numerals are explained as follows:

[0031] 11: Transmitter

[0032] rxDAT: Read data

[0033] 131, PHY, 41: Physical layer interface circuit

[0034] inDAT: Input data stream

[0035] 133, MAC, 43: Media access control circuit

[0036] 13, 40: Receiver

[0037] inDAT(L1)~inDAT(L4), inDAT(LN), inDAT(Ln): Input data stream

[0038] t1~t14: Time points

[0039] MSB: Most significant bit

[0040] LSB: Least significant bit

[0041] inByte1~inByte32, inByte36, inByte40: Input bytes

[0042] DW11, DW21, DW31, DW41, DW12, DW22, DW32, DW42, DW13, DW14, DW15, DW16, DW17, DW18, DW19, DW110, DW23, DW24, DW25, DW26, DW27, DW33, DW34, DW35, DW36, DW37, DW38, DW43, DW44, DW45, DW46, DW47, DW48, DW49: Data double words

[0043] Tsym: Symbol period

[0044] Tdw: Double-word period

[0045] 45: Timing adjustment circuit

[0046] det(1), det(N), det(n): Instruction sense signal(s)

[0047] push(1), push(N), push(n), push(2) ~ push(4): Push signal lines

[0048] Spop: Momentary signal(s)

[0049] Sflush: Clear signal(s)

[0050] 451, 453, 455: Data synchronization circuit

[0051] 450: Controller

[0052] algnDAT(L1), algnDAT(LN), algnDAT(Ln): Timing-symmetric data stream

[0053] algnByte1 ~ algnByte32: Timing-adjusted bytes

[0054] 451a, 453a, 455a, DET1, DETn, DETN: Instruction sensors

[0055] BUF1, BUn, BUN, 451c, 453c, 455c: Buffers

[0056] 4531: Instruction receiving circuit

[0057] 4535: Instruction comparison circuit

[0058] 4533a: First part of instruction register

[0059] 4533b: Second part of instruction register

[0060] 4533c: Third part of instruction register

[0061] 4533d: Fourth part of instruction register

[0062] cmdDW1, cmdDW2, cmdDW3, cmdDW4: Instruction double words

[0063] 4533: Instruction register

[0064] CLK: Clock signal

[0065] EIEOS: Electrical Idle Escape Instruction Set

[0066] Tord: During Instruction

[0067] Tbuff(1), Tbuff(2), Tbuff(3), Tbuff(4): During Buffer

[0068] S801, S803, S807, S809, S811, S813, S815, S817: Steps

[0069] Qth: Symbol Quantity Threshold Detailed Implementation Manner

[0070] To ensure that the input of the Media Access Control circuit (MAC) is data with symmetric timing, a timing adjustment circuit is provided between the Physical Layer Interface circuit (PHY) and the Media Access Control circuit (MAC) in the present disclosure. The timing adjustment circuit is used to adjust the timing of the out-of-sync input data streams inDAT(L1) to inDAT(LN), and then generate synchronous symmetric-timing data streams algnDAT(L1) to algnDAT(LN). After that, the timing adjustment circuit transmits the symmetric-timing data streams algnDAT(L1) to algnDAT(LN) to the Media Access Control circuit (MAC). Accordingly, the Media Access Control circuit (MAC) can accurately perform packet parsing based on the symmetric-timing data streams algnDAT(L1) to algnDAT(LN).

[0071] Please refer to Figure 3 , which is a schematic diagram showing the provision of a timing adjustment circuit between the Physical Layer Interface circuit (PHY) and the Media Access Control circuit (MAC). For ease of explanation, the same symbols are used in this text to represent signal lines and the signals transmitted by the signal lines.

[0072] In Figure 3In this case, the receiver 40 includes: a physical layer interface circuit (PHY) 41, a timing adjustment circuit 45, and a media access control circuit (MAC) 43. Among them, the timing adjustment circuit 45 is electrically connected to the physical layer interface circuit (PHY) 41 through the input data lines (inDAT(L1)~inDAT(LN)), and is electrically connected to the media access control circuit (MAC) 43 through the timing symmetric data lines (algnDAT(L1)~algnDAT(LN)). According to the concept of the present disclosure, although the timing adjustment circuit 45 receives the input data streams inDAT(L1)~inDAT(LN) from the physical layer interface circuit (PHY) 41 successively, the timing of the timing symmetric data streams algnDAT(L1)~algnDAT(LN) output by the timing adjustment circuit 45 remains consistent. Accordingly, the media access control circuit (MAC) 43 can correctly analyze the packets.

[0073] The timing adjustment circuit 45 includes a controller 450 and N data synchronization circuits 451 respectively corresponding to channels Lane_1~Lane_N. Among them, the controller 450 is electrically connected to the data synchronization circuits 451 through the instruction sensing signal lines det(1)~det(N), the push signal lines push(1)~push(N), the momentary signal line Spop, and the clear signal line Sflush. For ease of explanation, the following embodiments assume N = 4. In actual applications, the value of N is not limited thereto.

[0074] Please refer to Figure 4 , which is a schematic diagram of the timing symmetric data streams algnDAT(L1)~algnDAT(L4) generated by the timing adjustment circuit. In this diagram, the vertical axis represents the timing symmetric data streams algnDAT(L1)~algnDAT(L4) respectively, and the horizontal axis represents time. The distance between each adjacent time point t1~t9 on the horizontal axis is Tsym. Among them, the timing symmetric data streams algnDAT(L1)~algnDAT(L4) respectively correspond to the data channels Lane_1~Lane_4.

[0075] The timing-symmetrical data stream algnDAT(L1) corresponding to data channel Lane_1 includes: timing-adjusted bytes algnByte1, algnByte5, algnByte9, algnByte13, algnByte17, algnByte21, algnByte25, algnByte29, etc. The first timing-adjusted byte algnByte1, the second timing-adjusted byte algnByte5, the third timing-adjusted byte algnByte9, and the fourth timing-adjusted byte algnByte13 in the timing-symmetrical data stream algnDAT(L1) together form data double word DW11; and the fifth timing-adjusted byte algnByte17, the sixth timing-adjusted byte algnByte21, the seventh timing-adjusted byte algnByte25, and the eighth timing-adjusted byte algnByte29 in the timing-symmetrical data stream algnDAT(L1) together form data double word DW12.

[0076] The timing-symmetrical data stream algnDAT(L2) corresponding to data channel Lane_2 includes: timing-adjusted bytes algnByte2, algnByte6, algnByte10, algnByte14, algnByte18, algnByte22, algnByte26, algnByte30, etc. The first timing-adjusted byte algnByte2, the second timing-adjusted byte algnByte6, the third timing-adjusted byte algnByte10, and the fourth timing-adjusted byte algnByte14 in the timing-symmetrical data stream algnDAT(L2) together form data double word DW21; and the fifth timing-adjusted byte algnByte18, the sixth timing-adjusted byte algnByte22, the seventh timing-adjusted byte algnByte26, and the eighth timing-adjusted byte algnByte30 in the timing-symmetrical data stream algnDAT(L2) together form data double word DW22.

[0077] The timing-symmetrical data stream algnDAT(L3) corresponding to data channel Lane_3 includes: timing-adjusted bytes algnByte3, algnByte7, algnByte11, algnByte15, algnByte19, algnByte23, algnByte27, algnByte31, etc. The first timing-adjusted byte algnByte3, the second timing-adjusted byte algnByte7, the third timing-adjusted byte algnByte11, and the fourth timing-adjusted byte algnByte15 in the timing-symmetrical data stream algnDAT(L3) together form data double word DW31; and, the fifth timing-adjusted byte algnByte19, the sixth timing-adjusted byte algnByte23, the seventh timing-adjusted byte algnByte27, and the eighth timing-adjusted byte algnByte31 in the timing-symmetrical data stream algnDAT(L3) together form data double word DW32.

[0078] The timing-symmetrical data stream algnDAT(L4) corresponding to data channel Lane_4 includes: timing-adjusted bytes algnByte4, algnByte8, algnByte12, algnByte16, algnByte20, algnByte24, algnByte28, algnByte32, etc. The first timing-adjusted byte algnByte4, the second timing-adjusted byte algnByte8, the third timing-adjusted byte algnByte12, and the fourth timing-adjusted byte algnByte16 in the timing-symmetrical data stream algnDAT(L4) together form data double word DW41; and, the fifth timing-adjusted byte algnByte20, the sixth timing-adjusted byte algnByte24, the seventh timing-adjusted byte algnByte28, and the eighth timing-adjusted byte algnByte32 in the timing-symmetrical data stream algnDAT(L4) together form data double word DW42.

[0079] The timing-symmetrical data streams algnDAT(L1) to algnDAT(L4) output from the self-timing adjustment circuit 45 have consistent timing with each other. For example, the data double-word DW11 of the timing-symmetrical data stream algnDAT(L1), the data double-word DW21 of the timing-symmetrical data stream algnDAT(L2), the data double-word DW31 of the timing-symmetrical data stream algnDAT(L3), and the data double-word DW41 of the timing-symmetrical data stream algnDAT(L4) are aligned with each other. In addition, the data double-word DW12 of the timing-symmetrical data stream algnDAT(L1), the data double-word DW22 of the timing-symmetrical data stream algnDAT(L2), the data double-word DW32 of the timing-symmetrical data stream algnDAT(L3), and the data double-word DW42 of the timing-symmetrical data stream algnDAT(L4) are also aligned with each other.

[0080] According to the concept of the present disclosure, the physical layer interface circuit (PHY) 41 adds the available instructions selected from the instruction set (Ordered Set) defined by PCIe to the input data streams inDAT(L1) to inDAT(LN) as the basis for judging the timing relationship of the data. According to the PCIe definition, the instructions in the instruction set include 16 symbols, and each symbol corresponds to a byte. According to the concept of the present disclosure, the instructions selected from the instruction set for judging whether the timing is consistent can be the Electrical Idle Exit Ordered Set (abbreviated as EIEOS), the Start of Data Stream (abbreviated as SDS) instruction set, etc. For the sake of simplicity of description, the following embodiments assume that the timing adjustment circuit 45 makes a judgment according to the EIEOS instruction. In actual applications, what the instruction for judging the reception time point of the input data stream is, and the content of the instruction, etc., do not affect the operation mode of the timing adjustment circuit 45.

[0081] Please refer to Figure 5 , which is a block diagram of a timing adjustment circuit corresponding to data channels Lane_1 to Lane_N. For the sake of convenience of description, only the data synchronization circuit 451 corresponding to the data channel Lane_1, the data synchronization circuit 453 corresponding to the data channel Lane_n, and the data synchronization circuit 455 corresponding to the data channel Lane_N are shown here.

[0082] The data synchronization circuit 451 includes: an instruction sensor (DET1) 451a and a buffer (BUF1) 451c; the data synchronization circuit 453 includes: an instruction sensor (DET1) 453a and a buffer (BUF n) 453c; the data synchronization circuit 455 includes: an instruction sensor (DET1) 455a and a buffer (BUF N) 455c. Among them, the buffers (BUF1) 451c, (BUF n) 453c, and (BUF N) 455c can adopt first-in-first-out (FIFO) buffers, and the sizes of the buffers (BUF1) 451c, (BUF n) 453c, and (BUF N) 455c are equal.

[0083] After receiving the input data stream inDAT(L1), the data synchronization circuit 451 selectively stores the input data stream inDAT(L1) in the buffer (BUF1) 451c in response to the control of the controller 450, so as to adjust the generation time point of the timing symmetric data stream algnDAT(L1). After receiving the input data stream inDAT(Ln), the data synchronization circuit 453 selectively stores the input data stream inDAT(Ln) in the buffer (BUF n) 453c in response to the control of the controller 450, so as to adjust the generation time point of the timing symmetric data stream algnDAT(Ln). After receiving the input data stream inDAT(LN), the data synchronization circuit 455 selectively stores the input data stream inDAT(LN) in the buffer (BUF N) 455c in response to the control of the controller 450, so as to adjust the generation time point of the timing symmetric data stream algnDAT(LN).

[0084] In Figure 5 it, the controller 450 transmits the instantaneous signal Spop to each of the data synchronization circuits 451, 453, and 455 in a synchronous manner. When the data synchronization circuits 451, 453, and 455 receive the instantaneous signal Spop, the buffers (BUF1) 451c, (BUF n) 453c, and (BUF5) 455c synchronously output the contents of the stored input data streams inDAT(L1), inDAT(Ln), and inDAT(LN) as the channel timing symmetric data streams algnDAT(L1), algnDAT(Ln), and algnDAT(LN).

[0085] In addition to the instantaneous signal Spop, the controller 450 also synchronously issues a clear signal Sflush to each of the data synchronization circuits 451, 453, and 455 when specific conditions are met. For example, the specific condition can be the situation where the number of temporarily stored input data has filled the buffers 451c, 453c, and 455c, but the controller 450 has not yet issued the instantaneous signal Spop to the data synchronization circuits 451, 453, and 455.

[0086] In the data synchronization circuit 451, the instruction sensor (DET1) 451a and the buffer (BUF1) 451c are both electrically connected to the physical layer interface circuit (PHY) 41 and the controller 450, and the buffer (BUF1) 451c is also electrically connected to the media access control circuit (MAC) 43.

[0087] Both the instruction sensor 451a and the buffer 451c receive the input data stream inDAT(L1) from the physical layer interface circuit (PHY) 41. Among them, the instruction sensor 451a selectively changes the level of the instruction sensing signal det(1) according to the content of the input data stream inDAT(L1). When the controller 450 determines that the level of the instruction sensing signal det(1) changes (for example, from a low level to a high level), it correspondingly changes the level of the push signal push(1) transmitted to the buffer (BUF1) (for example, from a low level to a high level).

[0088] When the buffer (BUF1) 451c continuously receives the push signal push(1) with a low level, the buffer (BUF1) 451c does not temporarily store the input data stream inDAT(L1) for a period of time. At this time, the operation of the physical layer interface circuit (PHY) 41 may vary slightly depending on the instruction type used to determine whether the timing is consistent. For example, if the instruction used to determine whether the timing is consistent is the EIEOS instruction, the physical layer interface circuit (PHY) 41 will, in response to the push signal push(1) with a low level, choose to ignore (drop) the input data stream inDAT(L1). Another example is that if the instruction used to determine whether the timing is consistent is the SDS instruction, the physical layer interface circuit (PHY) 41 will, in response to the push signal push(1) with a low level, directly transmit the input data stream inDAT(L1) to the media access control circuit (MAC) 43.

[0089] On the other hand, when the buffer (BUF1) 451c starts to receive the push signal push(1) with a high level, the buffer (BUF1) 451c temporarily stores the input data stream inDAT(L1) for a period of time until the level of the momentary signal Spop or the clear signal Sflush issued by the controller 450 changes. The levels of the momentary signal Spop and the clear signal Sflush change in different situations, so they do not change levels simultaneously. After the buffer (BUF1) 451c receives the momentary signal Spop with a changed level, the buffer (BUF1) 451c starts to gradually transmit the stored data outward. On the other hand, when the buffer (BUF1) 451c detects a change in the level of the clear signal Sflush, the buffer (BUF1) 451c discards the content of the input data stream inDAT(L1) that it has temporarily stored.

[0090] According to the concept of the present disclosure, the internal architectures and operating modes of the respective data synchronization circuits 451, 453, and 455 are similar. Therefore, the connection relationships between the instruction sensors (DETn) 453a, (DETN) 455a and the buffers (BUFn) 453c, (BUFN) 455c in the data synchronization circuits 453 and 455 and the controller 450, the physical layer interface circuit (PHY) 41, and the media access control circuit (MAC) 43, as well as the operating modes of the instruction sensors (DETn) 453a, (DETN) 455a and the buffers (BUFn) 453c, (BUFN) 455c, will not be described herein.

[0091] In Figure 5 , it is assumed that the instruction sensors DET1 to DETN respectively determine whether their respective single-channel preset conditions are satisfied. Once the instruction sensors DET1 to DETN determine that the corresponding input data streams inDAT(L1) to inDAT(LN) contain the preset instruction CMDpre, it is determined that the single-channel preset conditions are established, and corresponding instruction sensing signals det(1) to det(N) are generated to the controller 450. Once the controller 450 receives the instruction sensing signals det(1) to det(N), it will immediately change the levels of the push signals push(1) to push(N) corresponding to the instruction sensing signals det(1) to det(N). From Figure 5 it can be seen that the controller 450 is electrically connected to the buffers BUF1 to BUN through the push signal lines push(1) to push(N) respectively. When the levels of the push signals push(1) to push(N) connected to the buffers BUF1 to BUN change from a low level to a high level, the buffers BUF1 to BUN will temporarily store the contents of the input data streams inDAT(L1) to inDAT(LN) for a period of time.

[0092] Furthermore, the momentary signal Spop and the clear signal Sflush generated by the controller 450 do not need to be generated separately for each of the individual buffers BUF1 to BUN, but are simultaneously transmitted to the buffers BUF1 to BUN. That is, the buffers BUF1 to BUN simultaneously transmit the stored data of the input data streams inDAT(L1) to inDAT(LN) in synchronization with the change in the level of the momentary signal Spop. Alternatively, the buffers BUF1 to BUN simultaneously discard the stored data of the input data streams inDAT(L1) to inDAT(LN) in response to the change in the level of the clear signal Sflush.

[0093] The present disclosure further defines a full-channel preset condition. When the full-channel preset condition is satisfied, the controller 450 will change the level of the momentary signal Spop (for example, from a low level to a high level). The full-channel preset condition means that starting from the time when the controller 450 receives the first generated command sensing signal det(n) (n = 1 to N), the controller 450 can receive the command sensing signals det(1) to det(N) of all data channels within the command period Tord.

[0094] According to the concept of the present disclosure, when the full-channel preset condition is satisfied, the buffers BUF1 to BUFN simultaneously receive the momentary signal Spop transmitted by the controller 450. Once the momentary signal Spop changes from a low level to a high level, the buffers BUF1 to BUFN will synchronously output the data of the internally stored input data streams inDAT(L1) to inDAT(LN) as the time-sequence symmetric data streams algnDAT(L1) to algnDAT(LN).

[0095] Please refer to Figure 6 , which is a block diagram of the command sensor. The command sensor (DETn) 453a includes a command receiving circuit 4531, a command comparison circuit 4535, and a command register 4533. The command comparison circuit 4535 is electrically connected to both the command receiving circuit 4531 and the command register 4533. The command register 4533 includes four parts: the first part command register 4533a, the second part command register 4533b, the third part command register 4533c, and the fourth part command register 4533d. The length of the command register 4533 is determined according to the command length defined by the specifications used by the receiver. For example, for the PCIeGen 3.0 specification, the command length is 128 bits. Accordingly, the four parts of the command register 4533 respectively correspond to the lengths of one command double-word cmdDW1, cmdDW2, cmdDW2, and cmdDW2.

[0096] For the sake of convenience of explanation, it is assumed herein that the preset command CMDpre stored in the command register 4533 is the EIEOS command. In practical applications, the types and numbers of the preset commands CMDpre stored in the command register 4533 do not need to be limited. The command receiving circuit 4531 repeatedly extracts the content that conforms to the preset length (for example, the preset length = 1 double-word = 4 symbols) from the input data stream inDAT(Ln), and then transmits the extracted input command CMDrv(DW) to the command comparison circuit 4535.

[0097] The preset instruction CMDpre(DW) stored in the instruction register 4533 is also transmitted to the instruction comparison circuit 4535. The instruction comparison circuit 4535 compares the content of the preset instruction CMDpre(DW) with that of the input instruction CMDrv(DW). If the contents of the two are the same, the instruction comparison circuit 4535 changes the level of the instruction sensing signal det(n). If the contents of the two are different, the instruction comparison circuit 4535 does not change the level of the instruction sensing signal det(n). When the instruction comparison circuit 4535 determines that the contents of the preset instruction CMDpre(DW) and the input instruction CMDrv(DW) are the same, the instruction sensor (DETn) 453a can stop performing instruction fetching and comparison.

[0098] In the foregoing example, it is assumed that when the contents of the preset instruction CMDpre(DW) and the input instruction CMDrv(DW) are exactly the same, the instruction comparison circuit 4535 will change the level of the instruction sensing signal det(n). To accelerate the speed of the timing adjustment circuit for timing, in actual application, when the instruction comparison circuit 4535 compares the content of the preset instruction CMDpre(DW) with that of the input instruction CMDrv(DW), it can also perform the comparison on a part of them. For example, the preset instruction CMDpre(DW) and the input instruction CMDrv(DW) are each divided into four equal parts, and after comparing the first equal part of the preset instruction CMDpre(DW) with the first equal part of the input instruction CMDrv(DW) (for example, the instruction double word cmdDW1), the level of the instruction sensing signal det(n) is directly determined according to the comparison result of the first equal part. Such considerations in the design can be adjusted according to the system requirements.

[0099] The EIEOS instruction may be different with the version of PCIe. For example, according to the PCIe Gen 3.0 specification, the format of the EIEOS instruction is FF00-FF00-FF00-FF00-FF00-FF00-FF00-FF00h. Another example, according to the PCIe Gen 4.0 specification, the format of the EIEOS instruction is FFFF-0000-FFFF-0000-FFFF-0000-FFFF-0000h. Also note that in actual application, as long as the preset instruction CMDpre has a preset and fixed format and is used to represent the state transition, the type of the preset instruction CMDpre does not need to be limited. For example, the data stream start instruction set SDS can also be used as the preset instruction CMDpre. The format of the SDS instruction set is 5555-5555-5555-5555-5555-5555-5555-55E1h. For the convenience of explanation, the following embodiments assume that the preset instruction CMDpre is the EIEOS instruction of PCIe Gen 3.0.

[0100] Please refer to Figure 7 , which is a waveform diagram of the timing adjustment circuit converting the input data stream inDAT with inconsistent timing into the timing-symmetrical data stream algnDAT with consistent timing. In this diagram, the horizontal axis represents time. The interval between each adjacent time point t1 to t14 on the horizontal axis is the double-word period Tdw. Additionally, it is assumed here that the width of each data channel Lane_1 to Lane_4 is 32 bits (equivalent to the width of a double word DW). In Figure 7 , an instruction with a length of 128 bits is split and transmitted over 4 double-word periods Tdw. That is, the instruction period Tord is equivalent to 4 double-word periods (4 * Tdw).

[0101] Figure 7 The signals from top to bottom are: the clock signal CLK, the push signal push(1) corresponding to the data channel Lane_1 and the input data stream inDAT(L1), the push signal push(2) corresponding to the data channel Lane_2 and the input data stream inDAT(L2), the push signal push(3) corresponding to the data channel Lane_3 and the input data stream inDAT(L3), the push signal push(4) corresponding to the data channel Lane_4 and the input data stream inDAT(L4), the momentary signal Spop, and the timing-symmetrical data streams algnDAT(L1) to algnDAT(L4) corresponding to the data channels Lane_1 to Lane_4 respectively.

[0102] After the instruction sensor DET1 senses the EIEOS instruction of the input data stream inDAT(L1) at time point t1, it issues an instruction sensing signal det(1) to the controller, and the controller converts the push signal push(1) from a low level to a high level at time point t1. The instruction period Tord of the input data stream inDAT(L1) from time point t1 to t5 is the EIEOS instruction. In each double-word period Tdw starting from time point t5, the content of the input data stream inDAT(L1) is sequentially the data double words DW11, DW12, DW13, DW14, DW15, DW16, DW17, DW18, DW19, DW110,....

[0103] After the instruction sensor DET2 senses the EIEOS instruction of the input data stream inDAT(L2) at time point t4, it sends an instruction sensing signal det(2) to the controller 450, and the controller converts the push signal push(2) from a low level to a high level at time point t4. The instruction period Tord of the input data stream inDAT(L2) during the time points t4 to t8 is the EIEOS instruction. During the multiple double-word periods Tdw starting from time point t8, the contents of the input data stream inDAT(L2) are sequentially data double-words DW21, DW22, DW23, DW24, DW25, DW26, DW27, ….

[0104] After the instruction sensor DET3 senses the EIEOS instruction of the input data stream inDAT(L3) at time point t3, it sends an instruction sensing signal det(3) to the controller, and the controller 450 converts the push signal push(3) from a low level to a high level at time point t3. The instruction period Tord of the input data stream inDAT(L3) during the time points t3 to t7 is the EIEOS instruction. During each double-word period Tdw starting from time point t7, the contents of the input data stream inDAT(L3) are sequentially data double-words DW31, DW32, DW33, DW34, DW35, DW36, DW37, DW38, ….

[0105] After the instruction sensor DET4 senses the EIEOS instruction of the input data stream inDAT(L4) at time point t2, it sends an instruction sensing signal det(4) to the controller 450, and the controller 450 converts the push signal push(4) from a low level to a high level at time point t2. The instruction period Tord of the input data stream inDAT(L4) during the time points t2 to t6 is the EIEOS instruction. During each double-word period Tdw starting from time point t6, the contents of the input data stream inDAT(L4) are sequentially data double-words DW41, DW42, DW43, DW44, DW45, DW46, DW47, DW48, DW49, ….

[0106] From Figure 7It can be seen that the instruction sensor (DET1) starts to receive the EIEOS instruction of the input data stream inDAT(L1) first (time points t1 to t5). Secondly, the instruction sensor (DET4) starts to receive the EIEOS instruction of the input data stream inDAT(L4) (time points t2 to t6). Then, the instruction sensor (DET3) starts to receive the EIEOS instruction of the input data stream inDAT(L3) (time points t3 to t7), and finally the instruction sensor (DET2) starts to receive the EIEOS instruction of the input data stream inDAT(L2) (time points t4 to t8). After the EIEOS instruction of the last data channel (data channel Lane_2) is received at time point t8, the controller switches the instantaneous signal Spop from the low level to the high level at time point t9.

[0107] With the level change of the instantaneous signal Spop at time point t9, starting from time point t9, the buffers BUF1 to BUF4 start to synchronously output the timing-symmetrical data streams algnDAT(L1) to algnDAT(L4). During time points t9 to t13, the contents of the timing-symmetrical data streams algnDAT(L1) to algnDAT(L4) are all four instruction double-word groups of the EIEOS instruction.

[0108] The content of the timing-symmetrical data stream algnDAT(L1) is the data double-word DW11 during time points t13 to t14, and the content is the data double-word DW12 during time points t14 to t15. The content of the timing-symmetrical data stream algnDAT(L2) is the data double-word DW21 during time points t13 to t14, and the content is the data double-word DW22 during time points t14 to t15. The content of the timing-symmetrical data stream algnDAT(L3) is the data double-word DW31 during time points t13 to t14, and the content is the data double-word DW32 during time points t14 to t15. The content of the timing-symmetrical data stream algnDAT(L4) is the data double-word DW41 during time points t13 to t14, and the content is the data double-word DW42 during time points t14 to t15.

[0109] The waveforms are described in the following order of time points t1 to t14 Figure 7 At time point t1, only the instruction sensing signal det(1) switches from the low level to the high level. The controller 450 can determine that at time point t1, only the data channel Lane_1 receives the EIEOS instruction. Based on this, the controller 450 can determine that the timing asymmetry period Tdiff between the data channels Lane_1 to Lane_4 is at least equal to one double-word period Tdw. That is, Tdiff≥Tdw.

[0110] Up to time point t2, since the levels of the command sensing signals det(1) and det(4) have been successively changed, but the levels of the command sensing signals det(2) and det(3) have not started to change yet, the controller 450 can determine that at time point t2, the data channels Lane_2 and Lane_3 have not started to receive the EIEOS command. Accordingly, the controller 450 can determine that the timing asymmetry period Tdiff between the data channels Lane_1 to Lane_4 is at least equal to two double-word periods Tdw * 2. That is, Tdiff ≥ 2 * Tdw.

[0111] Up to time point t3, since the levels of the command sensing signals det(1), det(4), and det(3) have been successively changed, but the level of the command sensing signal det(2) has not changed yet, the controller 450 can determine that at time point t3, the data channel Lane_2 has not received the EIEOS command. Accordingly, the controller 450 can determine that the timing asymmetry period Tdiff between the data channels Lane_1 to Lane_4 is at least equal to three double-word periods Tdw * 3. That is, Tdiff ≥ 3 * Tdw.

[0112] Up to time point t4, since the levels of the command sensing signals det(1), det(4), det(3), and det(2) have all been successively changed. Accordingly, the controller 450 can determine that the timing asymmetry period Tdiff between the data channels Lane_1 to Lane_4 is equal to three double-word periods Tdw. That is, Tdiff = 3 * Tdw.

[0113] As described above, the data synchronization circuit corresponding to the data channel Lane_1 starts to receive the EIEOS command at time point t1; the data synchronization circuit corresponding to the data channel Lane_4 starts to receive the EIEOS command at time point t2; the data synchronization circuit corresponding to the data channel Lane_3 starts to receive the EIEOS command at time point t3; and the data synchronization circuit corresponding to the data channel Lane_2 starts to receive the EIEOS command at time point t4. That is, the time difference between the data channels Lane_1 and Lane_2 receiving the EIEOS is (t4 - t1) = 3 double-word periods Tdw * 3. Since one double-word period Tdw is equivalent to 4 symbol periods (Tdw = 4 * Tdw). Therefore, in Figure 7 it, the timing asymmetry period Tdiff across the data channels Lane_1 to Lane_4 is equivalent to 12 symbol periods (Tdiff = Tdw * 3 = Tsym * 12).

[0114] Up to time point t5, the EIEOS instructions in the input data stream inDAT(L1) have been completely received. Therefore, during the time period from t5 to t6, buffer BUF1 receives the data double-word group DW11 in the input data stream inDAT(L1). On the other hand, buffer BUF2 continuously receives the second instruction double-word group in the input data stream inDAT(L2); buffer BUF3 continuously receives the third instruction double-word group in the input data stream inDAT(L3); and buffer BUF2 continuously receives the fourth instruction double-word group in the input data stream inDAT(L4).

[0115] Up to time point t6, the EIEOS instructions in the input data streams inDAT(L1) and inDAT(L4) have both been completely received. Therefore, during the time period from t6 to t7, buffer BUF1 will receive the data double-word group DW12 in the input data stream inDAT(L1), and buffer BUF4 will receive the data double-word group DW41 in the input data stream inDAT(L4). On the other hand, buffer BUF2 continuously receives the third instruction double-word group in the input data stream inDAT(L2); and buffer BUF3 continuously receives the fourth instruction double-word group in the input data stream inDAT(L3).

[0116] Up to time point t7, the EIEOS instructions in the input data streams inDAT(L1), inDAT(L3), and inDAT(L4) have all been completely received. Therefore, during the time period from t7 to t8, buffer BUF1 will receive the data double-word group DW13 in the input data stream inDAT(L1), buffer BUF3 will receive the data double-word group DW31 in the input data stream inDAT(L3), and buffer BUF4 will receive the data double-word group DW42 in the input data stream inDAT(L4). On the other hand, buffer BUF2 continuously receives the fourth instruction double-word group in the input data stream inDAT(L2).

[0117] Up to time point t8, the EIEOS instructions of data channels Lane_1, Lane_2, Lane_3, and Lane_4 have all been completely received. Therefore, during the time period from t8 to t9, buffer BUF1 receives the data double-word group DW14 in the input data stream inDAT(L1); buffer BUF2 receives the data double-word group DW21 in the input data stream inDAT(L2); buffer BUF3 receives the data double-word group DW32 in the input data stream inDAT(L3); and buffer BUF4 receives the data double-word group DW43 in the input data stream inDAT(L4).

[0118] Starting from time point t9, the instruction sensors DET1 to DET4 can suspend sensing the EIEOS instruction, and the buffers BUF1 to BUF4 start to synchronously output the timing-symmetrical data streams algnDAT(L1) to algnDAT(L4).

[0119] During the time period from t9 to t10, the data double words DW15 of the input data stream inDAT(L1), the data double words DW22 of the input data stream inDAT(L2), the data double words DW33 of the input data stream inDAT(L3), and the data double words DW44 of the input data stream inDAT(L4) will be respectively transmitted to the buffers BUF1, BUF2, BUF3, and BUF4 and temporarily stored therein. At the same time, the timing-symmetrical data streams algnDAT(L1) to algnDAT(L4) respectively output from the buffers BUF1, BUF2, BUF3, and BUF4 have the content of the first instruction double word of the EIEOS instruction in the input data streams inDAT(L1) to inDAT(L4).

[0120] During the time period from t10 to t11, the data double words DW16 of the input data stream inDAT(L1), the data double words DW23 of the input data stream inDAT(L2), the data double words DW34 of the input data stream inDAT(L3), and the data double words DW45 of the input data stream inDAT(L4) will be respectively transmitted to the buffers BUF1, BUF2, BUF3, and BUF4 and temporarily stored therein. At the same time, the timing-symmetrical data streams algnDAT(L1) to algnDAT(L4) respectively output from the buffers BUF1, BUF2, BUF3, and BUF4 have the content of the second instruction double word of the EIEOS instruction in the input data streams inDAT(L1) to inDAT(L4).

[0121] During the time period from t11 to t12, the data double words DW17 of the input data stream inDAT(L1), the data double words DW24 of the input data stream inDAT(L2), the data double words DW35 of the input data stream inDAT(L3), and the data double words DW46 of the input data stream inDAT(L4) will be respectively transmitted to the buffers BUF1, BUF2, BUF3, and BUF4 and temporarily stored therein. At the same time, the timing-symmetrical data streams algnDAT(L1) to algnDAT(L4) respectively output from the buffers BUF1, BUF2, BUF3, and BUF4 have the content of the third instruction double word of the EIEOS instruction in the input data streams inDAT(L1) to inDAT(L4).

[0122] During the time period from t12 to t13, the data double words DW18 of the input data stream inDAT(L1), the data double words DW25 of the input data stream inDAT(L2), the data double words DW36 of the input data stream inDAT(L3), and the data double words DW47 of the input data stream inDAT(L4) will be respectively transmitted to the buffers BUF1, BUF2, BUF3, and BUF4 and temporarily stored therein. At the same time, the timing-symmetrical data streams algnDAT(L1) to algnDAT(L4) respectively output from the buffers BUF1, BUF2, BUF3, and BUF4 have the content of the fourth instruction double word of the EIEOS instruction in the input data streams inDAT(L1) to inDAT(L4).

[0123] During the time period from t13 to t14, the data double words DW19 of the input data stream inDAT(L1), the data double words DW26 of the input data stream inDAT(L2), the data double words DW37 of the input data stream inDAT(L3), and the data double words DW48 of the input data stream inDAT(L4) will be respectively transmitted to the buffers BUF1, BUF2, BUF3, and BUF4 and temporarily stored therein. At the same time, the timing-symmetrical data stream algnDAT(L1) output from the buffer BUF1 is the data double word DW11 received and temporarily stored during the time period from t5 to t6; the timing-symmetrical data stream algnDAT(L2) output from the buffer BUF2 is the data double word DW21 received and temporarily stored during the time period from t8 to t9; the timing-symmetrical data stream algnDAT(L3) output from the buffer BUF3 is the data double word DW31 received and temporarily stored during the time period from t7 to t8; the timing-symmetrical data stream algnDAT(L4) output from the buffer BUF4 is the data double word DW41 received and temporarily stored during the time period from t6 to t7.

[0124] The component operations and signal changes after time point t14 can be inferred from the foregoing description and will not be elaborated here. Also, please note that the level changes of the momentary signal Spop and the clear signal Sflush here are only for example. In actual applications, the controller 450 can also notify the buffers BUF1 to BUF4 to output or discard the data content of the previously temporarily stored input data stream by pulling the momentary signal Spop and the clear signal Sflush from a high level to a low level.

[0125] At Figure 7In it, after buffer BUF1 receives the first instruction double-word group (FF00 - FF00h) of the input data stream inDAT(L1) at time point t1, it stores it until time point t9 when it starts to be transmitted. Therefore, the time period from t1 to t9 is equivalent to the buffering period Tbuff(1) during which the data of the input data stream inDAT(L1) needs to be temporarily stored in buffer BUF1. Similarly, the time period from t4 to t9 is equivalent to the buffering period Tbuff(2) during which the first instruction double-word group (FF00 - FF00h) of the input data stream inDAT(L2) needs to be temporarily stored in buffer BUF2; the time period from t3 to t9 is equivalent to the buffering period Tbuff(3) during which the first instruction double-word group (FF00 - FF00h) of the input data stream inDAT(L3) needs to be temporarily stored in buffer BUF3; the time period from t2 to t9 is equivalent to the buffering period Tbuff(4) during which the first instruction double-word group (FF00 - FF00h) of the input data stream inDAT(L4) needs to be temporarily stored in buffer BUF4.

[0126] Since buffer BUF1 is the first buffer to start receiving the EIEOS instruction, its capacity must be sufficient to store the first instruction double-word group of the EIEOS instruction of the input data stream inDAT(L1) up to time points t1 - t9 (equivalent to the length of 8 double-word groups, i.e., 8*Tdw). And during the time period from t2 to t9, buffer BUF1 still continuously receives the second instruction double-word group, the third instruction double-word, the fourth instruction double-word group, and data double-word groups DW11, DW12, DW13, DW14. The contents of these continuously received instruction double-word groups and data double-word groups also need to be stored. Accordingly, before time point t9, buffer BUF1 must store the contents of the 8 double-word groups received during the time period from t1 to t9 (equivalent to 8 double-word groups, i.e., 8*Tdw), including 4 instruction double-word groups and 4 data double-word groups DW11, DW12, DW13, DW14).

[0127] For another example, according to Figure 7As can be seen from the dashed-line box, the data double-word DW11 of the input data stream inDAT(L1) is transferred to the buffer BUF1 at time point t5 and output from the buffer BUF1 at time point t13 as the data double-word DW11 of the time-sequence symmetric data stream algnDAT(L1). Accordingly, the buffer BUF1 must store the data double-word DW11 during the period from time point t5 to t13 (8*Tdw). In addition, during the period from time point t5 to t13, the buffer BUF1 still successively receives the data double-words DW12, DW13, DW14, DW15, DW16, DW17, DW18 of the input data stream inDAT(L1) that also need to be temporarily stored. According to the foregoing description, it can be known that in the input data stream inDAT(L1), whether it is the EIEOS instruction or the data double-words DW11, DW12, DW13, DW14, DW15, DW16, DW17, DW18, they must be stored in the buffer BUF1 for 8 double-word periods (Tbuff(1) = 8*Tdw).

[0128] Since one double-word is equal to four bytes, the buffer BUF1 should provide 8*4 = 32 bytes of space accordingly. Moreover, in actual applications, the order in which the buffers BUF1 to BUF4 receive the input data streams inDAT(L1) to inDAT(L4) is not necessarily fixed. Therefore, the timing adjustment circuit should provide buffers BUF1 to BUF4 of equal size. That is, according to Figure 7 the waveform, the buffers BUF1 to BUF4 all provide at least 32 bytes of space.

[0129] In actual applications, for the case where the degree of timing asymmetry between the data channels Lane_1 to Lane_N is relatively large, the buffers BUF1 to BUN can also provide larger storage spaces. Consequently, the buffer period Tbuff(n) of the first data channel Lane_n that receives the input data stream while waiting for other data channels to receive the input data stream can be longer. Also note that in actual applications, the operation of the buffers BUF1 to BUN may be used in conjunction with other control signals, and these control signals can also be stored in the buffers BUF1 to BUN. In summary, regarding the length of the buffer period Tbuff(n) and the selection of the sizes of the buffers BUFF1 to BUFFN, they can be modified according to the selection of control signals, the design of the system, or the application, and there is no need to limit them.

[0130] Please refer to Figure 8, which is a flowchart of a controller of a timing adjustment circuit. First, in response to the input data streams inDAT(L1) to inDAT(LN) transmitted from the physical layer interface circuit (PHY) to the timing adjustment circuit, the instruction sensors DET1 to DETN each selectively generate instruction sensing signals det(1) to det(N) to the controller (step S801). Regarding the generation method of the instruction sensing signals det(1) to det(N), it has been described in Figure 6 and will not be repeated here.

[0131] Next, the controller 450 determines whether any one of the instruction sensors DET1 to DETN generates an instruction sensing signal det (step S803). If the determination result of step S803 is negative, the controller 450 generates a clear signal Sflush to BUF1 to BUFN, and after the buffers BUF1 to BUFN clear the stored data (step S807), step S801 is executed again.

[0132] If the determination result of step S803 is positive, the controller 450 will receive at least one instruction sensing signal det. For the sake of illustration, it is assumed here that a total of x sensors DET generate the instruction sensing signal det simultaneously. Among them, x is a positive integer, and x < N. For example, it is possible that the instruction sensors DET1 and DET3 generate the instruction sensing signals det(1) and det(3) simultaneously at the beginning.

[0133] The controller 450 issues push signals push (such as push(1), push(3)) corresponding to these instruction sensing signals det (such as the instruction sensing signals det(1), det(3)) to the buffers BUF (such as buffers BUF1, BUF3) in response to the received x instruction sensing signals det, notifying that the input data streams inDAT (such as input data streams inDAT(L1), inDAT(L3)) of the x data channels should be stored (step S809).

[0134] Next, the controller 450 determines whether the remaining (N - x) instruction sensing signals det are received within the instruction period Tord since the first time point when x instruction sensing signals det are received (step S811). If the judgment result in step S811 is negative, it means that the amount of data that needs to be temporarily stored to compensate for the degree of timing asymmetry exceeds the symbol quantity threshold Qth (for example, 32 symbols) (step S813). For such a situation, it means that the capacities of the buffers BUF1 to BUFN are still insufficient to compensate for the out-of-sync phenomenon caused by timing asymmetry. Therefore, the controller 450 generates a flush signal Sflush to the buffers BUF1 to BUFN to clear the data stored in the buffers BUF1 to BUFN. The symbol quantity threshold Qth is equivalent to the storage space provided by each of the buffers BUF1 to BUFN that can be individually used to temporarily store the input data streams inDAT(L1) to inDAT(LN).

[0135] In response to the (N - x) instruction sensing signals det received successively within the instruction period Tord, the controller 450 successively issues the corresponding (N - x) push signals push to the (N - x) buffers BUF, notifying these buffers to temporarily store the input data streams inDAT corresponding to the (N - x) data channels (step S815). After step S815 ends, it means that the data channels Lane_1 to Lane_N have all received the EIEOS instruction. Therefore, the controller 450 issues a pop signal Spop to the buffers BUF1 to BUFN, and the buffers BUF1 to BUFN start to synchronously transmit the timing-symmetrical data streams algnDAT(L1) to algnDAT(LN) (step S817).

[0136] In actual application, regarding the process of how the buffers BUF1 to BUFN perform subsequent actions in response to the instruction sensing signals det(1) to det(N) generated by the instruction sensors DET1 to DETN, different methods can be adopted. In Figure 5 after the instruction sensors DET1 to DETN transmit the instruction sensing signals det(1) to det(N) to the controller 450, the controller 450 then issues the push signals push(1) to push(4) to the buffers BUF1 to BUFN. Figures 9A - 9C are examples of several other possible implementation methods.

[0137] Please refer to Figures 9A - 9C , which is a schematic diagram illustrating the implementation method of the timing adjustment circuit. Since Figures 9A - 9C 's architecture is generally similar to Figure 5 , only the differences will be briefly described here. Regarding the generation of the pop signal Spop and the flush signal Sflush, and the operation modes of each component, they can be analogizedFigure 5 The description thereof will not be elaborated here. Similarly, since the operating modes of the data synchronization circuits 451, 453, and 455 corresponding to different data channels are similar, only the data synchronization circuit 451 will be taken as an example here.

[0138] In Figure 9A , it is assumed that the instruction sensor (DET1) 451a simultaneously transmits the instruction sensing signal det(1) to the controller 450 and the buffer (BUF) 451c. That is, the instruction sensing signal det(1) can be directly regarded as the push signal push(1).

[0139] In Figure 9B , it is assumed that the instruction sensor (DET1) 451a writes the instruction sensing signal det(1) into the register 452. In addition, the controller 450 determines whether / when to change the levels of the push signal push(1), the pop signal Spop, and the flush signal Sflush connected to the buffers BUF1 to BUFN by reading the content of the register 452.

[0140] In Figure 9C , it is assumed that the instruction sensor (DET1) 451a simultaneously transmits the instruction sensing signal det(1) to the controller 450, the buffer (BUF) 451c, and the register 454. That is, the instruction sensing signal det(1) can be directly regarded as the push signal push(1). In addition, the controller 450 determines whether / when to generate the pop signal Spop and the flush signal Sflush by reading the content of the register 454.

[0141] According to the concept of the present invention, the controller 450 issues the pop signal Spop and the flush signal Sflush in response to the instruction sensing signals det(1) to det(N) generated by the instruction sensors DET1 to DETN, and the buffers BUF1 to BUFN store the contents of the input data streams inDAT(L1) to inDAT(LN) in response to the instruction sensing signals det(1) to det(N). In actual application, regarding the connection relationship between the instruction sensors DET1 to DETN, the controller 450, and the buffers BUF1 to BUFN, and whether the timing adjustment circuit uses a register or other circuits, etc., it is not limited to Figure 5 , Figures 9A - 9C the examples.

[0142] According to the foregoing description, it can be known that the embodiment of the timing adjustment circuit described in the present disclosure can, in response to the situation of inconsistent timings of data channels, delay the earlier received input data stream inDAT for a longer period and then convert it into a timing-symmetrical data stream algnDAT. By setting the timing adjustment circuit, it can be ensured that the operation of the media access control circuit (MAC) is correct.

[0143] In summary, although the present invention has been disclosed above in embodiments, it is not intended to limit the present invention. Those of ordinary skill in the technical field to which the present invention pertains can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to that defined by the appended claims.

Claims

1. A timing adjustment circuit, comprising: N data synchronization circuits, which respectively convert N input data streams with inconsistent timings into N timing-symmetrical data streams with consistent timings, wherein a nth data synchronization circuit among the N data synchronization circuits comprises: A n-th instruction sensor that changes the level of an n-th instruction sensing signal when an n-th input data stream among the N input data streams satisfies a single-channel preset condition; and a nth buffer, which stores the nth input data stream in response to a change in the level of a nth push signal; and, a controller, electrically connected to the N data synchronization circuits, which receives the nth instruction sensing signal and changes the level of a momentary signal connected to the nth buffer when an all-channel preset condition is satisfied, wherein the nth buffer outputs the stored nth input data stream in response to the change in the level of the momentary signal as a nth timing-symmetrical data stream among the N timing-symmetrical data streams, where n and N are positive integers, and n is less than or equal to N.

2. The timing adjustment circuit according to claim 1, wherein N is a power of 2.

3. The timing adjustment circuit according to claim 1, wherein the capacity of the nth buffer is related to the length of the preset instruction.

4. The timing adjustment circuit according to claim 1, wherein the nth instruction sensor comprises: an instruction receiving circuit, which extracts an input instruction from the nth input data stream; an instruction register, which stores a preset instruction; and An instruction comparison circuit, electrically connected to the instruction receiving circuit and the instruction register, compares the preset instruction with the input instruction, wherein, when at least a part of the preset instruction conforms to at least a part of the input instruction, the instruction comparison circuit determines that the single-channel preset condition is established and changes the level of the nth instruction sensing signal.

5. The timing adjustment circuit according to claim 1, wherein the preset instruction is an electrical idle escape instruction set or a data stream start instruction set.

6. The timing adjustment circuit according to claim 1, wherein the controller changes the level of the nth push signal in response to the change in the level of the nth instruction sensing signal.

7. The timing adjustment circuit according to claim 1, wherein the nth push signal is the nth instruction sensing signal.

8. The timing adjustment circuit according to claim 1, wherein the all-channel preset condition means that the controller receives N instruction sensing signals from the N data synchronization circuits during an instruction period.

9. The timing adjustment circuit according to claim 1, wherein a first input byte in the nth input data stream is asynchronous with a first input byte of at least one of the remaining (N - 1) input data streams among the N input data streams.

10. The timing adjustment circuit according to claim 9, wherein first timing adjustment bytes in each of the N timing-symmetrical data streams are synchronous with each other.

11. The timing adjustment circuit according to claim 1, wherein the N data synchronization circuits are electrically connected between a physical layer interface circuit and a media access control circuit.

12. The timing adjustment circuit according to claim 11, wherein the N data synchronization circuits respectively receive the N input data streams from the physical layer interface circuit.

13. The timing adjustment circuit as claimed in claim 11, wherein the N data synchronization circuits transmit the N timing-symmetric data streams to the media access control circuit.

14. The timing adjustment circuit as claimed in claim 1, wherein when the all-channel preset condition is not satisfied, the controller issues a clear signal to the N data synchronization circuits, and the nth buffer discards the stored nth input data stream in response to the clear signal.

15. A method for eliminating timing asymmetry, applied to a timing adjustment circuit, the method for eliminating timing asymmetry comprising the following steps: Receiving N input data streams with inconsistent timings from a physical layer interface circuit; Storing the nth input data stream when the nth input data stream among the N input data streams satisfies a single-channel preset condition; Transmitting the stored N input data streams as N timing-symmetric data streams when an all-channel preset condition is satisfied, wherein the timings of the N timing-symmetric data streams are consistent, and the all-channel preset condition is related to the single-channel preset condition; And Transmitting the N timing-symmetric data streams to a media access control circuit, where n and N are positive integers, and n is less than or equal to N.

16. A receiving circuit, comprising: A physical layer interface circuit that generates N input data streams with inconsistent timings; A medium access control circuit receives N temporally symmetric data streams with consistent timing; And, A timing adjustment circuit electrically connected between the physical layer interface circuit and the media access control circuit, comprising: N data synchronization circuits that respectively convert the N input data streams into the N timing-symmetric data streams, wherein the nth data synchronization circuit among the N data synchronization circuits comprises: An nth instruction sensor that changes the level of an nth instruction sensing signal when the nth input data stream among the N input data streams satisfies a single-channel preset condition; And An nth buffer that stores the nth input data stream in response to the change in the level of the nth instruction sensing signal; And, A controller electrically connected to the N data synchronization circuits, which receives the nth instruction sensing signal and changes the level of a momentary signal connected to the nth buffer when an all-channel preset condition is satisfied, wherein the nth buffer outputs the stored nth input data stream as the nth timing-symmetric data stream among the N timing-symmetric data streams in response to the change in the level of the momentary signal, where n and N are positive integers, and n is less than or equal to N.

Images