Clock function testing method, device, equipment and storage medium

Abstract

The present application discloses a clock function test method, device, equipment and storage medium, which relates to the field of edge server technology. Applied to a preset test board, the method includes: determining whether a clock test signal sent by a processing chip for processing the clock in the edge server is obtained; if a clock test signal is obtained, the clock test signal is processed by a field programmable logic gate array and a phase-locked loop in the preset test board, and the clock information obtained after processing is sent to the mainboard of the edge server through a preset communication method, so that the edge server compares and judges the parsed clock information with the clock test signal to output the test result of the clock function of the edge server; if the clock test signal is not obtained, an alarm is issued through an indicator light pre-configured on the preset test board. Through the technical solution of the present application, the clock detection function of the edge server can be fully covered.

Description

Technical Field

[0001] The present invention relates to the technical field of edge servers, and in particular to a clock function testing method, device, equipment and storage medium. Background Art

[0002] With the advancement and development of technology, the amount of data generated in our daily lives has exploded. Various forms of artificial intelligence rely on the immense computing power of servers, making them crucial to our lives. With the growth of the Internet of Things, virtual reality, and 5G mobile networks, transferring massive amounts of data traffic directly back to data centers for processing will pose significant challenges to the network architectures of existing telecom operators and the computing, storage, and intelligent analytics services provided by internet vendors. At the same time, emerging business applications are constantly emerging, including smart transportation, unmanned retail, smart hospitals, smart homes, smart factories, smart grids, and autonomous driving. These emerging services place stringent demands on low latency, high bandwidth, multiple connections, and a highly stable and secure operating environment.

[0003] Edge computing refers to a new service model in which data or tasks are computed and executed at the edge of the network, close to the data source. This allows data to be stored and processed at the edge of the network, collaborating with cloud computing to provide intelligent services at the data source. Consequently, edge servers have more stringent requirements for network latency. The clock function of edge servers is a key function and a key indicator of edge server performance. However, production testing for clock functions is severely lacking, making it impossible to ensure that production line inspections fully cover edge server functions. This poses a risk of defective products entering the market, causing financial losses to customers and leading to customer complaints.

[0004] In summary, how to fully cover the functions of the edge server clock during production testing, eliminate the hidden dangers of defective products, and make up for the shortcomings of factory inspection and testing is a problem that needs to be solved. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a clock function testing method, device, equipment, and storage medium that can fully cover the clock functions of the edge server during production testing, eliminate the hidden dangers of defective products, and make up for the shortcomings of factory inspection and testing. The specific solution is as follows:

[0006] In a first aspect, the present application discloses a clock function test method, which is applied to a preset test board, comprising:

[0007] Determine whether a clock test signal sent by a processing chip for processing a clock in an edge server is obtained;

[0008] If the clock test signal sent by the processing chip for processing the clock in the edge server is obtained, the clock test signal is processed by the field programmable logic gate array and the phase-locked loop in the preset test board, and the clock information obtained after processing is sent to the main board of the edge server through a preset communication method, so that the edge server can parse the clock information and compare the parsed clock information with the clock test signal to output the test result of the clock function of the edge server;

[0009] If the clock test signal sent by the processing chip for processing the clock in the edge server is not obtained, an alarm is issued through the indicator light pre-configured on the preset test board.

[0010] Optionally, the determining whether a clock test signal sent by a processing chip for processing a clock in the edge server is obtained includes:

[0011] Determine whether a TOD signal and a 1PPS signal sent by a processing chip for processing a clock in an edge server are obtained; wherein the TOD signal and the 1PPS signal are obtained by the edge server through any one of a global positioning system, Ethernet, and a cascade machine cascaded with the edge server.

[0012] Optionally, the processing of the clock test signal by using a field programmable logic gate array and a phase-locked loop in the preset test board includes:

[0013] Receiving the TOD signal through a field programmable logic gate array in the preset test board and analyzing the TOD signal;

[0014] The 1PPS signal is received by a phase-locked loop in the preset test board, and a local clock is outputted by an oven-controlled crystal oscillator, so as to correct the phase difference caused by the time delay of the 1PPS signal according to the local clock.

[0015] Optionally, the sending of the processed clock information to the mainboard of the edge server through a preset communication method includes:

[0016] The processed clock information is sent to the mainboard of the edge server via a universal serial bus.

[0017] Optionally, the sending of the processed clock information to the mainboard of the edge server through a preset communication method includes:

[0018] Sending the processed clock information to the platform controller hub of the edge server through a preset communication method;

[0019] Alternatively, the processed clock information is sent to the system-on-chip of the edge server via a preset communication method.

[0020] Optionally, the clock function testing method further includes:

[0021] The field programmable logic gate array and the phase-locked loop communicate via an I2C bus;

[0022] The processing chip for processing the clock in the edge server and the mainboard of the edge server communicate with each other via a system management bus.

[0023] In a second aspect, the present application discloses a clock function testing method, which is applied to an edge server and includes:

[0024] A clock test signal is sent to a preset test board through a processing chip for processing a clock in the edge server, so that the preset test board determines whether the clock test signal is obtained; wherein, if the preset test board obtains the clock test signal, the clock test signal is processed by a field programmable logic gate array and a phase-locked loop in the preset test board, and the clock information obtained after the processing is sent to the main board of the edge server through a preset communication method; if the clock test signal is not obtained, an alarm is issued through an indicator light pre-configured on the preset test board;

[0025] receiving clock information obtained by processing the clock test signal sent by the preset test board through the preset communication method, and parsing the clock information;

[0026] The parsed clock information is compared with the clock test signal to output a test result of the clock function of the edge server.

[0027] In a third aspect, the present application discloses a clock function test device, which is applied to a preset test board, comprising:

[0028] A signal determination module is used to determine whether a clock test signal sent by a processing chip for processing a clock in an edge server has been obtained;

[0029] A first processing module is configured to, if a clock test signal sent by a processing chip for processing a clock in an edge server is obtained, process the clock test signal through a field programmable logic gate array and a phase-locked loop in the preset test board, and send the processed clock information to a mainboard of the edge server through a preset communication method, so that the edge server can parse the clock information, compare and determine the parsed clock information with the clock test signal, and output a test result of the clock function of the edge server;

[0030] The second processing module is configured to issue an alarm through an indicator light pre-configured on the preset test board if the clock test signal sent by the processing chip for processing the clock in the edge server is not obtained.

[0031] In a fourth aspect, the present application discloses an electronic device, comprising a processor and a memory; wherein the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the clock function testing method as described above.

[0032] In a fifth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein the computer program implements the clock function testing method as described above when executed by a processor.

[0033] The present application provides a clock function testing method, which is applied to a preset test board, and determines whether a clock test signal sent by a processing chip for processing the clock in an edge server is obtained; if the clock test signal sent by the processing chip for processing the clock in the edge server is obtained, the clock test signal is processed by a field programmable logic gate array and a phase-locked loop in the preset test board, and the clock information obtained after processing is sent to the main board of the edge server through a preset communication method, so that the edge server parses the clock information and compares and judges the parsed clock information with the clock test signal to output a test result of the clock function of the edge server; if the clock test signal sent by the processing chip for processing the clock in the edge server is not obtained, an alarm is issued through an indicator light pre-configured on the preset test board. It can be seen that the present invention proposes a new strategic approach, which tests and verifies the clock function of the edge server through a preset test board and the entire system, builds a test platform, and uses the field programmable logic gate array and phase-locked loop in the preset test board to obtain the clock test signal, and transmits the processed clock information to the source edge server for comparison through a preset communication method, so as to output the test result to check whether the clock function of the edge server is normal. It can be used in production testing to detect whether the clock function is normal and whether it meets the factory conditions, ensuring full coverage of the machine's factory inspection functions, making up for the defect that the functional inspection in production cannot be fully covered, and eliminating the hidden dangers of defective products; in addition, the preset test board can also support intuitive alarm information display.

[0034] In addition, the present application provides a clock function test device, equipment and storage medium, which correspond to the above-mentioned clock function test method and have the same effect as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0036] Figure 1 This is a flow chart of a clock function testing method disclosed in this application;

[0037] Figure 2 A circuit diagram of a clock function test hardware design disclosed in this application;

[0038] Figure 3 This is a flow chart of a clock function testing method disclosed in this application;

[0039] Figure 4 A schematic diagram of a clock function test process disclosed in this application;

[0040] Figure 5 This is a schematic structural diagram of a clock function test device disclosed in this application;

[0041] Figure 6 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0042] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0043] Edge computing, as a new service model, places even stricter network latency requirements on edge servers. However, edge servers are severely lacking in production testing for clock functionality, making it impossible to ensure that production line testing fully covers edge server functionality. This creates the risk of defective products entering the market, causing financial losses to customers and potentially leading to customer complaints.

[0044] To this end, the present application provides a clock function testing solution that can fully cover the functions of the clock of the inspection edge server during production testing, eliminate the hidden dangers of defective products, and make up for the shortcomings of factory inspection and testing.

[0045] The embodiment of the present invention discloses a clock function test method, see Figure 1 As shown, the method is applied to a preset test board, and includes:

[0046] Step S11: determining whether a clock test signal sent by a processing chip for processing a clock in an edge server is obtained.

[0047] In an embodiment of the present application, a preset test board is applied to build a test platform by using a preset test board in combination with an edge server. A 1U single-channel Otii edge server is taken as an example, hereinafter referred to as the edge server. A clock test signal emitted by a processing chip for processing a clock in the edge server is received by a preset test board. For example, a clock test signal emitted by a field programmable gate array (FPGA) in the edge server is received by a preset test board. It is understandable that the processing chip for processing the clock used by the edge server is not limited to FPGA, and other similar chips with a clock processing function can be used.

[0048] Furthermore, the clock test signal sent by the processing chip for processing the clock in the edge server includes a TOD signal (Time of Day, time information) and a 1PPS signal (1Pulse Per Second, second pulse). It should be noted that after the edge server is powered on, it obtains TOD and 1PPS information from the Global Positioning System (GPS), Ethernet or a cascaded machine, that is, the TOD signal and the 1PPS signal are obtained by the edge server through any one of the global positioning system, Ethernet, and the cascaded machine cascaded with the edge server. The TOD signal and the 1PPS signal are then output to the preset test board, and the preset test board is used to determine whether the TOD signal and the 1PPS signal sent by the FPGA in the edge server are obtained.

[0049] Step S12: If the clock test signal sent by the processing chip for processing the clock in the edge server is obtained, the clock test signal is processed by the field programmable logic gate array and the phase-locked loop in the preset test board, and the clock information obtained after processing is sent to the main board of the edge server through a preset communication method, so that the edge server can parse the clock information and compare the parsed clock information with the clock test signal to output the test result of the clock function of the edge server.

[0050] In an embodiment of the present application, a preset test board determines whether a TOD signal and a 1PPS signal sent by an edge server are received. After the preset test board obtains the TOD signal and the 1PPS signal, the TOD signal and the 1PPS signal are processed respectively by different modules in the preset test board, wherein the TOD signal is sent to the FPGA for processing, and the 1PPS is sent to the phase-locked loop (PLL) for processing. Specifically, the TOD signal is received by the field programmable logic gate array in the preset test board, and the TOD signal is parsed; the 1PPS signal is received by the phase-locked loop in the preset test board, and a local clock is output through a constant temperature crystal oscillator, so as to correct the phase difference caused by the time delay of the 1PPS signal according to the local clock.

[0051] It is understandable that since the edge server still has a certain delay in the link relative to the network, in the overall solution, the oven controlled crystal oscillator (OCXO) of the preset test board provides an accurate reference clock source for the PLL. Usually, the PLL outputs a 25M clock to provide a reference clock source for the FPGA. The phase comparator in the PLL is used to compare the 1PPS signal from the edge server with the local clock, thereby reducing the phase difference caused by the delay. In this way, the phase difference caused by the link delay is reduced by referring to the local clock OCXO, meeting the edge server's network delay requirements.

[0052] In the embodiment of the present application, the preset test board communicates with the edge server via a Universal Serial Bus (USB). The preset test board is pre-connected to the USB interface of the edge tester. After the preset test board processes the clock test signal, it transmits the clock information to the mainboard of the edge server via USB.

[0053] It should be pointed out that the field programmable logic gate array and the phase-locked loop in the preset test board communicate through the I2C bus (Inter-Integrated Circuit), that is, the FPGA in the preset test board obtains the PPS information in the PLL through I2C, and then the FPGA uniformly transmits the processed clock information to the mainboard of the edge server through USB.

[0054] In a specific embodiment, the processed clock information is sent to the platform controller hub (PCH) of the edge server through a preset communication method; in another specific embodiment, the processed clock information is sent to the system on chip (SOC) of the edge server through a preset communication method.

[0055] Furthermore, after receiving the clock information transmitted by the preset test board, the mainboard PCH or SOC of the edge server parses the clock information. During the production inspection test, the parsed clock information is compared with the clock test signal output by the edge server under the OS (Operating System, computer management control program) to output the test result of the clock function of the edge server to determine whether it passes.

[0056] Step S13: If the clock test signal sent by the processing chip for processing the clock in the edge server is not obtained, an alarm is issued through the indicator light pre-configured on the preset test board.

[0057] In an embodiment of the present application, if the preset test board fails to obtain the TOD signal and the 1PPS signal, the FPGA will light up a red indicator light to issue an alarm. It can be understood that an indicator light for test warning is pre-configured on the preset test board card. When there is no TOD signal and 1PPS signal input, the red indicator light will be lit to issue an alarm.

[0058] like Figure 2 The figure shows the overall hardware circuit design for clock function testing. The edge server's clock processing FPGA chip extracts the TOD and 1PPS signals and sends them to the pre-set test board. The TOD signal is processed by the FPGA in the pre-set test board, while the 1PPS signal is processed by the PLL in the pre-set test board. The OCXO in the pre-set test board provides a precise reference clock source for the PLL. When the PLL outputs a 25M clock, it provides a reference clock source for the FPGA. The FPGA and PLL in the pre-set test board communicate via I2C, allowing the FPGA to obtain the 1PPS information from the PLL. This information is then transmitted to the edge server's mainboard PCH or SoC via USB. The PCH or SoC in the edge server receives this information from the FPGA via USB and parses the clock information. During production testing, the edge server can obtain the clock information from the pre-set test board under the OS, compare it with its own TOD and 1PPS information, and then provide feedback. It should be noted that the processing chip for processing the clock in the edge server and the mainboard of the edge server communicate with each other via a system management bus (SMBus).

[0059] The present application provides a clock function testing method, which is applied to a preset test board, and determines whether a clock test signal sent by a processing chip for processing the clock in an edge server is obtained; if the clock test signal sent by the processing chip for processing the clock in the edge server is obtained, the clock test signal is processed by a field programmable logic gate array and a phase-locked loop in the preset test board, and the clock information obtained after processing is sent to the main board of the edge server through a preset communication method, so that the edge server parses the clock information and compares and judges the parsed clock information with the clock test signal to output a test result of the clock function of the edge server; if the clock test signal sent by the processing chip for processing the clock in the edge server is not obtained, an alarm is issued through an indicator light pre-configured on the preset test board. It can be seen that the present invention proposes a new strategic approach, which tests and verifies the clock function of the edge server through a preset test board and the entire system, builds a test platform, and uses the field programmable logic gate array and phase-locked loop in the preset test board to obtain the clock test signal, and transmits the processed clock information to the source edge server for comparison through a preset communication method, so as to output the test result to check whether the clock function of the edge server is normal. It can be used in production testing to detect whether the clock function is normal and whether it meets the factory conditions, ensuring full coverage of the machine's factory inspection functions, making up for the defect that the functional inspection in production cannot be fully covered, and eliminating the hidden dangers of defective products; in addition, the preset test board can also support intuitive alarm information display.

[0060] The present application discloses a method for testing clock function. Figure 3 As shown, applied to an edge server, the method includes:

[0061] Step S21: Send a clock test signal to a preset test board through the processing chip for processing the clock in the edge server, so that the preset test board determines whether the clock test signal is obtained; wherein, if the preset test board obtains the clock test signal, the clock test signal is processed by the field programmable logic gate array and the phase-locked loop in the preset test board, and the clock information obtained after processing is sent to the mainboard of the edge server through a preset communication method; if the clock test signal is not obtained, an alarm is issued through the indicator light pre-configured on the preset test board.

[0062] In an embodiment of the present application, it is applied to an edge server, and a clock test signal is sent to a preset test board through the edge server to determine whether the preset test board has obtained the clock test signal of the edge server. The clock test signal includes a TOD signal and a 1PPS signal. It is understandable that if the preset test board obtains the clock test signal, the clock test signal is processed separately using different processing modules in the preset test board: the TOD signal of the edge server is parsed, and then the 1PPS from the edge server is compared with the local clock using PLL to reduce the phase difference caused by the delay. Finally, the clock information obtained after processing is returned to the edge server. If the preset test board does not obtain the clock test signal, the preset test board can support intuitive alarm information display, and light up a red indicator light to alarm when there is no TOD and 1PPS input.

[0063] Step S22: receiving clock information obtained by processing the clock test signal and sent by the preset test board through the preset communication method, and analyzing the clock information.

[0064] In an embodiment of the present application, the PCH or SOC in the edge server receives clock information sent from the FPGA in the preset test board via USB. The clock information includes TOD and 1PPS. The clock information is parsed by the PCH or SOC to determine whether the clock function of the edge server is normal.

[0065] Step S23: Compare and judge the parsed clock information with the clock test signal to output a test result of the clock function of the edge server.

[0066] In an embodiment of the present application, after receiving the clock information transmitted by the preset test board, the mainboard PCH or SOC of the edge server parses the clock information. During the production inspection test, the parsed clock information is compared and judged with the clock test signal output by the edge server under the OS to output the test result of the clock function of the edge server to determine whether it passes.

[0067] like Figure 4The following is a logical flow diagram of the overall clock function testing method. The test platform is constructed using an FPGA. A pre-configured test board is connected to the machine's USB port. When the machine is powered on, the server obtains 1PPS and TOD information from GPS, Ethernet, or a cascaded machine, and outputs these information to the pre-configured test board. The pre-configured test board determines whether it has received the 1PPS and TOD signals sent by the edge server. If so, the PLL on the pre-configured test board corrects the 1PPS for phase difference, and the FPGA on the pre-configured test board analyzes the TOD. This information is then transmitted to the edge server's PCH or SOC via USB. Finally, the edge server's OS compares the acquired information with the output information to determine the result, and the process concludes. If the pre-configured test board does not receive the 1PPS and TOD signals from the edge server, the FPGA on the test board illuminates a pre-configured red warning light on the pre-configured test board, notifying the inspector to proceed. The process concludes.

[0068] In addition, the present invention is not limited to use in servers. The present invention is applicable to any similar scenarios and similar designs and can improve product quality.

[0069] The present application provides a clock function testing method, which is applied to an edge server, wherein a clock test signal is sent to a preset test board through a processing chip for processing a clock in the edge server, so that the preset test board determines whether the clock test signal is obtained; wherein, if the preset test board obtains the clock test signal, the clock test signal is processed by a field programmable logic gate array and a phase-locked loop in the preset test board, and the clock information obtained after the processing is sent to the main board of the edge server through a preset communication method; if the clock test signal is not obtained, an alarm is issued through an indicator light pre-configured on the preset test board; the clock information obtained after processing the clock test signal sent by the preset test board through the preset communication method is received, and the clock information is parsed; the parsed clock information is compared and judged with the clock test signal to output a test result of the clock function of the edge server. It can be seen that the present invention proposes a new strategic approach, which tests and verifies the clock function of the edge server through a preset test board and the entire system, builds a test platform, and uses the field programmable logic gate array and phase-locked loop in the preset test board to obtain the clock test signal, and transmits the processed clock information to the source edge server for comparison through a preset communication method, so as to output the test result to check whether the clock function of the edge server is normal. It can be used in production testing to detect whether the clock function is normal and whether it meets the factory conditions, ensuring full coverage of the machine's factory inspection functions, making up for the defect that the functional inspection in production cannot be fully covered, and eliminating the hidden dangers of defective products; in addition, the preset test board can also support intuitive alarm information display.

[0070] Correspondingly, the embodiment of the present application also discloses a clock function test device, which is applied to a preset test board, see Figure 5 As shown, the device includes:

[0071] The signal determination module 11 is used to determine whether a clock test signal sent by a processing chip for processing a clock in an edge server is obtained;

[0072] The first processing module 12 is configured to, if the clock test signal sent by the processing chip for processing the clock in the edge server is obtained, process the clock test signal through the field programmable logic gate array and the phase-locked loop in the preset test board, and send the processed clock information to the main board of the edge server through a preset communication method, so that the edge server can parse the clock information, compare and judge the parsed clock information with the clock test signal, and output a test result of the clock function of the edge server;

[0073] The second processing module 13 is configured to generate an alarm through an indicator light pre-configured on the preset test board if the clock test signal sent by the processing chip for processing the clock in the edge server is not obtained.

[0074] Among them, for more specific working processes of the above modules, please refer to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0075] It can be seen that the above-mentioned scheme of this embodiment is applied to the preset test board, and it is judged whether the clock test signal sent by the processing chip for processing the clock in the edge server is obtained; if the clock test signal sent by the processing chip for processing the clock in the edge server is obtained, the clock test signal is processed by the field programmable logic gate array and the phase-locked loop in the preset test board, and the clock information obtained after processing is sent to the mainboard of the edge server through a preset communication method, so that the edge server parses the clock information and compares and judges the parsed clock information with the clock test signal to output the test result of the clock function of the edge server; if the clock test signal sent by the processing chip for processing the clock in the edge server is not obtained, an alarm is issued through the indicator light pre-configured on the preset test board. It can be seen that the present invention proposes a new strategic approach, which tests and verifies the clock function of the edge server through a preset test board and the entire system, builds a test platform, and uses the field programmable logic gate array and phase-locked loop in the preset test board to obtain the clock test signal, and transmits the processed clock information to the source edge server for comparison through a preset communication method, so as to output the test result to check whether the clock function of the edge server is normal. It can be used in production testing to detect whether the clock function is normal and whether it meets the factory conditions, ensuring full coverage of the machine's factory inspection functions, making up for the defect that the functional inspection in production cannot be fully covered, and eliminating the hidden dangers of defective products; in addition, the preset test board can also support intuitive alarm information display.

[0076] Furthermore, the embodiment of the present application also discloses an electronic device, Figure 6 This is a structural diagram of an electronic device 20 according to an exemplary embodiment, and the content in the diagram cannot be considered as any limitation to the scope of use of the present application.

[0077] Figure 6This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps of the clock function test method disclosed in any of the aforementioned embodiments. Furthermore, the electronic device 20 in this embodiment may specifically be a server.

[0078] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device. The communication protocol it follows is any communication protocol that can be applied to the technical solution of this application and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world. Its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0079] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, a magnetic disk, or an optical disk. The resources stored thereon may include an operating system 221, a computer program 222, and data 223. The data 223 may include various data. The storage method can be temporary storage or permanent storage.

[0080] The operating system 221 is used to manage and control the hardware devices on the electronic device 20 and the computer program 222, and can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the clock function test method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program capable of performing other specific tasks.

[0081] Furthermore, the embodiments of the present application also disclose a computer-readable storage medium, where the computer-readable storage medium includes a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a magnetic disk, or an optical disk, or any other form of storage medium known in the technical field. When the computer program is executed by a processor, the aforementioned clock function test method is implemented. For the specific steps of the method, reference can be made to the corresponding content disclosed in the aforementioned embodiments, and no further description will be given here.

[0082] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0083] The steps of the clock function test or algorithm described in conjunction with the embodiments disclosed herein can be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0084] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0085] The above is a detailed introduction to the clock function test method, device, equipment and storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for general technical personnel in this field, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A clock function testing method, characterized in that: Applicable to pre-set test boards, including: Determine whether a clock test signal sent by a processing chip for processing a clock in an edge server is obtained; If the clock test signal sent by the processing chip for processing the clock in the edge server is obtained, the clock test signal is processed by the field programmable logic gate array and the phase-locked loop in the preset test board, and the clock information obtained after processing is sent to the main board of the edge server through a preset communication method, so that the edge server can parse the clock information and compare the parsed clock information with the clock test signal to output the test result of the clock function of the edge server; If the clock test signal sent by the processing chip for processing the clock in the edge server is not obtained, an alarm is issued through the indicator light pre-configured on the preset test board; The processing of the clock test signal by the field programmable logic gate array and the phase-locked loop in the preset test board includes: Receiving a TOD signal through a field programmable logic gate array in the preset test board and analyzing the TOD signal; The 1PPS signal is received by a phase-locked loop in the preset test board, and a local clock is outputted by an oven-controlled crystal oscillator, so as to correct the phase difference caused by the time delay of the 1PPS signal according to the local clock.

2. The clock function testing method according to claim 1, wherein: The determining whether a clock test signal sent by a processing chip for processing a clock in an edge server is obtained includes: Determine whether a TOD signal and a 1PPS signal sent by a processing chip for processing a clock in an edge server are obtained; wherein the TOD signal and the 1PPS signal are obtained by the edge server through any one of a global positioning system, Ethernet, and a cascade machine cascaded with the edge server.

3. The clock function testing method according to claim 1, wherein: The step of sending the processed clock information to the mainboard of the edge server through a preset communication method includes: The processed clock information is sent to the mainboard of the edge server via a universal serial bus.

4. The clock function testing method according to claim 1, wherein: The step of sending the processed clock information to the mainboard of the edge server through a preset communication method includes: Sending the processed clock information to the platform controller hub of the edge server through a preset communication method; Alternatively, the processed clock information is sent to the system-on-chip of the edge server via a preset communication method.

5. The clock function testing method according to any one of claims 1 to 4, characterized in that: Also includes: The field programmable logic gate array and the phase-locked loop communicate via an I2C bus; The processing chip for processing the clock in the edge server and the mainboard of the edge server communicate with each other via a system management bus.

6. A clock function testing method, characterized in that: Applicable to edge servers, including: A clock test signal is sent to a preset test board through a processing chip for processing the clock in the edge server, so that the preset test board determines whether the clock test signal is obtained; wherein, if the preset test board obtains the clock test signal, the clock test signal is processed by the field programmable logic gate array and the phase-locked loop in the preset test board, and the clock information obtained after processing is sent to the mainboard of the edge server through a preset communication method; if the clock test signal is not obtained, an alarm is issued through an indicator light pre-configured on the preset test board; the processing of the clock test signal by the field programmable logic gate array and the phase-locked loop in the preset test board includes: receiving a TOD signal through the field programmable logic gate array in the preset test board and parsing the TOD signal; receiving a 1PPS signal through the phase-locked loop in the preset test board, and outputting a local clock through an oven-controlled crystal oscillator, so as to correct the phase difference caused by the time delay of the 1PPS signal according to the local clock; receiving clock information obtained by processing the clock test signal sent by the preset test board through the preset communication method, and parsing the clock information; The parsed clock information is compared with the clock test signal to output a test result of the clock function of the edge server.

7. A clock function test device, characterized in that: Applicable to pre-set test boards, including: A signal determination module is used to determine whether a clock test signal sent by a processing chip for processing a clock in an edge server has been obtained; A first processing module is configured to, if a clock test signal sent by a processing chip for processing a clock in an edge server is obtained, process the clock test signal through a field programmable logic gate array and a phase-locked loop in the preset test board, and send the processed clock information to a mainboard of the edge server through a preset communication method, so that the edge server can parse the clock information, compare and determine the parsed clock information with the clock test signal, and output a test result of the clock function of the edge server; A second processing module is configured to issue an alarm through an indicator light pre-configured on the preset test board if the clock test signal sent by the processing chip for processing the clock in the edge server is not obtained; The first processing module is specifically configured to: Receiving a TOD signal through a field programmable logic gate array in the preset test board and analyzing the TOD signal; The 1PPS signal is received by a phase-locked loop in the preset test board, and a local clock is outputted by an oven-controlled crystal oscillator, so as to correct the phase difference caused by the time delay of the 1PPS signal according to the local clock.

8. An electronic device, characterized in that: The electronic device includes a processor and a memory; wherein the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the clock function testing method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that Used to store a computer program; wherein when the computer program is executed by a processor, the clock function testing method according to any one of claims 1 to 6 is implemented.

Images