A data path detection method, device, apparatus and storage medium

Abstract

The present disclosure provides a data path detection method, device, equipment and storage medium, which is applied to the detection process of the data path of a semiconductor integrated circuit. The data path detection method comprises: a detection device sending a cutting signal to a cutting unit; the cutting unit cutting the connection between a bit line sensing circuit and a bit line in the data path based on the received cutting signal; the detection device writing test data into the bit line sensing circuit; under a preset condition, the detection device reads target data of the bit line sensing circuit; and defects of the data path are detected according to the test data and the target data. By using the data path detection method in the present disclosure, even if there is a problem in the storage array of the semiconductor integrated circuit, the defects of the data path can still be quickly detected, the overall test time of the semiconductor integrated circuit is saved, and the detection efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and particularly relates to a data path detection method, device, equipment and storage medium. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a chip with a high-density repetitive memory array unit. With the increasing demand of application end, the memory array unit is continuously miniaturized, which brings great challenges to the manufacturing process. Therefore, if a problem occurs in the internal memory array, it is usually difficult to test the problem, and it is impossible to determine whether it is a memory array failure or a data path failure, which affects the overall research and development time of the product. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0004] The present disclosure provides a data path detection method, device, equipment and storage medium.

[0005] According to a first aspect of some embodiments of the present disclosure, a data path detection method is provided, the data path detection method comprising:

[0006] The detection device sends a cut-off signal to the cut-off unit;

[0007] The cut-off unit cuts off the connection between the bit line sensing circuit and the bit line in the data path based on the received cut-off signal;

[0008] The detection device writes test data into the bit line sensing circuit;

[0009] Under a preset condition, the detection device reads target data of the bit line sensing circuit;

[0010] According to the test data and the target data, the defect of the data path is detected.

[0011] According to some embodiments of the present disclosure, the cut-off unit comprises an N-type MOS tube or a P-type MOS tube.

[0012] According to some embodiments of the present disclosure, the cut-off unit comprises an N-type MOS tube, and the detection device sends a cut-off signal to the cut-off unit, comprising:

[0013] The detection device sends a low-level signal to the gate of the N-type MOS tube;

[0014] Alternatively,

[0015] The cutting unit comprises a P-type MOS tube, and the detection device sends a cutting signal to the cutting unit, comprising:

[0016] The detection device sends a high-level signal to the gate of the P-type MOS tube.

[0017] According to some embodiments of the present disclosure, the detection device writes test data into the bit line sensing circuit, comprising:

[0018] The detection device sends an activation instruction to turn on a word line in the storage array.

[0019] According to some embodiments of the present disclosure, the detection device writes test data into the bit line sensing circuit, further comprising:

[0020] The detection device sends a write instruction to write test data into the bit line sensing circuit through the write port of the data path.

[0021] According to some embodiments of the present disclosure, the detection device reads target data of the bit line sensing circuit under a preset condition, comprising:

[0022] The detection device sends a read command to read target data in the bit line sensing circuit.

[0023] According to some embodiments of the present disclosure, the detection device detects defects of the data path according to the test data and the target data, comprising:

[0024] If the test data is inconsistent with the target data, the detection device determines that the data path has defects.

[0025] According to some embodiments of the present disclosure, the defects include short-circuit defects or open-circuit defects.

[0026] The second aspect of the present disclosure provides a data path detection device applied to the detection process of a data path of a semiconductor integrated circuit, comprising:

[0027] A sending module is configured to send a cutting signal to a cutting unit, so that the cutting unit cuts the connection between a bit line sensing circuit and a bit line in the data path after receiving the cutting signal;

[0028] A writing module is configured to write test data into the bit line sensing circuit;

[0029] A reading module is configured to read target data of the bit line sensing circuit under a preset condition;

[0030] A judging module is configured to detect defects of the data path according to the test data and the target data.

[0031] According to some embodiments of the present disclosure, the cutting unit comprises an N-type MOS tube or a P-type MOS tube, and the sending module is configured to:

[0032] send a low-level signal to a gate of the N-type MOS tube; or

[0033] the sending module is configured to:

[0034] send a high-level signal to a gate of the P-type MOS tube.

[0035] According to some embodiments of the present disclosure, the sending module is further configured to:

[0036] send an activation instruction to turn on a word line in a storage array.

[0037] According to some embodiments of the present disclosure, the sending module is further configured to:

[0038] send a write instruction;

[0039] the write module is configured to:

[0040] write test data into the bit line sensing circuit through a write port of the data path.

[0041] According to some embodiments of the present disclosure, the sending module is configured to:

[0042] send a read command;

[0043] the read module is configured to:

[0044] read target data in the bit line sensing circuit.

[0045] According to some embodiments of the present disclosure, the judging module is configured to:

[0046] if the test data is inconsistent with the target data, judge that the data path has a defect.

[0047] According to some embodiments of the present disclosure, the data path comprises a data path in a dynamic random access memory.

[0048] A third aspect of the present disclosure provides a data path detection device, comprising:

[0049] a processor;

[0050] a memory for storing processor-executable instructions;

[0051] wherein the processor is configured to perform the data path detection method according to the first aspect.

[0052] According to a fourth aspect of the embodiments of the present disclosure, a non-transitory computer readable storage medium is provided, which, when instructions in the storage medium are executed by a processor of a terminal, enables a detection device to perform the data path detection method according to the first aspect.

[0053] The data path detection method, device, equipment and storage medium provided by the embodiments of the present disclosure solve the problem that the existing technology cannot test the defects of the data path when the storage array of the semiconductor integrated circuit fails. Using the data path detection method in the present disclosure, the defects of the data path can be quickly detected, the overall test time of the semiconductor integrated circuit is saved, and the detection efficiency is improved.

[0054] Other aspects can become apparent from the following detailed description when read in conjunction with the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0055] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure. In these drawings, like reference numerals are used to represent similar elements throughout. The accompanying drawings are of some embodiments of the present disclosure, but not all embodiments. Other drawings can be derived from these drawings by those skilled in the art without paying creative labor.

[0056] Figure 1 is a circuit diagram of a conventional bit line sensing circuit according to an example.

[0057] Figure 2 is a flow chart of a data input and read process according to an example embodiment.

[0058] Figure 3 is a flow chart of a data path detection method according to an example embodiment.

[0059] Figure 4 is a bit line sensing circuit circuit diagram according to an example embodiment, in which the cut-off unit is an N-type MOS tube.

[0060] Figure 5 is a bit line sensing circuit circuit diagram according to an example embodiment, in which the cut-off unit is a P-type MOS tube.

[0061] Figure 6 is a block diagram of a data path detection device according to an example embodiment.

[0062] Figure 7 is a block diagram of a data path detection device according to an example embodiment. DETAILED DESCRIPTION

[0063] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0064] Dynamic Random Access Memory (DRAM) is a chip with a high-density, repeatable memory array. As application demands increase, these memory array cells are continuously miniaturizing, posing significant challenges to manufacturing processes. For example... Figure 1 As shown, in traditional bit-line sensing circuits, the bit line and bit-line sensing circuit cannot be disconnected during data writing and reading. Data is written through an external data port and directly to the target storage array via a data path, and then read from the target storage array via the same data path. If a problem occurs in the internal storage array, it is usually difficult to test the source of the problem and determine whether it is a storage array failure or a data path failure, thus impacting the overall product development time.

[0065] To address the aforementioned issues, this disclosure provides a data path detection method. In this method, a disconnection unit can disconnect or connect the bit line sensing circuit and the bit line in the data path. When the data path is disconnected, i.e., when the connection between the bit line and the bit line sensing circuit is broken, target data can be written into the bit line sensing circuit. During detection, the target data in the bit line sensing circuit is read and compared with test data to determine whether a fault has occurred in the data path. Using the data path detection method of this disclosure, the problem can be quickly identified, improving detection efficiency without affecting the overall product development time.

[0066] Before explaining the technical content involved in this disclosure, a brief explanation of the data input and reading process will be given first, such as... Figure 2 The diagram illustrates the process of writing data from the data port DQ to Dbus and storing it on the bit lines, as well as reading data from the bit lines to Dbus and then reading it back through the data port DQ. This process involves a bit line sensing circuit, which includes a cut-off unit connected to a detection device. The detection device sends a cut-off signal to the cut-off unit to control it to disconnect the bit line sensing circuit from the bit lines in the data path. The cut-off unit can be any component with a circuit-breaking function; this embodiment does not impose any specific limitation.

[0067] The specific process of data input and reading is as follows: firstly, disconnect the connection between the bit line and the bit line sensing circuit. Write data from the data terminal DQ to Dbus, and enable the signal from Dbus to Bbus to write data from Dbus to the bidirectional drive circuit between Dbus and Bbus and to Bbus; then enable the signal from Bbus to Cbus to write data from Bbus to the bidirectional drive circuit between Bbus and Cbus and to Cbus; then enable the signal from Cbus low eight bits <0:7> to Cbus high eight bits <15:8> to write data to the bidirectional drive circuit between Cbus low eight bits <0:7> and Cbus high eight bits <15:8>; then enable the signal from Cbus to Abus to write data to the bidirectional drive circuit between Cbus and Abus and to Abus; then write data to the YIO write drive circuit according to the global data line YIO write enable signal and the YIOEQ signal, and write data to the local read-write conversion module according to the local data line LIO write drive signal, and finally write to the bit line sensing circuit according to the column selection signal Csl, to complete the writing of the target data.

[0068] When reading data, the connection between the bit line and the bit line sensing circuit has been disconnected. Therefore, the target data is read out from the bit line sensing circuit through the data path according to the connection signal Iso of the cutting unit, the local data line LIO read drive signal, the global data line YIO read drive signal, the Abus to Cbus enable signal, the Cbus high eight bits <15:8> to Cbus low eight bits <0:7> enable signal, the Cbus to Bbus enable signal, and the Bbus to Dbus enable signal in sequence. The reading of the target data is completed.

[0069] According to an example embodiment, as shown in Figure 3 The data path detection method provided in the embodiment includes the following steps:

[0070] S110, the detection device sends a cutting signal to the cutting unit.

[0071] S120, the cutting unit cuts the connection between the bit line sensing circuit and the bit line in the data path based on the received cutting signal.

[0072] S130, the detection device writes test data to the bit line sensing circuit.

[0073] S140, under a predetermined condition, the detection device reads the target data of the bit line sensing circuit.

[0074] S150, according to the test data and the target data, the defects of the data path are detected.

[0075] The detection method in the embodiment needs to use a detection device to detect, and in the detection process, the detection device is connected with the dynamic random access memory, writes signals into the dynamic random access memory or reads signals from the dynamic random access memory, so as to detect the dynamic random access memory.

[0076] In step S110, before detecting defects existing in the data path using the detection device, a cut-off signal needs to be sent to a cut-off unit first. The cut-off unit can be, for example, an NMSO tube (i.e. an N-type MOS tube) or a PMOS tube (i.e. a P-type MOS tube), etc., which can realize the on-off control of the circuit. When the detection device sends the cut-off signal, for example, a tmReadLio instruction can be sent, which can make the cut-off unit lose the connection function, so as to disconnect the circuit connected by the cut-off unit, so that the read operation and the write operation in the subsequent steps can only be operated in the bit line sensing circuit.

[0077] In step S120, referring to Figure 4 and Figure 5 , the cut-off unit 334 cuts off the connection between the bit line sensing circuit 333 and the bit line in the data path based on the received cut-off signal. For example, when the cut-off unit 334 is an NMOS tube, a low voltage can be sent to the gate voltage of the NMOS tube to cut off the connection between the bit line sensing circuit 333 and the bit line in the data path; for another example, when the cut-off unit 334 is a PMOS tube, a high voltage can be sent to raise the gate voltage of the PMOS tube to cut off the connection between the bit line sensing circuit 333 and the bit line in the data path. After the connection between the bit line sensing circuit and the bit line in the data path is disconnected, whether the data path has defects can be detected. The data path can be, for example, the path between Dbus and the bit line sensing circuit in Figure 2 . After the connection between the bit line and the bit line sensing circuit is disconnected, whether the data path has defects can be determined by reading the data in the data path and detecting, so as to realize the detection of the entire data path.

[0078] After the connection between the bit line sensing circuit 333 and the bit line in the data path is cut off, the detection device sends an activation instruction (Active cmd) to turn on a word line in the storage array.

[0079] In step S130, the detection device sends a write instruction (Write cmd). At this time, data can be written into the bit line sensing circuit 333 through the data path. As shown in Figure 2 , the path from the data path to the bit line sensing circuit 333 is completely turned on, and at this time, the data can be written into the bit line sensing circuit 333.

[0080] In step S140, after the bit line sensing circuit 333 is disconnected from the bit line, the data that has been written is saved in the bit line sensing circuit 333. In this step, the predetermined condition is that the bit line sensing circuit 333 is disconnected from the bit line, at which time the detection device sends a read command (Read cmd) to the bit line sensing circuit 333 to read the target data saved therein, to provide data support for the subsequent defect judgment process. In this step, the target data read is the data written into the bit line sensing circuit 333 via the data path, and by comparing the target data with the test data, it can be directly reflected whether the data path and the bit line sensing circuit 333 have problems.

[0081] In step S150, after the target data of the bit line sensing circuit 333 is read, it is compared with the test data to detect whether the target data and the test data are consistent, and then to judge whether the data path has defects. If it is detected that the target data and the test data are inconsistent, it means that the target data has errors in the writing or reading process via the data path, resulting in changes in the data, indicating that the data path or the bit line sensing circuit has defects. If the target data and the test data are consistent, it means that the target data has no errors in the writing and reading process via the data path, i.e. the data path and the bit line sensing circuit have no defects.

[0082] Among them, the defect of the data path can be a short circuit defect or an open circuit defect, which can be further detected and determined by the detection device.

[0083] According to an example embodiment, referring to FIG. 4, Figure 4 The cutting unit 334 in this embodiment includes an N-type MOS tube. The source of the N-type MOS tube is connected to the bit line sensing circuit, the drain is connected to the bit line, and the gate is connected to the cutting signal. When the cutting unit 334 receives the cutting signal, it sends a low level to the gate of the N-type MOS tube, causing the N-type MOS tube to be non-conductive, thereby cutting off the connection between the bit line sensing circuit 333 and the bit line in the data path. Since the local data line LIO is always connected to the bit line sensing circuit 333, the data is saved in the bit line sensing circuit 333. The detection device can read the target data in the bit line sensing circuit 333. Finally, the defects of the data path are judged according to the comparison result of the test data and the target data, i.e. whether the data path has errors.

[0084] According to an example embodiment, as Figure 5As shown, the cutoff unit 334 in this embodiment includes a P-type MOS transistor. The source of the P-type MOS transistor is connected to the bit line sensing circuit, the drain is connected to the bit line, and the gate is connected to the cutoff signal. When the cutoff unit 334 receives the cutoff signal, it sends a high-level signal to the gate of the P-type MOS transistor, causing the P-type MOS transistor to de-conduct, thereby cutting off the connection between the bit line sensing circuit 333 and the bit line in the data path. Since the local data line LIO is always connected to the bit line sensing circuit 333, the written data can be stored in the bit line sensing circuit 333. Under preset conditions, the detection device can read the target data in the bit line sensing circuit 333. Finally, it detects defects in the data path based on the test data and the target data, such as comparing whether the test data and the read target data are consistent to determine whether there is a defect in the data path.

[0085] Figure 6 A block diagram of a data path detection device is shown according to an exemplary embodiment. Figure 6 As shown, the device includes at least a sending module 301, a writing module 302, a reading module 303, and a judging module 304. The sending module 301 sends a cut-off signal to the cut-off unit, causing the cut-off unit to disconnect the bit line sensing circuit from the bit line in the data path upon receiving the cut-off signal. The writing module 302 writes test data into the bit line sensing circuit. The reading module 303 reads the target data from the bit line sensing circuit under preset conditions. The judging module 304 detects defects in the data path based on the test data and the target data.

[0086] When the cutoff unit is an N-type MOSFET, the transmitting module 301 sends a low-level signal to the N-type MOSFET. When the cutoff unit is a P-type MOSFET, it sends a high-level signal to the P-type MOSFET. The transmitting module 301 also sends an activation command to open a word line in the memory array. The writing module 302 writes the target data to the bit line sensing circuit. The reading module 303 receives a read command and reads the target data from the bit line sensing circuit. If the test data is inconsistent with the target data, the judgment module 304 determines whether there is a defect in the data path.

[0087] Figure 7 This is a block diagram illustrating a device for data path detection, namely a computer device 400, according to an exemplary embodiment. For example, the computer device 400 may be provided as a terminal device. (Refer to...) Figure 7The computer device 400 includes a processor 401, the number of which can be set to one or more as needed. The computer device 400 also includes a memory 402 for storing instructions, such as an application program, executable by the processor 401. The number of memories can be set to one or more as needed. The stored application program can be one or more. The processor 401 is configured to execute the instructions to perform the above-described data path detection method.

[0088] Those skilled in the art will appreciate that embodiments of the present disclosure can be provided as methods, apparatus (devices), or computer program products. Accordingly, the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure can take the form of a computer program product on one or more computer-usable storage media having computer-usable program code embodied in the medium. The computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, including but not limited to RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer, and the like. In addition, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and can include any information delivery media. The foregoing description of the exemplary embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto.

[0089] In an exemplary embodiment, a non-transitory computer readable storage medium, such as the memory 402 including instructions, is provided, which can be executed by the processor 401 of the apparatus 400 to complete the above-described method. For example, the non-transitory computer readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0090] A non-transitory computer readable storage medium, when the instructions in the storage medium are executed by the processor of the terminal, enables the detection device to perform the data path detection method in the above-described embodiments.

[0091] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks.

[0092] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks.

[0093] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks.

[0094] In this disclosure, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0095] While the preferred embodiments of the disclosure have been described, additional variations and modifications can be made to these embodiments by those skilled in the art once they have the benefit of the foregoing description. Therefore, the appended claims are intended to encompass within their scope all possible variations and modifications of the preferred embodiments.

[0096] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the spirit or scope of the disclosure. Thus, it is intended that the present disclosure cover the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.

Claims

1. A data path detection method applied to a detection process of a data path of a semiconductor integrated circuit, characterized by, The data path detection method comprises: The detection device sends a cut-off signal to a cut-off unit; The cut-off unit cuts off the connection between the bit line sensing circuit and the bit line in the data path based on the received cut-off signal; The detection device writes test data into the bit line sensing circuit through a write port and a write driving circuit of the data path; Under a preset condition, the detection device reads target data of the bit line sensing circuit through a read circuit, wherein the read circuit is connected with the write driving circuit; According to the test data and the target data, the detection device detects defects of the data path.

2. The detection method according to claim 1, characterized in that, The cut-off unit comprises an N-type MOS tube or a P-type MOS tube.

3. The detection method according to claim 2, characterized in that, The cut-off unit comprises an N-type MOS tube, and the detection device sends a cut-off signal to the cut-off unit, comprising: The detection device sends a low-level signal to the gate of the N-type MOS tube; or The cut-off unit comprises a P-type MOS tube, and the detection device sends a cut-off signal to the cut-off unit, comprising: The detection device sends a high-level signal to the gate of the P-type MOS tube. The detection device writes test data into the bit line sensing circuit through a write port and a write driving circuit of the data path, comprising:

4. The method of claim 1, wherein The detection device sends an activation instruction to turn on a word line in the storage array. The detection device writes test data into the bit line sensing circuit through a write port and a write driving circuit of the data path, further comprising:

5. The detection method according to claim 4, characterized in that, The detection device sends a write instruction to write test data into the bit line sensing circuit through a write port and a write driving circuit of the data path. The detection device reads target data of the bit line sensing circuit through a read circuit under a preset condition, comprising:

6. The method of claim 1, wherein, The detection device sends a read command to read target data in the bit line sensing circuit. The detection device detects defects of the data path according to the test data and the target data, comprising:

7. The detection method according to claim 1, characterized in that, If the test data is inconsistent with the target data, the detection device determines that the data path has defects. The defects comprise short-circuit defects or open-circuit defects.

8. The method of claim 1, wherein, The data path detection device comprises:

9. A data path detection device, applied to the data path detection process of semiconductor integrated circuits, characterized in that, A sending module configured to send a cut-off signal to a cut-off unit, so that the cut-off unit cuts off the connection between the bit line sensing circuit and the bit line in the data path after receiving the cut-off signal; A write module configured to write test data into the bit line sensing circuit through a write port and a write driving circuit of the data path; A read module configured to read target data of the bit line sensing circuit through a read circuit under a preset condition, wherein the read circuit is connected with the write driving circuit; A judgment module configured to detect defects of the data path according to the test data and the target data. The cut-off unit comprises an N-type MOS tube or a P-type MOS tube, and the sending module is configured to:

10. The data path detection apparatus of claim 9, wherein, send a low-level signal to the gate of the N-type MOS tube; or The sending module is configured to: send a high-level signal to the gate of the P-type MOS tube. The sending module is further configured to:

11. The data path detection apparatus of claim 9, wherein, ​ sending an activation instruction to turn on a word line in a memory array.

12. The data path detection apparatus of claim 11, wherein, The sending module is further configured to: sending a write instruction; The write module is configured to: write test data into the bit line sensing circuit through a write port of the data path.

13. The data path detection apparatus of claim 9, wherein, The sending module is configured to: sending a read instruction; The read module is configured to: read target data in the bit line sensing circuit.

14. The data path detection apparatus of claim 9, wherein, The judging module is configured to: if the test data is inconsistent with the target data, judging that the data path has a defect.

15. The data path detection apparatus of claim 9, wherein, The data path comprises a data path in a dynamic random access memory.

16. A data path detection device, characterized by The detection device comprises: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to perform the detection method according to any one of claims 1 to 8.

17. A non-transitory computer-readable storage medium, comprising: When the instructions in the storage medium are executed by the processor of the terminal, the detection device can perform the detection method according to any one of claims 1 to 8.

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