Electrostatic discharge protection device and method of manufacturing the same, semiconductor device

Abstract

The application relates to an electrostatic discharge protection device and a manufacturing method thereof and a semiconductor device, the electrostatic discharge protection device comprising: a substrate; an insulating layer arranged on the substrate; an active region layer arranged on the insulating layer and comprising a second conductive type well region, a source region and a drain region, the source region and the drain region being arranged in the second conductive type well region; a gate arranged on the second conductive type well region between the source region and the drain region; a dielectric layer arranged on the gate and the active region layer; and a first metal interconnection arranged on the dielectric layer; wherein a first contact hole is arranged between the first metal interconnection and the gate, a second contact hole is arranged between the first metal interconnection and the source region, and a third contact hole is arranged between the first metal interconnection and the substrate. The application adds a new path connected to the substrate to the source end, and an effective ESD current release path can be formed when the ESD protection structure works, heat accumulation in the silicon film is prevented, and the ESD protection capability is effectively improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to an electrostatic discharge protection device, a method for manufacturing the electrostatic discharge protection device, and a semiconductor device. Background Technology

[0002] SOI (Silicon on Insulator) refers to silicon-on-insulator technology. SOI is a fully dielectric isolation technology where devices such as MOSFETs are fabricated on a top silicon film, with an oxide layer acting as an isolation layer between the top silicon film and the substrate. This technology completely eliminates the latch-up effect of traditional bulk silicon processes, has low parasitic capacitance, and offers advantages such as high speed, low power consumption, high integration, and high reliability.

[0003] Since MOS devices are formed above buried oxide layers, and shallow trench isolation (STI) structures are used on the buried oxide layers, the MOS devices are completely isolated by the thick oxide layer. Moreover, silicon dioxide has extremely poor heat dissipation capabilities, far inferior to those of silicon. Therefore, heat can easily accumulate in the silicon film, and the SOI self-heating effect will become a new problem.

[0004] Electrostatic discharge (ESD) failure is one of the most common reliability problems faced by the electronics industry. Statistics show that up to 35% of integrated circuit failures are caused by ESD, resulting in billions of dollars in losses annually for the electronics industry. Therefore, protection devices are crucial for the stability and safe operation of integrated circuits, and the industry's requirements for ESD protection diodes are becoming increasingly stringent.

[0005] From the perspective of ESD protection, GGNMOS (gate-grounded N-channel metal-oxide-semiconductor field-effect transistor) devices formed on fully depleted SOI substrates as ESD protection devices cannot form an effective current release path, and heat is easily accumulated in the top silicon layer. This will cause irreversible damage to the protection device, and the MOS circuit will lose ESD protection. Summary of the Invention

[0006] Therefore, it is necessary to provide an electrostatic discharge protection device.

[0007] An electrostatic discharge protection device includes: a substrate having a first conductivity type; an insulating layer disposed on the substrate; an active region layer disposed on the insulating layer, including a well region, a source region, and a drain region of a second conductivity type, wherein the source region and the drain region are disposed in the well region of the second conductivity type, and the source region and the drain region have a first conductivity type; a gate disposed above the structure of the well region of the second conductivity type located between the source region and the drain region; a dielectric layer disposed on the gate and the active region layer; and a first metal interconnect disposed on the dielectric layer; wherein the first metal interconnect has a first contact hole between itself and the gate, and a second contact hole between itself and the source region, the first contact hole and the second contact hole being filled with conductive material to achieve electrical connection between the first metal interconnect and the gate, and electrical connection between the first metal interconnect and the source region; the electrostatic discharge protection device further includes a third contact hole extending downward from the bottom of the first metal interconnect to the substrate, the third contact hole being filled with conductive material to achieve electrical connection between the first metal interconnect and the substrate; the first conductivity type and the second conductivity type are opposite conductivity types.

[0008] In one embodiment, the electrostatic discharge protection device is a silicon-on-insulator device, the substrate is a silicon substrate, and the active region layer is a top silicon layer.

[0009] In one embodiment, the first conductivity type is N-type, the second conductivity type is P-type, the gate is used as the gate of the GGNMOS, the drain region is used as the drain of the GGNMOS, and the source region is used as the source of the GGNMOS.

[0010] In one embodiment, an isolation structure is further included, the bottom of which extends to the insulating layer. The isolation structure is disposed on the outside of the GGNMOS, and the third contact hole extends through the dielectric layer, the isolation structure, and the insulating layer in sequence to the substrate.

[0011] In one embodiment, the surface of the drain region includes a metal silicide region and a self-aligned silicide barrier region; the electrostatic discharge protection device further includes a drain electrode disposed on the dielectric layer, and the electrostatic discharge protection device also has a fourth contact hole extending from the bottom of the drain electrode to the metal silicide region, the fourth contact hole being filled with a conductive material to achieve electrical connection between the drain electrode and the metal silicide region, and the self-aligned silicide barrier region forming a ballast resistor.

[0012] It is also necessary to provide a semiconductor device including a device region and an ESD region, wherein the device region and the ESD region include: a substrate having a first conductivity type; an insulating layer disposed on the substrate; an active region layer disposed on the insulating layer; and a dielectric layer disposed on the active region layer; the ESD region further includes: a well region of a second conductivity type disposed in the active region layer; a source region having a first conductivity type disposed in the second conductivity type well region; a drain region having a first conductivity type disposed in the second conductivity type well region; and a gate disposed in the second conductivity type well region above the structure located between the source region and the drain region, wherein the dielectric layer covers the device region. On the gate; a first metal interconnect is disposed on the dielectric layer; wherein, a first contact hole is provided between the first metal interconnect and the gate, and a second contact hole is provided between the first metal interconnect and the source region, the first contact hole and the second contact hole are filled with conductive material to realize the electrical connection between the first metal interconnect and the gate, and the first metal interconnect and the source region, the semiconductor device further comprises a third contact hole extending downward from the bottom of the first metal interconnect to the substrate, the third contact hole is filled with conductive material to realize the electrical connection between the first metal interconnect and the substrate; the first conductivity type and the second conductivity type are opposite conductivity types.

[0013] In one embodiment, an isolation structure is further provided at the junction of the device region and the ESD region, the bottom of the isolation structure extends to the insulating layer, and the third contact hole extends through the dielectric layer, the isolation structure and the insulating layer in sequence to the substrate.

[0014] It is also necessary to provide a method for manufacturing electrostatic discharge protection devices.

[0015] A method for manufacturing an electrostatic discharge protection device includes: obtaining a substrate; the substrate comprising a substrate, an insulating layer, and an active region layer stacked sequentially, the substrate having a first conductivity type; forming a well region of a second conductivity type on the semiconductor layer; the first conductivity type and the second conductivity type being opposite conductivity types; forming a gate on the well region of the second conductivity type; forming a source region and a drain region in the well regions of the second conductivity type on both sides of the gate, the source region and the drain region having a first conductivity type; forming a dielectric layer on the gate and the active region layer; forming a first contact hole, a second contact hole, and a third contact hole, the first contact hole penetrating downward from the top of the dielectric layer to the gate, the second contact hole penetrating downward from the top of the dielectric layer to the source region, and the third contact hole penetrating downward from the top of the dielectric layer to the substrate; filling the first contact hole, the second contact hole, and the third contact hole with a conductive material; forming a first metal interconnect on the dielectric layer; the gate being electrically connected to the first metal interconnect through the first contact hole, the source region being electrically connected to the first metal interconnect through the second contact hole, and the substrate being electrically connected to the first metal interconnect through the third contact hole.

[0016] In one embodiment, before forming a second conductivity type well region in the semiconductor layer, the step of forming an isolation structure is further included, the bottom of the isolation structure extending to the insulating layer, and the second conductivity type well region being formed on one side of the isolation structure; the step of forming a third contact hole includes photolithography and etching to form a third contact hole that sequentially penetrates the dielectric layer, the isolation structure and the insulating layer and extends to the substrate.

[0017] In one embodiment, after the steps of forming the source region and the drain region, a step of forming a metal silicide region is further included; the step of forming the metal silicide region includes forming a self-aligned silicide barrier layer in a portion of the surface of the drain region, and then performing a metallization process to form a metal silicide region in the location on the surface of the drain region where the self-aligned silicide barrier layer is not formed; a ballast resistor is formed in the location on the surface of the drain region where the self-aligned silicide barrier layer is formed; the method of manufacturing the electrostatic discharge protection device further includes: forming a fourth contact hole extending downward from the top of the dielectric layer to the drain region; filling the fourth contact hole with a conductive material; forming a drain electrode on the dielectric layer, the drain electrode being electrically connected to the metal silicide region through the fourth contact hole.

[0018] The aforementioned electrostatic discharge protection device and its manufacturing method, as well as the semiconductor device, can form an effective ESD current release path when the ESD protection structure is working by adding a new path to the substrate at the source end, preventing excessive heat accumulation in the silicon film and effectively improving the ESD protection capability. Attached Figure Description

[0019] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0020] Figure 1 This is a schematic diagram of the structure of a semiconductor device in one embodiment;

[0021] Figure 2 yes Figure 1 The diagram shows the current discharge path of an electrostatic discharge protection device integrated into a semiconductor device.

[0022] Figures 3a-3h This is a cross-sectional schematic diagram of the device during the manufacturing process of an embodiment of an electrostatic discharge protection device;

[0023] Figure 4 This is a flowchart of a method for manufacturing an electrostatic discharge protection device in one embodiment. Detailed Implementation

[0024] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0026] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0027] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0029] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0030] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0031] Figure 1 This is a schematic diagram of the structure of a semiconductor device in one embodiment. Figure 2 yes Figure 1 The diagram shows a schematic of the current discharge path of an electrostatic discharge protection device integrated into a semiconductor device. Figure 1 As shown, the semiconductor device includes a device region and an ESD region, wherein the ESD region is used to form an electrostatic discharge protection device. Both the device region and the ESD region include a substrate 110, an insulating layer 120, an active region layer 130, and a dielectric layer 170. The ESD region also includes a second conductivity type well region 152, a source region 154, a drain region 156, a gate 160, and a first metal interconnect 182.

[0032] Substrate 110 has a first conductivity type. Insulating layer 120 is disposed on substrate 110. Active region layer 130 is disposed on insulating layer 120. Dielectric layer 170 is disposed on gate 160 and active region layer 130. First metal interconnect 182 is disposed on dielectric layer 170. Device region can be disposed of devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs). Active region and well region structures of the device can be disposed in active region layer 130 of device region. Second conductivity type well region 152 is disposed in active region layer 130 of ESD region. Source region 154 and drain region 156 have the first conductivity type and are disposed in second conductivity type well region 152. Gate 160 is disposed above the structure of second conductivity type well region 152 located between source region 154 and drain region 156. A first contact hole 171 is provided between the first metal interconnect 182 and the gate 160, and a second contact hole 173 is provided between the first metal interconnect 182 and the source region 154. The first contact hole 171 and the second contact hole 173 are filled with conductive material to achieve electrical connection between the first metal interconnect 182 and the gate 160, and between the first metal interconnect 182 and the source region 154. A third contact hole 175 is also provided between the first metal interconnect 182 and the substrate 110. The third contact hole 175 extends downward from the bottom of the first metal interconnect 182 to the substrate 110, and the third contact hole 175 is filled with conductive material to achieve electrical connection between the first metal interconnect 182 and the substrate 110.

[0033] exist Figure 1 and Figure 2 In the illustrated embodiment, the first conductivity type is N-type, the second conductivity type is P-type, the source region 154 and the drain region 156 are N+ regions, and the substrate 110 is an N+ substrate. The gate 160 is the gate of a GGNMOS, the drain region 156 is the drain of a GGNMOS, and the source region 154 is the source of a GGNMOS.

[0034] The aforementioned semiconductor device, by adding a new path connecting the source to the substrate, can form an effective ESD current release path when the ESD protection structure is in operation (see...). Figure 2 This design prevents excessive heat accumulation in the silicon film, effectively improving ESD protection capabilities and achieving high ESD protection capabilities of 4kV or even above 8kV, representing a qualitative leap in ESD protection. Furthermore, the bulk contact lead-out of the aforementioned devices with electrostatic discharge protection structures is unaffected by the thickness of the top silicon film in SOI, and they are compatible with both fully depleted SOI and partially depleted SOI processes, meeting design requirements at different process nodes. This strong compatibility makes them suitable for various process nodes and beneficial for developers.

[0035] In one embodiment of this application, a drain electrode 184 is further provided on the dielectric layer 170, and the drain electrode 184 is electrically connected to the drain region 156 through a fourth contact hole 177. Figure 1In the illustrated embodiment, the surface of the drain region 156 includes a metal silicide region 157 and a self-aligned silicide barrier region. In one embodiment of this application, the portion of the surface of the drain region 156 other than the metal silicide region 157 is a self-aligned silicide barrier region. The drain electrode achieves electrical connection with the metal silicide region 157 through the conductive material filled in the fourth contact hole 177, and the self-aligned silicide barrier region forms a ballast resistor. In the initial stage of ESD (i.e., when electrostatic discharge is conducted to the ESD protection structure), the ballast resistor can buffer the large current, allowing the current to be discharged evenly. The metal silicide region 157 can reduce the contact resistance of the contact hole.

[0036] In one embodiment of this application, the conductive materials filled in the first contact hole 171, the second contact hole 173, the third contact hole 175, and the fourth contact hole 177 may be the same or different, including but not limited to metallic materials; wherein, the metallic materials may include one or more of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W, and Al. In one embodiment of this application, tungsten plugs are formed in the first contact hole 171, the second contact hole 173, the third contact hole 175, and the fourth contact hole 177.

[0037] In one embodiment of this application, the semiconductor device provided is an SOI device. The substrate 110 is a silicon substrate, the active region layer 130 is a top silicon layer, and the insulating layer 120 is a buried oxide layer, the material of which can be silicon oxide, such as silicon dioxide. The dielectric layer 170 can be an interlayer dielectric (ILD) as a contact hole isolation medium. Specifically, the interlayer dielectric can be a silicon oxide layer, such as a doped or undoped silicon oxide material layer formed by thermal chemical vapor deposition (thermal CVD) or high-density plasma (HDP) manufacturing processes, specifically undoped silicon glass (USG), silicon phosphosilicate glass (PSG), or borosilicate phosphosilicate glass (BPSG). Alternatively, the interlayer dielectric can also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS), or boron-doped tetraethoxysilane (BTEOS).

[0038] exist Figure 1In the illustrated embodiment, an isolation structure 142 is further provided at the boundary between the ESD region and the device region, with the bottom of the isolation structure 142 extending to the insulating layer 120. A third contact hole 175 sequentially penetrates the dielectric layer 170, the isolation structure 142, and the insulating layer 120, extending to the substrate 110. Positioning the third contact hole 175 at the location of the isolation structure 142 allows the conductive material in the third contact hole 175 to be insulated from the ESD protection structure (e.g., GGNMOS), preventing the third contact hole 175 from negatively impacting the electrical performance of the ESD protection structure. In one embodiment of this application, the isolation structure 142 is an STI (shallow trench isolation structure).

[0039] In one embodiment of this application, the device region is provided with a MOSFET, and the device formed by the device region is a fully depleted silicon-on-insulator device. The source region and drain region of the MOSFET are located in the active region layer 130 of the device region, and the bottom of the source region and drain region of the MOSFET extends to the insulating layer 120.

[0040] This application provides an electrostatic discharge protection device having the ESD region structure of the semiconductor device described in the foregoing embodiments. In one embodiment of this application, the electrostatic discharge protection device includes:

[0041] The substrate has a first type of conductivity;

[0042] An insulating layer is disposed on the substrate;

[0043] An active region layer is disposed on the insulating layer and includes a second conductivity type well region, a source region, and a drain region. The source region and the drain region are disposed in the second conductivity type well region, and the source region and the drain region have a first conductivity type.

[0044] A gate is disposed above the structure in which the second conductivity type well region is located between the source region and the drain region;

[0045] A dielectric layer is disposed on the gate and active regions layers;

[0046] A first metal interconnect is disposed on the dielectric layer;

[0047] The first metal interconnect has a first contact hole between itself and the gate, and a second contact hole between itself and the source region. The first and second contact holes are filled with conductive material to achieve electrical connection between the first metal interconnect and the gate, and electrical connection between the first metal interconnect and the source region. The electrostatic discharge protection device also has a third contact hole extending downward from the bottom of the first metal interconnect to the substrate. The third contact hole is filled with conductive material to achieve electrical connection between the first metal interconnect and the substrate. The first conductivity type and the second conductivity type are opposite conductivity types.

[0048] In one embodiment of this application, the electrostatic discharge protection device is a silicon-on-insulator device, the substrate is a silicon substrate, and the active region layer is a top silicon layer.

[0049] In one embodiment of this application, the first conductivity type is N-type, the second conductivity type is P-type, the gate is used as the gate of the GGNMOS, the drain region is used as the drain of the GGNMOS, and the source region is used as the source of the GGNMOS.

[0050] In one embodiment of this application, the electrostatic discharge protection device further includes an isolation structure, the bottom of which extends to the insulating layer. The isolation structure is disposed on the outside of the GGNMOS, and the third contact hole extends through the dielectric layer, the isolation structure, and the insulating layer in sequence to the substrate.

[0051] In one embodiment of this application, the surface of the drain region includes a metal silicide region and a self-aligned silicide barrier region; the electrostatic discharge protection device further includes a drain electrode disposed on the dielectric layer, and the electrostatic discharge protection device is further provided with a fourth contact hole extending from the bottom of the drain electrode to the metal silicide region, the fourth contact hole being filled with a conductive material to achieve electrical connection between the drain electrode and the metal silicide region, and the self-aligned silicide barrier region forming a ballast resistor.

[0052] This application provides a method for manufacturing an electrostatic discharge protection device. Figure 4 This is a flowchart of a method for manufacturing an electrostatic discharge protection device in one embodiment, including the following steps:

[0053] S410, obtain the substrate.

[0054] See Figure 3a The substrate includes a substrate 110, an insulating layer 120, and an active region layer 130 stacked sequentially. The substrate 110 has a first conductivity type.

[0055] In one embodiment of this application, the electrostatic discharge protection device is an SOI device, the substrate 110 is a silicon substrate, the active region layer 130 is a top silicon layer, and the insulating layer 120 is a buried oxide layer, the material of which can be silicon oxide, such as silicon dioxide.

[0056] S420, a second conductivity type well region is formed in the semiconductor layer.

[0057] In one embodiment of this application, the step of forming the isolation structure 142 is included before step S420. See also Figure 3bFirst, a silicon dioxide layer 134 is formed on the active region layer 130, and then a silicon nitride layer 136 is formed on the silicon dioxide layer 134 to prepare for the formation of the isolation structure 142. The isolation structure 142 can be formed at the boundary between the device region and the ESD region. Specifically, trenches can be dug at the location of the isolation structure 142 by photolithography and etching, and then silicon dioxide is deposited in the trenches to form the isolation structure 142. See [link to documentation]. Figure 3c Since the silicon nitride layer 136 and silicon dioxide layer 134 need to be removed in subsequent steps, the surface of the isolation structure 142 can first be etched to be flush with the surface of the active region layer 130 by wet etching (the photoresist formed by photolithography before trenching of the isolation structure 142 can be retained until this wet etching step), and then the silicon nitride layer 136 and silicon dioxide layer 134 can be removed by etching, as follows. Figure 3d As shown. In one embodiment of this application, the isolation structure 142 is an STI.

[0058] In one embodiment of this application, after the isolation structure 142 is formed, ions of a second conductivity type can be implanted into the active region layer 130 of the ESD region through photolithography and ion implantation processes to form a second conductivity type well region 152. The second conductivity type well region 152 is formed on one side of the isolation structure 142.

[0059] S430, a gate is formed on the well region of the second conductivity type.

[0060] After removing the photoresist used for implantation in the second conductivity type well region 152, a layer of polysilicon is deposited on the wafer surface (on the semiconductor layer 112), and then the gate 160 is formed by photolithography and etching, as shown in the figure. Figure 3e .

[0061] S440 forms a source region and a drain region in a second conductivity type well region on both sides of the gate.

[0062] Self-aligned implantation of first-conductivity-type ions into the second-conductivity-type well region 152 forms a source region 154 and a drain region 156 on both sides of the gate 160, as shown in the reference. Figure 3f In this configuration, gate 160 is the gate of the GGNMOS, source region 154 is the source region of the GGNMOS, and drain region 156 is the drain region of the GGNMOS.

[0063] In one embodiment of this application, step S440 is followed by a step of forming a metal silicide region 157. Specifically, a self-aligned silicide barrier layer (SAB) is formed in a portion of the surface of the drain region 156, followed by metallization, and the metal silicide region 157 is formed at the locations on the surface of the drain region 156 where the SAB is not formed. A ballast resistor is formed at the locations on the surface of the drain region 156 where the self-aligned silicide barrier layer is formed.

[0064] S450, a dielectric layer is formed on the gate and active region layers.

[0065] In one embodiment of this application, an interlayer dielectric (ILD) is deposited on the wafer surface to form a dielectric layer 170 as a contact hole isolation medium, as described above. Figure 3g .

[0066] S460 forms the first contact hole, the second contact hole, and the third contact hole.

[0067] In one embodiment of this application, contact holes are formed by photolithography and etching. A first contact hole 171 extends downward from the top of the dielectric layer 170 to the gate 160, a second contact hole 173 extends downward from the top of the dielectric layer 170 to the source region 154, and a third contact hole 175 extends downward from the top of the dielectric layer 170 to the substrate 110.

[0068] In one embodiment of this application, photolithography is used to sequentially etch through the dielectric layer 170, the isolation structure 142, and the insulating layer 120 to form a third contact hole 175 extending to the substrate 110.

[0069] In one embodiment of this application, step S460 further includes forming a fourth contact hole 177 extending downward from the top of the dielectric layer 170 to the drain region 156.

[0070] In one embodiment of this application, photolithography and deep hole etching can be performed first to form the third contact hole 175, and then contact hole photolithography and etching can be performed again to form the first contact hole 171, the second contact hole 173 and the fourth contact hole 177.

[0071] S470, fill the first contact hole, the second contact hole and the third contact hole with conductive material.

[0072] In one embodiment of this application, tungsten metal is deposited into the first contact hole 171, the second contact hole 173, the third contact hole 175 and the fourth contact hole 177, and a smooth surface is formed by chemical mechanical polishing (CMP).

[0073] S480 forms the first metal interconnect on the dielectric layer.

[0074] In one embodiment of this application, a metal layer 180 is deposited on the dielectric layer 170 to form a metal contact, such as... Figure 3h As shown. Then, the metal layer 180 is photolithographically etched and etched to form the first metal interconnect 182 and the drain electrode 184, as shown. Figure 1 .

[0075] In one embodiment of this application, the first conductivity type is N-type, the second conductivity type is P-type, the source region 154 and the drain region 156 are N+ regions, and the substrate 110 is an N+ substrate.

[0076] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0077] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0078] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An electrostatic discharge protection device, characterized in that, include: The substrate has a first type of conductivity; An insulating layer is disposed on the substrate; An active region layer is disposed on the insulating layer, including a source region, a drain region, and a second conductivity type well region, wherein the source region and the drain region are disposed in the second conductivity type well region, and the source region and the drain region have a first conductivity type; A gate is disposed above the structure in which the second conductivity type well region is located between the source region and the drain region; A dielectric layer is disposed on the gate and active regions layers; A first metal interconnect is disposed on the dielectric layer; The first metal interconnect has a first contact hole between itself and the gate, and a second contact hole between itself and the source region. The first and second contact holes are filled with conductive material to achieve electrical connection between the first metal interconnect and the gate, and electrical connection between the first metal interconnect and the source region. The electrostatic discharge protection device also has a third contact hole extending downward from the bottom of the first metal interconnect to the substrate. The third contact hole is filled with conductive material to achieve electrical connection between the first metal interconnect and the substrate. The first conductivity type and the second conductivity type are opposite conductivity types.

2. The electrostatic discharge protection device according to claim 1, characterized in that, The electrostatic discharge protection device is a silicon-on-insulator device, the substrate is a silicon substrate, and the active region layer is a top silicon layer.

3. The electrostatic discharge protection device according to claim 1, characterized in that, The first conductivity type is N-type, the second conductivity type is P-type, the gate is used as the gate of the GGNMOS, the drain region is used as the drain of the GGNMOS, and the source region is used as the source of the GGNMOS.

4. The electrostatic discharge protection device according to claim 3, characterized in that, It also includes an isolation structure, the bottom of which extends to the insulating layer. The isolation structure is located on the outside of the GGNMOS. The third contact hole extends through the dielectric layer, the isolation structure, and the insulating layer in sequence to the substrate.

5. The electrostatic discharge protection device according to claim 1, characterized in that, The surface of the drain region includes a metal silicide region and a self-aligned silicide barrier region; the electrostatic discharge protection device also includes a drain electrode disposed on the dielectric layer, and the electrostatic discharge protection device is further provided with a fourth contact hole extending from the bottom of the drain electrode to the metal silicide region, the fourth contact hole being filled with conductive material to achieve electrical connection between the drain electrode and the metal silicide region, and the self-aligned silicide barrier region forming a ballast resistor.

6. A semiconductor device, characterized in that, It includes a device area and an ESD area, wherein the device area and the ESD area include: The substrate has a first type of conductivity; An insulating layer is disposed on the substrate; An active region layer is disposed on the insulating layer; A dielectric layer is disposed on the active region layer; The ESD zone also includes: A second conductivity type well region is disposed in the active region layer; The source region, having a first conductivity type, is located within the well region of the second conductivity type. The drain region, having a first conductivity type, is located within the well region of the second conductivity type. A gate is disposed above the structure of the second conductivity type well region located between the source region and the drain region, and the dielectric layer covers the gate. A first metal interconnect is disposed on the dielectric layer; The first metal interconnect has a first contact hole between itself and the gate, and a second contact hole between itself and the source region. The first and second contact holes are filled with conductive material to achieve electrical connection between the first metal interconnect and the gate, and electrical connection between the first metal interconnect and the source region. The semiconductor device also has a third contact hole extending downward from the bottom of the first metal interconnect to the substrate. The third contact hole is filled with conductive material to achieve electrical connection between the first metal interconnect and the substrate. The first conductivity type and the second conductivity type are opposite conductivity types.

7. The semiconductor device according to claim 6, characterized in that, It also includes an isolation structure located at the junction of the device region and the ESD region, the bottom of the isolation structure extending to the insulating layer, and the third contact hole extending through the dielectric layer, the isolation structure and the insulating layer in sequence to the substrate.

8. A method for manufacturing an electrostatic discharge protection device, comprising: Obtain the substrate; The substrate includes a substrate, an insulating layer and an active region layer stacked sequentially, and the substrate has a first conductivity type; A well region of a second conductivity type is formed in the semiconductor layer; the first conductivity type and the second conductivity type are opposite conductivity types; A gate is formed on the well region of the second conductivity type; A source region and a drain region are formed in the second conductivity type well region on both sides of the gate, the source region and the drain region having a first conductivity type; A dielectric layer is formed on the gate and active region layers; A first contact hole, a second contact hole, and a third contact hole are formed. The first contact hole extends downward from the top of the dielectric layer to the gate, the second contact hole extends downward from the top of the dielectric layer to the source region, and the third contact hole extends downward from the top of the dielectric layer to the substrate. The first contact hole, the second contact hole, and the third contact hole are filled with conductive material. A first metal interconnect is formed on the dielectric layer; the gate is electrically connected to the first metal interconnect through the first contact hole, the source region is electrically connected to the first metal interconnect through the second contact hole, and the substrate is electrically connected to the first metal interconnect through the third contact hole.

9. The method for manufacturing the electrostatic discharge protection device according to claim 8, characterized in that, Before forming the second conductivity type well region in the semiconductor layer, the step of forming an isolation structure is further included, the bottom of the isolation structure extending to the insulating layer, and the second conductivity type well region being formed on one side of the isolation structure; The steps for forming the third contact hole include photolithography and etching to form a third contact hole that sequentially penetrates the dielectric layer, the isolation structure and the insulating layer, thereby extending to the substrate.

10. The method for manufacturing the electrostatic discharge protection device according to claim 8, characterized in that, Following the steps of forming the source and drain regions, the method further includes the step of forming a metal silicide region; The step of forming the metal silicide region includes forming a self-aligned silicide barrier layer in a portion of the surface of the drain region, and then performing a metallization process to form a metal silicide region in the location on the surface of the drain region where the self-aligned silicide barrier layer is not formed. A ballast resistor is formed at the location on the surface of the drain region where a self-aligned silicide barrier layer is formed. The manufacturing method of the electrostatic discharge protection device further includes: A fourth contact hole is formed, extending downwards from the top of the dielectric layer to the drain region; Fill the fourth contact hole with conductive material; A drain electrode is formed on the dielectric layer, and the drain electrode is electrically connected to the metal silicide region through the fourth contact hole.

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