Device with electrostatic discharge protection structure and method of manufacturing the same

Abstract

The application relates to a device with an electrostatic discharge protection structure and a manufacturing method thereof, the device comprising a device region and an ESD region, the device region comprising: a substrate; an insulating layer arranged on the substrate; and a device active region layer arranged on the insulating layer; and the ESD region comprising: a semiconductor layer connected with the substrate; a well region arranged in the semiconductor layer; a first doped region arranged on the surface of the well region; a second doped region arranged on the surface of the well region; and a gate arranged above the well region between the first doped region and the second doped region; wherein the gate is a gate of a GGNMOS, the first doped region is a source of the GGNMOS, the second doped region is a drain of the GGNMOS, the semiconductor layer is an emitter of a triode, the second doped region is a collector of the triode, and the well region of the second conduction type is a base of the triode. The application can avoid thermal breakdown failure of the ESD protection structure caused by poor heat dissipation. The ESD region has two current discharge paths, the current discharge efficiency is improved, and the ESD protection capability is high.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a device with electro static discharge protection structure, and to a manufacturing method of a device with electro static discharge protection structure. BACKGROUND

[0002] SOI (Silicon on Insulator) refers to a silicon on insulator technology. The SOI process technology is a full dielectric isolation technology, and a metal oxide semiconductor field effect transistor (MOSFET) and the like is made on a top silicon film, and there is an oxide layer between the top silicon film and the substrate as an isolation. This technology completely eliminates the latch-up effect of the traditional bulk silicon process, has small parasitic capacitance, and has the advantages of high speed, low power consumption, high integration, and high reliability.

[0003] Since the MOS device is formed above the buried oxide layer, plus the shallow trench isolation (STI) structure on the buried oxide layer, the MOS device is completely isolated by the thick oxide layer, and the heat dissipation capacity of the silicon dioxide material is much poorer than that of the silicon material, so heat is easily accumulated in the silicon film, and the SOI self-heating effect will become a new problem.

[0004] Electro static discharge (ESD) failure is one of the most common problems in the reliability of the electronic industry, and according to statistics, as high as 35% of integrated circuit failures are caused by ESD, which causes losses of tens of billions of dollars to the electronic industry every year. Therefore, protecting the device is crucial to the stability and safe operation of the integrated circuit, and the industry has increasingly high requirements for ESD protection diodes.

[0005] From the perspective of ESD protection, thermal breakdown is the most important failure mode of ESD protection devices, and once heat is accumulated in the silicon film, the self-heating effect will cause irreversible damage to the protection device, and the MOS circuit will lose ESD protection. SUMMARY

[0006] Therefore, it is necessary to provide a device with an electro static discharge protection structure.

[0007] A device with electrostatic discharge protection structure, comprising a device region and an ESD region, the device region comprising: a substrate, having a first conductivity type; an insulating layer, disposed on the substrate; a device active region layer, disposed on the insulating layer; the ESD region comprising: a semiconductor layer, connected with the substrate, having a first conductivity type; a second conductivity type well region, disposed in the semiconductor layer; a first doped region, having a first conductivity type, disposed on the surface of the second conductivity type well region; a second doped region, having a first conductivity type, disposed on the surface of the second conductivity type well region; a gate, disposed above the structure of the second conductivity type well region between the first doped region and the second doped region; wherein the gate is the gate of a GGNMOS, the first doped region is the source region of the GGNMOS, the second doped region is the drain region of the GGNMOS, the semiconductor layer is the emitter of a triode, the second doped region is the collector of the triode, and the second conductivity type well region is the base of the triode; the first conductivity type and the second conductivity type are opposite conductivity types.

[0008] In one of the embodiments, the device is a silicon-on-insulator device, the substrate is a silicon substrate, the device active region layer is a top silicon layer, and the semiconductor layer is a silicon epitaxial layer.

[0009] In one of the embodiments, the insulating layer is a buried oxide layer.

[0010] In one of the embodiments, a third doped region is further included in the second conductivity type well region, the third doped region is located below the second doped region and directly contacts the second doped region, and the third doped region has a first conductivity type.

[0011] In one of the embodiments, an isolation structure is further included, the isolation structure is disposed at the junction of the device region and the ESD region, and the bottom of the isolation structure extends to the insulating layer.

[0012] In one of the embodiments, the isolation structure is a shallow trench isolation structure.

[0013] In one of the embodiments, the device region is provided with a metal-oxide-semiconductor field effect transistor.

[0014] In one of the embodiments, the device is a fully-depleted silicon-on-insulator device, the source region and the drain region of the metal-oxide-semiconductor field effect transistor are disposed in the device active region layer, and the bottom of the source region and the drain region extends to the insulating layer.

[0015] The surface of the second doped region comprises a metal silicide region and a self-aligned silicide block region, and the self-aligned silicide block region forms a ballast resistance.

[0016] In one of the embodiments, the first conductivity type is N type and the second conductivity type is P type.

[0017] It is also necessary to provide a manufacturing method of a device with electrostatic discharge protection structure.

[0018] A manufacturing method of a device with electrostatic discharge protection structure comprises: obtaining a substrate; the substrate comprises a substrate, an insulating layer and an active region layer which are sequentially stacked, and the substrate has a first conductivity type; removing the active region layer and the insulating layer of an ESD region to expose the substrate of the ESD region; filling a semiconductor material in the position of the removed active region layer and insulating layer to form a semiconductor layer, and the semiconductor layer has the first conductivity type; forming a second conductivity type well region on the semiconductor layer; forming a gate on the second conductivity type well region; forming a first doped region and a second doped region on the surface of the second conductivity type well region on both sides of the gate, and the first doped region and the second doped region have the first conductivity type; wherein the gate is the gate of a GGNMOS, the first doped region is the source region of the GGNMOS, the second doped region is the drain region of the GGNMOS, the substrate of the ESD region is the emitter of a transistor, the second doped region is the collector of the transistor, and the second conductivity type well region is the base of the transistor; and the first conductivity type and the second conductivity type are opposite conductivity types.

[0019] In one of the embodiments, the device is a silicon-on-insulator device, the substrate is a silicon substrate, and the active region layer is a top silicon layer; the method further comprises forming a silicon oxide layer on the surface of the top silicon layer before the step of removing the active region layer and the insulating layer of the ESD region; and the step of filling a semiconductor material in the position of the removed active region layer and insulating layer to form a semiconductor layer comprises forming the semiconductor layer by epitaxy.

[0020] In one of the embodiments, the step of removing the active region layer and the insulating layer of the ESD region comprises removing the silicon oxide layer, the active region layer and the insulating layer of the ESD region by photolithography and dry etching.

[0021] In one of the embodiments, the method further comprises the step of removing the silicon oxide layer and the excess semiconductor layer by chemical mechanical polishing so that the surface of the semiconductor layer is flush with the surface of the active region layer.

[0022] In one embodiment, after the steps of forming the first and second doped regions, the method further comprises a step of forming a metal silicide region; the step of forming the metal silicide region comprises forming a self-aligned silicide block on a portion of the surface of the second doped region, and then performing a metallization process to form the metal silicide region on the surface of the second doped region where no self-aligned silicide block is formed; the surface of the second doped region where the self-aligned silicide block is formed forms a ballast resistor.

[0023] The device with the ESD protection structure and the manufacturing method thereof, the front surface and the back surface of the ESD region are not separated by the insulating layer, and the poor heat dissipation caused by the thermal breakdown of the ESD protection structure is avoided. The ESD region has a lateral GGNMOS and a longitudinal transistor as the ESD protection device (and a lateral parasitic transistor is also formed), so that two current discharge paths are formed when the ESD protection device operates, the current discharge efficiency is improved, and the ESD protection capability is very high. BRIEF DESCRIPTION OF DRAWINGS

[0024] For better describing and illustrating the embodiments and / or examples of the inventions disclosed herein, one or more drawings can be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and / or examples, and the best mode presently understood of these inventions.

[0025] Figure 1 FIG. 1 is a schematic diagram of an equivalent transistor structure of an ESD protection structure of a device with an ESD protection structure in an embodiment;

[0026] Figure 2 FIG. 2 is a schematic diagram of a current discharge path of an ESD protection structure of a device with an ESD protection structure in an embodiment;

[0027] Figures 3a-3k FIG. 3 is a schematic diagram of a cross section of a device in a process of manufacturing a device with an ESD protection structure in an embodiment;

[0028] Figure 4 FIG. 4 is a flow chart of a manufacturing method of a device with an ESD protection structure in an embodiment;

[0029] Figure 5a FIG. 5 is a schematic diagram of a structure of an exemplary fully-depleted SOI MOS device, Figure 5b FIG. 6 is a schematic diagram of a structure of an exemplary "H" type gate structure. DETAILED DESCRIPTION

[0030] For the purposes of the US, the phrase "at least one of A and B" shall mean A or B or both A and B. For the purposes of the US, the phrase "at least one of A, B, and C" shall mean A or B or C or any combination thereof. For the purposes of the US, the phrase "at least one of A, B, and C, and possibly others" shall mean A or B or C or any combination thereof, and possibly others.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety for the teachings relevant to the sentence and / or paragraph in which the reference is presented.

[0032] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0033] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the application.

[0036] The semiconductor field terms used herein are the technical terms commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish the doping concentration, simply P+ type represents P-type with heavy doping concentration, P type represents P-type with medium doping concentration, P- type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N type represents N-type with medium doping concentration, N- type represents N-type with light doping concentration.

[0037] According to the relationship between the thickness of the device depletion region and the top silicon film, silicon-on-insulator metal-oxide-semiconductor field-effect transistor (SOI MOS) devices are divided into full-depleted SOI (Full Depleted SOI) and partially-depleted SOI (Partial Depleted SOI). Referring to Figure 5a For full-depleted SOI devices, because the silicon film is very thin, the source and drain N+ diffusions to the bottom buried oxide layer (BOX) isolate the P-well (PW), making it difficult to achieve effective body contact. In order to achieve the body contact lead-out of the full-depleted SOI device, one method is to use an "H" type body contact structure, as shown in Figure 5b The disadvantage of this structure is that it increases the MOS tube layout area, reduces the integration level of integrated circuits, and therefore has a higher cost.

[0038] Figure 1This is a schematic diagram of the equivalent transistor structure of the ESD protection structure of a device with an electrostatic discharge protection structure in one embodiment. Figure 2 This is a schematic diagram of the current discharge path of the ESD protection structure of a device with an electrostatic discharge protection structure in one embodiment. For example... Figure 1 As shown, the device with electrostatic discharge protection structure includes a device area and an ESD area; please refer to [link / reference needed]. Figure 2 The device region includes a substrate 110, an insulating layer 120, and a device active region layer 130. The substrate 110 has a first conductivity type, the insulating layer 120 is disposed on the substrate 110, and the device active region layer 130 is disposed on the insulating layer 120. Devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) can be disposed in the device region, and the active region and well region of the device can be disposed in the device active region layer 130. The ESD region is used to form an ESD protection structure, including a semiconductor layer 112, a second conductivity type well region 152, a gate 160, a first doped region 154, and a second doped region 156. The semiconductor layer 112 is connected to the substrate 110 and has a first conductivity type. The second conductivity type well region 152 is disposed in the semiconductor layer 112. The first doped region 154 and the second doped region 156 have the first conductivity type and are disposed on the surface of the second conductivity type well region 152. The gate 160 is disposed above the structure between the first doped region 154 and the second doped region 156 in the second conductivity type well region 152.

[0039] exist Figure 1 and Figure 2 In the illustrated embodiment, the first conductivity type is N-type, the second conductivity type is P-type, the first doped region 154 and the second doped region 156 are N+ regions, the substrate 110 is an N+ substrate, and the doping concentration of the semiconductor layer 112 can be lower than the doping concentration of the substrate 110. In other embodiments, the first conductivity type can also be P-type, and the second conductivity type can be N-type accordingly.

[0040] The ESD protection structure of the ESD region includes a GGNMOS (Gate-grounded N-channel metal-oxide-semiconductor field-effect transistor) and a vertically oriented transistor. The gate 160 is the gate of the GGNMOS, the first doped region 154 serves as the source region of the GGNMOS, and the second doped region 156 serves as the drain region of the GGNMOS. The substrate 110 of the ESD region serves as the emitter of the transistor (in other embodiments, the semiconductor layer 112 can also serve as the emitter), the second doped region 156 serves as the collector of the transistor, and the second conductivity type well region 152 serves as the base of the transistor. The ESD region also includes a lateral parasitic transistor, with the first doped region 154 serving as the emitter of the parasitic transistor, the second doped region 156 serving as the collector of the parasitic transistor, and the second conductivity type well region 152 serving as the base of the parasitic transistor.

[0041] When the ESD protection structure is working (i.e. has been deployed and can perform ESD protection), the substrate 110 of the second-conductivity-type well region 152 and the ESD region is grounded, and the second doped region 156 is connected to a positive voltage at a position of the integrated circuit that needs to be protected from ESD. In the initial stage of ESD (i.e. when static electricity is just being conducted to the ESD protection structure), the parasitic lateral transistor and the GGNMOS mainly work, and in the later stage of ESD (i.e. when the static electricity is being discharged), the vertical transistor mainly works.

[0042] The device with the ESD protection structure described above does not isolate the front surface and the back surface of the ESD region by the insulating layer 120, and heat can be conducted vertically through the substrate 110, so that the ESD protection structure is prevented from failing due to thermal breakdown caused by poor heat dissipation. The ESD region has the lateral GGNMOS and the vertical transistor as ESD protection devices (and also forms a lateral parasitic transistor), so that there are two current discharge paths when the ESD protection devices are working, which improves the current discharge efficiency and has a high ESD protection capability, can achieve a high ESD protection capability of 4kV or even 10kV or above, and realizes a qualitative leap in ESD protection capability. Moreover, the body contact lead of the device with the ESD protection structure described above is not affected by the thickness of the top silicon film of the SOI, and is applicable to full-depletion SOI and partial-depletion SOI processes, meets the design requirements under different process nodes, has strong compatibility, is suitable for various process nodes, and is conducive to the design of developers.

[0043] In an embodiment of the present application, the device with the ESD protection structure is an SOI device, the substrate 110 is a silicon substrate, the active region layer 130 of the device is a top silicon layer, the semiconductor layer 112 is a silicon epitaxial layer, and the insulating layer 120 is a buried oxide layer, which can be made of silicon oxide, such as silicon dioxide.

[0044] In an embodiment of the present application, the gate 160 is made of polysilicon material, and in other embodiments, metal, metal nitride, metal silicide or similar compounds can also be used as the material of the gate 160.

[0045] Referring to Figure 2 In this embodiment, the ESD protection structure further includes a third doped region 158 located in the second-conductivity-type well region 152. The third doped region 158 is located below the second doped region 156 and directly contacts the second doped region 156, and the third doped region 158 has the second conductivity type. The third doped region 158 is provided to form a Zener diode between the second doped region 156 and the third doped region 158, so as to increase the response speed of the transistor in the initial stage of operation and achieve fast response.

[0046] In one embodiment of the present application, the device region is provided with a MOSFET, and the device is a fully-depleted SOI device. The source region and the drain region of the MOSFET are provided in the device active region layer 130, and the bottom of the source region and the drain region of the MOSFET extends to the insulating layer 120.

[0047] In Figure 2 In the embodiment shown, the device with the electrostatic discharge protection structure further includes an isolation structure 142. The isolation structure 142 is provided at the boundary between the device region and the ESD region, and the bottom of the isolation structure 142 extends to the insulating layer 120, thereby insulating and separating the device active region layer 130 from the semiconductor layer 112. In one embodiment of the present application, the isolation structure 142 is an STI (shallow trench isolation structure).

[0048] In Figure 2 In the embodiment shown, the surface of the second doped region 156 includes a metal silicide region 157 and a self-aligned silicide block region. In one embodiment of the present application, the surface of the second doped region 156, except for the metal silicide region 157, is the self-aligned silicide block region. The self-aligned silicide block region forms a ballast resistance, which can buffer large current at the initial stage of ESD (i.e. when electrostatic is conducted to the ESD protection structure), and enable uniform discharge of current. The metal silicide region 157 can reduce the contact resistance of the contact hole (Contact).

[0049] Figure 4 is a flowchart of a method for manufacturing a device with an electrostatic discharge protection structure in one embodiment, including the following steps:

[0050] S410, obtaining a substrate.

[0051] Referring to Figure 3a , the substrate includes a substrate 110, an insulating layer 120 and a device active region layer 130, which are sequentially stacked. The substrate 110 has a first conductivity type.

[0052] In one embodiment of the present application, the device with the electrostatic discharge protection structure is an SOI device, the substrate 110 is a silicon substrate, the device active region layer 130 is a top silicon layer, and the insulating layer 120 is a buried oxide layer, which can be silicon oxide, such as silicon dioxide.

[0053] S420, removing the active region layer and the insulating layer of the ESD region.

[0054] In one embodiment of the present application, the device active region layer 130 and the insulating layer 120 of the ESD region are removed by photolithography and etching processes, so as to expose the substrate 110 of the ESD region.

[0055] In Figure 3bIn the embodiment shown, step S420 is preceded by a step of forming a silicon oxide layer 132 on the device active region layer 130. The silicon oxide layer 132 of the ESD region is removed in step S420. The silicon oxide layer 132 can be made of silicon dioxide.

[0056] Referring to Figure 3c , the photoresist 21 remaining after the photolithography covers the device region, step S420 is performed under the block of the photoresist 21 by dry etching, which must etch through the thick medium isolation of silicon dioxide, so that the ESD region after etching is all silicon material (substrate material).

[0057] S430, filling semiconductor material in the position of the removed active region layer and insulating layer to form a semiconductor layer.

[0058] In an embodiment of the present application, the semiconductor layer 112 of the first conductive type is formed by epitaxy, referring to Figure 3d . In an embodiment of the present application, the semiconductor layer 112 is N-type silicon. In an embodiment of the present application, the silicon oxide layer 132 can prevent the N-type silicon from growing in the device region during epitaxy. The photoresist 21 can be removed before the epitaxy of step S430.

[0059] In an embodiment of the present application, the excess semiconductor layer 112 can be ground flat after epitaxy. Specifically, the silicon oxide layer 132 and the excess semiconductor layer 112 can be removed by chemical mechanical polishing (CMP), so that the upper surface of the semiconductor layer 112 is flush with the upper surface of the device active region layer 130, as shown in Figure 3e .

[0060] S440, forming a well region of the second conductive type in the semiconductor layer.

[0061] In an embodiment of the present application, the CMP is followed by a step of forming an isolation structure 142. Referring to Figure 3f , a silicon dioxide layer 134 is first formed on the device active region layer 130 and the semiconductor layer 112, and then a silicon nitride layer 136 is formed on the silicon dioxide layer 134, to prepare for the formation of the isolation structure 142. Referring to Figure 3g , the isolation structure 142 is formed at the boundary between the device region and the ESD region. Specifically, a groove can be dug at the position of the isolation structure 142 by photolithography and etching, and then silicon dioxide is deposited in the groove to form the isolation structure 142. Since the silicon nitride layer 136 and the silicon dioxide layer 134 are to be removed in subsequent steps, the surface of the isolation structure 142 can be etched to be flush with the surface of the device active region layer 130 and the semiconductor layer 112 by wet etching (the photoresist formed by photolithography before the groove is dug can be retained to this step of wet etching), and then the silicon nitride layer 136 and the silicon dioxide layer 134 are etched and removed, as shown in Figure 3hThe isolation structure 142 is STI in one embodiment of the application.

[0062] In one embodiment of the application, after the isolation structure 142 is formed, ions of the second conductivity type are implanted into the semiconductor layer 112 by a photolithography and ion implantation process to form a second conductivity type well region 152.

[0063] S450, forming a gate on the second conductivity type well region.

[0064] After the photoresist used for implanting the second conductivity type well region 152 is removed, a layer of polysilicon is deposited on the wafer surface (on the semiconductor layer 112), and then a gate 160 is formed by photolithography and etching, as shown in Figure 3i .

[0065] S460, forming a first doped region and a second doped region on the surface of the second conductivity type well region on both sides of the gate.

[0066] The first conductivity type ions are self-aligned implanted into the second conductivity type well region 152 to form a first doped region 154 and a second doped region 156 on both sides of the gate 160, as shown in Figure 3j . The gate 160 is the gate of a GGNMOS (gate-grounded N-channel metal-oxide-semiconductor field-effect transistor), the first doped region 154 is the source region of the GGNMOS, and the second doped region 156 is the drain region of the GGNMOS. The substrate 110 of the ESD region is the emitter of a transistor, the second doped region 156 is the collector of the transistor, and the second conductivity type well region 152 is the base of the transistor. The ESD region also includes a lateral parasitic transistor, the first doped region 154 is the emitter of the parasitic transistor, the second doped region 156 is the collector of the parasitic transistor, and the second conductivity type well region 152 is the base of the parasitic transistor.

[0067] In the embodiment shown in Figure 3j , the method further includes a step of forming a third doped region 158 in the second conductivity type well region 152 by ion implantation. Specifically, the third doped region 158 is formed in direct contact with the second doped region 156 below the second doped region 156 by implanting ions of the second conductivity type. The third doped region 158 is provided to form a Zener diode between the second doped region 156 and the third doped region 158, thereby increasing the response speed of the first transistor and the second transistor at the initial stage of operation and achieving fast response.

[0068] In one embodiment of the present application, after step S460, a step of forming the metal silicide region 157 is further included. Specifically, a self-aligned silicide barrier (SAB) is formed on a part of the surface of the second doped region 156, and then a metallization process is performed to form the metal silicide region 157 on the surface of the second doped region 156 where no SAB is formed. See FIG. 6B. Figure 3k The position on the surface of the second doped region 156 where the SAB is formed forms the ballast resistance.

[0069] In one embodiment of the present application, the first conductivity type is N type, the second conductivity type is P type, the first doped region 154 and the second doped region 156 are N+ regions, and the substrate 110 is an N+ substrate. The doping concentration of the semiconductor layer 112 can be lower than the doping concentration of the substrate 110. In other embodiments, the first conductivity type can also be P type, and the second conductivity type is correspondingly N type.

[0070] It should be understood that, although the steps in the flowcharts of the present application are shown in sequence according to the arrows, the steps are not necessarily executed in sequence according to the arrows. Unless otherwise specified herein, the execution of the steps is not limited in sequence, and the steps can be executed in other sequences. Moreover, at least some of the steps in the flowcharts of the present application can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times. The execution sequence of the steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least some of the other steps or the steps or stages in other steps.

[0071] In the description of the present specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0072] The technical features of the above-described embodiments can be combined in any manner. In order to make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, however, as long as the combinations of the technical features do not contradict each other, they should be considered as within the scope of the present specification.

[0073] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A device having an electrostatic discharge protection structure, characterized by, The device comprises a device region and an ESD region, the device region comprising: a substrate having a first conductivity type; an insulating layer disposed on the substrate; a device active region layer disposed on the insulating layer; the ESD region comprising: a semiconductor layer connected to the substrate and having a first conductivity type; a second conductivity type well region disposed in the semiconductor layer; a first doped region having the first conductivity type and disposed on a surface of the second conductivity type well region; a second doped region having the first conductivity type and disposed on a surface of the second conductivity type well region; a gate disposed above a structure of the second conductivity type well region between the first doped region and the second doped region; wherein the gate is a gate of a GGNMOS, the first doped region is a source region of the GGNMOS, the second doped region is a drain region of the GGNMOS, the semiconductor layer is an emitter of a transistor, the second doped region is a collector of the transistor, the second conductivity type well region is a base of the transistor, a part of the substrate is in the device region and another part of the substrate is in the ESD region; the first conductivity type and the second conductivity type are opposite conductivity types.

2. The device with electrostatic discharge protection structure according to claim 1, wherein, The device is a silicon-on-insulator device, the substrate is a silicon substrate, the device active region layer is a top silicon layer, and the semiconductor layer is a silicon epitaxial layer.

3. The device with electrostatic discharge protection structure according to claim 1, wherein, Further comprising a third doped region in the second conductivity type well region, the third doped region is below the second doped region and directly contacts the second doped region, and the third doped region has the first conductivity type.

4. The device with electrostatic discharge protection structure according to claim 1, wherein, Further comprising an isolation structure disposed at a boundary between the device region and the ESD region, a bottom of the isolation structure extends to the insulating layer.

5. The device with electrostatic discharge protection structure according to claim 4, wherein, The isolation structure is a shallow trench isolation structure.

6. The device with electrostatic discharge protection structure of claim 1, wherein, A surface of the second doped region comprises a metal silicide region and a self-aligned silicide block region, and the self-aligned silicide block region forms a ballast resistance.

7. A method for manufacturing a device having an electrostatic discharge protection structure, comprising: obtaining a substrate; the substrate comprises a substrate, an insulating layer and an active region layer stacked in sequence, and the substrate has a first conductivity type; removing the active region layer and the insulating layer of the ESD region to expose the substrate of the ESD region; filling a semiconductor material in the position of the removed active region layer and insulating layer to form a semiconductor layer, the semiconductor layer having a first conductivity type; forming a second conductivity type well region in the semiconductor layer; forming a gate on the second conductivity type well region; forming a first doped region and a second doped region on the surface of the second conductivity type well region on both sides of the gate, the first doped region and the second doped region having a first conductivity type; wherein the gate is a gate of a GGNMOS, the first doped region is a source region of the GGNMOS, the second doped region is a drain region of the GGNMOS, the substrate of the ESD region is an emitter of a transistor, the second doped region is a collector of the transistor, and the second conductivity type well region is a base of the transistor; the first conductivity type and the second conductivity type are opposite conductivity types.

8. The method of manufacturing a device with an electrostatic discharge protection structure according to claim 7, wherein, The device is a silicon-on-insulator device, the substrate is a silicon substrate, and the active region layer is a top silicon layer; the step of removing the active region layer and the insulating layer of the ESD region further comprises a step of forming a silicon oxide layer on the surface of the top silicon layer; and the step of filling semiconductor material in the position of the removed active region layer and insulating layer to form a semiconductor layer comprises forming the semiconductor layer by epitaxy.

9. The method of manufacturing a device with an electrostatic discharge protection structure according to claim 7, wherein, The step of removing the active region layer and the insulating layer of the ESD region comprises removing the silicon oxide layer, the active region layer and the insulating layer of the ESD region by photolithography and dry etching.

10. The method of manufacturing a device with an electrostatic discharge protection structure according to claim 7, wherein, The step of forming the first doped region and the second doped region further comprises a step of forming a metal silicide region. The step of forming the metal silicide region comprises forming a self-aligned silicide barrier layer on part of the surface of the second doped region, and then performing a metallization process to form a metal silicide region on the surface of the second doped region where no self-aligned silicide barrier layer is formed; and the position of the surface of the second doped region where the self-aligned silicide barrier layer is formed forms a ballast resistor.

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