Semiconductor structure, preparation method thereof, chip transfer method and display panel
By forming spaced weakening structures and sacrificial layers on a substrate, the Micro LED chip transfer process is simplified, transfer efficiency and yield are improved, and damage risk and cost are reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHONGQING KONKA PHOTOELECTRIC TECH RES INST CO LTD
- Filing Date
- 2021-09-07
- Publication Date
- 2026-07-24
AI Technical Summary
Existing Micro LED chip transfer technologies suffer from complex process steps and low transfer efficiency and yield.
By forming multiple spaced weakening structures on a substrate and forming a sacrificial layer between the weakening structures, a chip is fabricated on the sacrificial layer after the chip is fabricated, the chip is picked up using a transfer device, and the transfer is completed after the sacrificial layer is removed.
It simplifies the chip transfer process, improves transfer efficiency and yield, reduces chip separation difficulty and damage risk, and allows for the reuse of weakened structures, thus reducing process costs.
Smart Images
Figure CN115775815B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display technology, and in particular to a semiconductor structure, its fabrication method, chip transfer method, and display panel. Background Technology
[0002] Micro LED display technology is an emerging display technology. Compared with conventional display technologies, displays based on Micro LED technology have the characteristics of fast response speed, self-illumination, high contrast, long lifespan, and high photoelectric efficiency.
[0003] In the Micro-LED industry, millions or even tens of millions of LED chips are transferred from the growth substrate to the temporary storage substrate, and then from the temporary storage substrate to the backplane. Commonly used chip transfer technologies include pick and place or laser transfer solutions. However, current chip transfer technologies generally suffer from problems such as complex process steps, low transfer efficiency, and low transfer yield.
[0004] Therefore, simplifying the process steps of chip transfer technology and improving transfer efficiency and yield are urgent problems to be solved. Summary of the Invention
[0005] In view of the shortcomings of the prior art, the purpose of this application is to provide a method for fabricating a semiconductor structure, a chip transfer method, and a display panel, which aims to reduce the process steps required to fabricate the weakened structure.
[0006] This application provides a method for fabricating a semiconductor structure according to some embodiments, including the following steps:
[0007] Provide substrate;
[0008] The substrate is patterned to form multiple spaced weakened structures, the height of which is less than the initial height of the substrate.
[0009] A sacrificial layer is formed between the weakened structures;
[0010] Multiple chips are formed, and the chips are in contact with the weakened structure.
[0011] The above-mentioned semiconductor structure fabrication method pre-patterns the substrate to form multiple spaced weakened structures. By forming weakened structures, the difficulty of separating the chip from the growth substrate can be reduced. In subsequent processes, no other transient substrate is required, thus enabling compatibility with the chip's own process, reducing process steps, and thereby improving chip transfer efficiency.
[0012] Furthermore, the semiconductor structure fabrication method described above forms a sacrificial layer between the weakened structures before forming the chip. This allows the chip to be formed on the upper surface of the sacrificial layer. This enables the chip to be removed before the chip is picked up by the transfer device in subsequent processes, thereby reducing the contact area between the chip and the weakened structure. This further reduces the difficulty of separating the chip from the substrate, improves the chip separation efficiency, and reduces the damage that may be caused to the chip during the separation process.
[0013] Furthermore, since the substrate with weakened structure prepared in the above semiconductor structure preparation method will not be destroyed after the chip is separated in subsequent processes, the multiple spaced weakened structures formed in this way can be reused, reducing process costs.
[0014] Optionally, the step of patterning the substrate to form a plurality of spaced-apart weakened structures includes the following steps:
[0015] Multiple mask patterns are formed on the surface of the substrate, and the multiple mask patterns are arranged in an array on the surface of the substrate, with a spacing between adjacent mask patterns;
[0016] The substrate is etched based on the mask pattern to form a plurality of spaced-apart weakened structures.
[0017] The above-mentioned semiconductor structure fabrication method involves pre-forming multiple mask patterns arranged in an array on the surface of a substrate, and then etching the substrate based on the mask patterns. This results in a uniform size of the weakened structure, avoiding the problem of reduced transfer yield caused by inconsistent size of the weakened structure and differences in adhesion.
[0018] Optionally, the mask pattern includes particles; forming multiple mask patterns on the surface of the substrate includes the following steps: forming multiple initial particles on the surface of the substrate, the multiple initial particles being arranged in an array and adjacent initial particles being in contact; etching each of the initial particles to obtain multiple mask patterns.
[0019] Compared to etching methods based on photoresist or other materials, the above-mentioned semiconductor structure fabrication method etches the substrate based on particles formed on the substrate surface, which can make the size of the prepared weakened structure more uniform and avoid the problem of reduced transfer yield due to inconsistent weakened structure size and different adhesion.
[0020] Optionally, the mask pattern includes a random pattern; forming multiple mask patterns on the surface of the substrate includes the following steps: forming multiple mask patterns on the surface of the substrate based on simulation calculations.
[0021] Optionally, the longitudinal cross-sectional shape of the weakening structure includes a triangle, a sphere, an arc, a curved surface, or a polygon.
[0022] Optionally, the spacing between adjacent weakening structures is smaller than the width of the chip; each chip is in contact with at least two of the weakening structures.
[0023] The above-mentioned semiconductor structure fabrication method, since each chip is in contact with at least two weakened structures, can effectively support each chip, thereby improving the reliability and stability of chip transfer.
[0024] Optionally, after forming multiple chips on the sacrificial layer, the method further includes: removing the sacrificial layer.
[0025] Based on the same inventive concept, this application also provides a semiconductor structure; the semiconductor structure is prepared by the semiconductor structure preparation method provided in any of the above embodiments, so the technical effects that can be achieved by the above semiconductor structure preparation methods can also be achieved by the semiconductor structure, which will not be described in detail here.
[0026] Based on the same inventive concept, this application also provides a chip transfer method, comprising the following steps:
[0027] The semiconductor structure is prepared using the semiconductor structure preparation method provided in the above embodiments;
[0028] The chip is picked up using a transfer device and transferred to the surface of the backplane.
[0029] The chip transfer method described above pre-patterns the substrate to form multiple spaced weakened structures. By forming weakened structures, the difficulty of separating the chip from the growth substrate can be reduced. No other transient substrate is required in subsequent processes, thus enabling compatibility with the chip's own process, reducing process steps, and improving chip transfer efficiency.
[0030] Furthermore, the chip transfer method described above forms a sacrificial layer between the weakened structures before forming the chip. This allows the chip to be formed on the upper surface of the sacrificial layer. This enables the chip to be removed before the transfer device picks up the chip in subsequent processes, thereby reducing the contact area between the chip and the weakened structures. This further reduces the difficulty of separating the chip from the substrate, improves the chip separation efficiency, and reduces the damage that may be caused to the chip during the separation process.
[0031] Furthermore, since the substrate with weakened structure prepared in the above chip transfer method will not be destroyed after the chip is separated in subsequent processes, the multiple spaced weakened structures formed in this way can be reused, reducing process costs.
[0032] Based on the same inventive concept, this application also provides a display panel, including: a back plate and a plurality of chips located on the surface of the back plate, wherein the plurality of chips are transferred to the surface of the back plate using the chip transfer method described in any of the above embodiments.
[0033] Since the chips of the aforementioned display panel are transferred to the backplane surface using the chip transfer method provided in any of the above embodiments, the display panel can also achieve the technical effects that the chip transfer method described in the above embodiments can achieve, and will not be described in detail here. Attached Figure Description
[0034] Figure 1 Flowcharts of methods for fabricating semiconductor structures provided in some embodiments of this application;
[0035] Figure 2 A flowchart of step S2 in a method for fabricating a semiconductor structure provided in some embodiments of this application;
[0036] Figure 3 A flowchart of step S21 in a method for fabricating a semiconductor structure provided in some embodiments of this application;
[0037] Figure 4 A flowchart of step S211 in a method for fabricating a semiconductor structure provided in some embodiments of this application;
[0038] Figure 5 A cross-sectional schematic diagram of the structure obtained in step S212 in a method for fabricating a semiconductor structure provided in some embodiments of this application;
[0039] Figure 6 A cross-sectional schematic diagram of the structure obtained in step S212 in a method for fabricating a semiconductor structure provided for some other possible embodiments of this application;
[0040] Figure 7 A cross-sectional schematic diagram of the structure obtained in step S3 in a method for fabricating a semiconductor structure provided in some embodiments of this application;
[0041] Figures 8 to 10 A cross-sectional schematic diagram of the structure obtained in step S4 in a method for fabricating a semiconductor structure provided in some embodiments of this application;
[0042] Figure 11 A cross-sectional schematic diagram of the structure obtained in step S5 in a method for fabricating a semiconductor structure provided in some embodiments of this application;
[0043] Figure 12 A flowchart of a chip transfer method provided for some embodiments of this application.
[0044] Explanation of reference numerals in the attached figures:
[0045] 1-Substrate; 2-Initial particle; 3-Particle; 4-Weakening structure; 5-Sacrificial layer; 6-Chip; 601-Epiaxial material layer; 602-Epiaxial layer; 603-First electrode; 604-Second electrode. Detailed Implementation
[0046] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.
[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.
[0048] In the Micro-LED industry, millions or even tens of millions of LED chips are transferred from the growth substrate to the temporary storage substrate, and then from the temporary storage substrate to the backplane. Commonly used chip transfer technologies include pick and place or laser transfer solutions.
[0049] As described in the background section, current chip transfer technologies generally suffer from complex process steps, low transfer efficiency, and low transfer yield. Therefore, simplifying the process steps of chip transfer technology and improving transfer efficiency and yield are urgent problems to be solved.
[0050] Therefore, this application aims to provide a solution that can solve the above-mentioned technical problems, the details of which will be described in the following embodiments.
[0051] Please see Figure 1 This application provides a method for fabricating a semiconductor structure according to some embodiments, including the following steps:
[0052] S1: Provides a substrate;
[0053] S2: Pattern the substrate to form multiple spaced weakened structures;
[0054] Specifically, the height of the weakened structure is less than the initial height of the substrate;
[0055] S3: A sacrificial layer is formed between weakened structures;
[0056] S4: Forming multiple chips; the chips come into contact with the weakened structure.
[0057] The above-mentioned semiconductor structure fabrication method pre-patterns the substrate to form multiple spaced weakened structures. By forming weakened structures, the difficulty of separating the chip from the growth substrate can be reduced. In subsequent processes, no other transient substrate is required, thus enabling compatibility with the chip's own process, reducing process steps, and thereby improving chip transfer efficiency.
[0058] Furthermore, the semiconductor structure fabrication method described above forms a sacrificial layer between the weakened structures before forming the chip. This allows the chip to be formed on the upper surface of the sacrificial layer. This enables the chip to be removed before the chip is picked up by the transfer device in subsequent processes, thereby reducing the contact area between the chip and the weakened structure. This further reduces the difficulty of separating the chip from the substrate, improves the chip separation efficiency, and reduces the damage that may be caused to the chip during the separation process.
[0059] Furthermore, since the substrate with weakened structure prepared in the above semiconductor structure preparation method will not be destroyed after the chip is separated in subsequent processes, the multiple spaced weakened structures formed in this way can be reused, reducing process costs.
[0060] The following is combined Figures 2 to 11 The preparation methods of semiconductor structures provided in some embodiments of this application will be described in more detail.
[0061] In step S1, as Figure 2 As shown, a substrate 1 is provided.
[0062] In some embodiments, the material of substrate 1 may include, but is not limited to, silicon (Si), silicon carbide (SiC), sapphire, gallium nitride (GaN), or gallium arsenide (GaAs), etc. That is, substrate 1 may include, but is not limited to, silicon substrate, silicon carbide substrate, sapphire substrate, gallium nitride substrate, or gallium arsenide substrate, etc. This application does not limit the specific material of substrate 1, as long as it is patterned to form a weakened structure with spaced arrangement.
[0063] In step S2, the substrate 1 is patterned to form multiple spaced weakened structures 4.
[0064] Specifically, in some embodiments, the height of the weakening structure 4 can be less than the initial height of the substrate 1; that is, when the substrate 1 is patterned, part of the substrate 1 can be retained so that no other transient substrate is needed in subsequent processes, reducing process steps; at the same time, after the chip 6 is separated in subsequent processes, it will not be destroyed. Therefore, the multiple weakening structures 4 arranged in this way can be reused, reducing process costs.
[0065] For step S2, as Figure 2 As shown, in some embodiments, step S2 may include the following steps:
[0066] S21: Multiple mask patterns are formed on the surface of substrate 1;
[0067] Specifically, multiple mask patterns can be arranged in an array on the surface of substrate 1, and there can be a gap between adjacent mask patterns;
[0068] S22: Based on the mask pattern, the substrate 1 is etched to form multiple spaced weakened structures 4.
[0069] The above-mentioned semiconductor structure fabrication method involves pre-forming multiple mask patterns arranged in an array on the surface of substrate 1, and then etching substrate 1 based on the mask patterns. This results in a uniform size for the weakened structure 4, avoiding the problem of reduced transfer yield caused by inconsistent size of the weakened structure 4 and differences in adhesion.
[0070] Optionally, the mask pattern may include, but is not limited to, particle 3 or other forms of mask patterns. This application does not limit the specific form of the mask pattern.
[0071] The following provides a more detailed description of some embodiments of this application where the mask pattern includes particles 3.
[0072] In the semiconductor structure fabrication method provided in the above embodiments, the mask pattern includes particles 3; please refer to... Figure 3 Based on the above implementation method, step S21 may include the following steps:
[0073] S211: Multiple initial particles 2 are formed on the surface of substrate 1, such as Figure 4 As shown;
[0074] Specifically, multiple initial particles 2 can be arranged in an array, and adjacent initial particles 2 can be in contact with each other;
[0075] S212: Etch each initial particle 2 to obtain multiple mask patterns, such as... Figure 5 As shown.
[0076] Specifically, step S212 may include etching each initial particle 2 to obtain multiple particles 3.
[0077] Optionally, adjacent initial particles 2 may or may not be in contact; this application does not impose any limitation on this.
[0078] The method for preparing the weakened structure 4 provided in the above embodiments, compared with the etching method based on photoresist or other materials, the method for preparing the semiconductor structure by etching the substrate 1 based on the particles 3 formed on the surface of the substrate 1, can make the size of the prepared weakened structure 4 more uniform, and avoid the problem of reduced transfer yield due to the difference in adhesion force caused by the inconsistent size of the weakened structure 4.
[0079] Optionally, the mask pattern may also include a random pattern. The following provides a more detailed description of other possible embodiments of this application where the mask pattern includes a random pattern.
[0080] In some embodiments, the mask pattern may include a random pattern; based on the above embodiments, step S21 may include the following steps: forming multiple mask patterns on the surface of substrate 1 based on simulation calculations.
[0081] Specifically, step S212 may include, but is not limited to, forming a plurality of random patterns on the surface of substrate 1 based on Monte Carlo simulation calculations.
[0082] For step S22, optionally, but not limited to photolithography etching process, the substrate 1 can be etched based on the mask pattern to form multiple spaced weakened structures 4; this application does not limit the specific method of patterning the structure to be etched.
[0083] In some embodiments, step S22 may include dry etching of the substrate 1 based on mask patterning to form a plurality of spaced weakened structures 4.
[0084] Dry etching has a high etching rate and causes minimal lateral erosion at the edges. The semiconductor structure fabrication method provided in the above embodiments uses dry etching to etch the substrate 1, which is not only easy to implement but also results in a well-defined weakened structure 4.
[0085] Optionally, the longitudinal cross-sectional shape of the weakening structure 4 may be any shape including but not limited to triangle, sphere, arc, curved surface or polygon. This application does not limit the longitudinal cross-sectional shape of the weakening structure 4.
[0086] In some implementations, the longitudinal cross-sectional shape of the weakening structure 4 may include a triangle.
[0087] The semiconductor structure fabrication method provided in the above embodiments forms a weakened structure 4 with a triangular longitudinal section, which results in a weakened structure 4 with good stability, which can stably support the chip 6 and improve the stability of the chip 6 transfer process.
[0088] For step S2, please refer to Figure 6 In some embodiments, after etching each initial particle 2 to obtain multiple mask patterns, a step of removing the mask patterns is included. The mask patterns can be removed using, but is not limited to, etching processes.
[0089] In step S3, as Figure 7 As shown, a sacrificial layer 5 is formed between the weakened structures 4.
[0090] Optionally, the sacrificial layer 5 may be a stacked structure consisting of any one or more layers of nitride semiconductor material, silicon dioxide (SiO2) layer or aluminum oxide (Al2O3) layer; this application does not limit the specific structure and material of the sacrificial layer 5.
[0091] In some embodiments, the sacrificial layer 5 includes a silicon nitride (SiN) layer.
[0092] Optionally, but not limited to physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes can be used to form a sacrificial layer 5 between the weakened structure 4.
[0093] The semiconductor structure fabrication method provided in the above embodiments has excellent adhesion because the sacrificial layer 5 includes a silicon nitride layer, and there is less residue when it is removed. This satisfies the process conditions without producing the opposite effect.
[0094] Optionally, the thickness of the sacrificial layer 5 can be the same as, less than or greater than the height of the weakening structure 4; this application does not limit the relationship between the thickness of the sacrificial layer 5 and the height of the weakening structure 4.
[0095] In some implementations, such as Figure 7 As shown, the thickness of the sacrificial layer 5 can be the same as the height of the weakening structure 4.
[0096] In the semiconductor structure fabrication method provided by the above embodiments, the thickness of the sacrificial layer 5 is the same as the height of the weakening structure 4. This allows the light-emitting surface of the chip 6 formed in subsequent processes to be on the same horizontal plane as the highest point of the weakening structure 4. This further reduces the contact area between the chip 6 and the weakening structure 4 after the sacrificial layer 5 is removed, thereby further reducing the difficulty of separating the chip 6 from the substrate 1, improving the chip separation efficiency, and reducing the damage that may be caused to the chip 6 during the separation process.
[0097] In some other possible implementations, the thickness of the sacrificial layer 5 may be less than the height of the weakening structure 4.
[0098] In the semiconductor structure fabrication method provided by the above embodiments, after the chip 6 is formed by subsequent processes, the weakened structure 4 can be partially embedded in the chip 6.
[0099] In the semiconductor structure fabrication method provided by the above embodiments, after the chip 6 is formed in the subsequent process, the weakening structure 4 is partially embedded in the chip 6. That is, the top of the weakening structure 4 can be partially embedded in the light-emitting surface of the chip 6. In this way, some uneven structures can be formed on the light-emitting surface of the chip 6 during the subsequent transfer process, increasing the adhesive adhesion area of the chip 6 during the subsequent transfer process. In addition, it can also be used as a way to roughen the light-emitting surface and improve the light extraction efficiency of the chip 6.
[0100] In step S4, please refer to Figures 8 to 10 Multiple chips 6 are formed; chip 6 can contact the weakened structure 4.
[0101] In some implementations, step S4 may include the following steps:
[0102] An epitaxial material layer 601 is formed on the upper surface of the sacrificial layer 5, such as... Figure 8 As shown; optionally, the epitaxial material layer 601 may include a buffer layer, an N-type layer, an active layer and / or a P-type layer, etc., and may also include functional layers such as an electron blocking layer, a stress relief layer, a current diffusion layer and / or a hole injection layer. This application does not limit the specific structure of the epitaxial material layer 601; optionally, the epitaxial material layer 601 may be formed by any of the following processes: physical vapor deposition, chemical vapor deposition, molecular beam epitaxy (MBE), magnetron sputtering, hydride vapor phase epitaxy (HVPE), metal-organic chemical vapor deposition (MOCVD) or ammonothermal method, etc. This application does not limit the specific method of forming the epitaxial material layer 601.
[0103] The epitaxial material layer 601 is patterned to form multiple epitaxial layers 602, such as... Figure 9 As shown; specifically, during the patterning process of the epitaxial material layer 601, the channel can be formed between adjacent weakened structures 4.
[0104] A first electrode 603 and a second electrode 604 are formed on the upper surface of each epitaxial layer 602 to form a chip 6, such as... Figure 10 As shown; optionally, the first electrode 603 can be an N electrode and the second electrode 604 can be a P electrode; optionally, both the first electrode 603 and the second electrode 604 can be, but are not limited to, aluminum electrodes, copper electrodes, nickel electrodes or tin electrodes, etc.
[0105] Specifically, during the patterning process of the epitaxial material layer 601, the patterned channels can be formed between adjacent weakened structures 4; that is, the orthogonal projection of the gap between adjacent chips 6 on the surface of the substrate 1 can be located between adjacent weakened structures 4.
[0106] Optionally, chip 6 may include, but is not limited to, flip-chip LEDs, vertical LEDs, or standard LEDs; this application does not limit this.
[0107] In some implementations, the spacing between adjacent weakening structures 4 is smaller than the width of the chip 6.
[0108] Based on the above implementation method, after removing the sacrificial layer 5, each chip 6 can contact at least two weakened structures 4.
[0109] The semiconductor structure fabrication method provided by the above embodiments, since each chip 6 is in contact with at least two weakening structures 4, can effectively support each chip 6, thereby improving the reliability and stability of the chip 6 transfer process.
[0110] Please see Figure 11 In some implementations, the following steps may be included after step S4:
[0111] S5: Remove sacrificial layer 5.
[0112] Optionally, the sacrificial layer 5 can be removed by a wet etching process, that is, by adding a solvent that can react with the sacrificial layer 5 between adjacent chips 6, but not limited to this process. It is understood that suitable removal chemicals and processes can be used for step S5, and this application does not limit the method of removing the sacrificial layer 5.
[0113] In addition, the removal process should have high selectivity relative to the substrate 1, that is, the removal rate of the sacrificial layer 5 should be significantly greater than the removal rate of the substrate 1, so that the removal process can be used to remove the sacrificial layer 5 without damaging the underlying substrate 1.
[0114] Please continue reading. Figure 11 Based on the same inventive concept, this application also provides a semiconductor structure according to some embodiments. The semiconductor structure is prepared by the semiconductor structure preparation method provided in the above embodiments. Therefore, the technical effects that can be achieved by the above semiconductor structure preparation method can also be achieved by the semiconductor structure, which will not be described in detail here.
[0115] Please see Figure 12Based on the same inventive concept, this application also provides a chip transfer method according to some embodiments, including the following steps:
[0116] S100: A semiconductor structure is prepared using the semiconductor structure preparation method provided in the above embodiments;
[0117] S200: The transfer device picks up the chip 6 and transfers the chip 6 to the surface of the backplane.
[0118] In step S100, since the semiconductor structure is prepared using the semiconductor structure preparation method provided in the above embodiments, the technical effects that the semiconductor structure preparation method provided in the above embodiments can achieve can also be achieved in step S100, and will not be described in detail here.
[0119] In step S200, a transfer device is used to pick up chip 6 and transfer chip 6 to the surface of the backplane.
[0120] Optionally, the chip 6 can be transferred to the surface of the backplane by performing a pick and place operation using a transfer head, but not limited to this method. This application does not limit the method of transferring the chip 6 to the surface of the backplane.
[0121] In some implementations, the picking and placing actions can be performed using a mass transfer head.
[0122] In some implementations, a portion of the chips 6 can be selectively transferred using a mass transfer head, or all of the chips 6 can be transferred at once using a mass transfer head.
[0123] The chip 6 transfer method provided in the above embodiments transfers the chip 6 to the surface of the backplane using a mass transfer head, achieving rapid transfer of the chip 6 and improving transfer efficiency. At the same time, it can also avoid the impact of high-energy laser on the circuit or other adjacent chips 6. In addition, the mass transfer has high accuracy, and transferring the chip 6 to the surface of the backplane using a mass transfer head can also improve the accuracy of the transfer.
[0124] Based on the same inventive concept, this application also provides a display panel according to some embodiments, including a back plate and a plurality of chips 6 located on the surface of the back plate.
[0125] Specifically, the display panel includes a plurality of chips that are transferred to the surface of the backplane using the chip transfer method provided in any of the above embodiments. Therefore, the display panel can also achieve the technical effects that the chip transfer method provided in any of the above embodiments can achieve, and will not be described in detail here.
[0126] Optionally, the display panel may include, but is not limited to, an LED display panel. This application does not limit the specific form of the display panel.
[0127] It should be understood that, although Figures 1 to 3 and Figure 12 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 1 to 3 and Figure 12 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0128] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: Provide substrate; The substrate is patterned to form multiple spaced weakened structures, the height of which is less than the initial height of the substrate. A sacrificial layer is formed between the weakened structures; Multiple chips are formed, the chips are in contact with the weakened structure, and the top of the weakened structure is embedded in the light-emitting surface of the chip; The step of patterning the substrate to form multiple spaced weakened structures includes the following steps: Multiple mask patterns are formed on the surface of the substrate, and the multiple mask patterns are arranged in an array on the surface of the substrate, with a spacing between adjacent mask patterns; The substrate is etched based on the mask pattern to form a plurality of spaced-apart weakened structures; The mask pattern includes particles; The process of forming multiple mask patterns on the surface of the substrate includes the following steps: Multiple initial particles are formed on the surface of the substrate, and the multiple initial particles are arranged in an array, with adjacent initial particles in contact with each other; Each of the initial particles is etched to obtain multiple mask patterns; Alternatively, the mask pattern may include a random pattern; The process of forming multiple mask patterns on the surface of the substrate includes the following steps: Multiple mask patterns are formed on the surface of the substrate based on simulation calculations.
2. The method for preparing the semiconductor structure according to claim 1, characterized in that, The longitudinal cross-sectional shape of the weakened structure includes triangles, spheres, arcs, curved surfaces, or polygons.
3. The method for preparing the semiconductor structure as described in claim 1, characterized in that, The spacing between adjacent weakening structures is less than the width of the chip; each chip is in contact with at least two of the weakening structures.
4. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that, After forming multiple chips on the sacrificial layer, the method further includes: removing the sacrificial layer.
5. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the semiconductor structure preparation method as described in any one of claims 1 to 4.
6. A chip transfer method, characterized in that, Includes the following steps: The semiconductor structure is prepared using the semiconductor structure preparation method as described in claim 4; The chip is picked up using a transfer device and transferred to the surface of the backplane.
7. A display panel, characterized in that, include: A backplane and a plurality of chips located on the surface of the backplane, wherein the plurality of chips are transferred to the surface of the backplane using the chip transfer method as described in claim 6.