Optoelectronic sensor device and display panel

Abstract

The application provides an optoelectronic sensor device and a display panel, and relates to the technical field of display. The optoelectronic sensor device comprises a gate electrode, an active layer and a photo-generated carrier layer which are stacked on a substrate; the photo-generated carrier layer is configured to generate photo-generated carriers under light; the active layer comprises a source region, a drain region and a channel region arranged between the source region and the drain region, and the channel region is attached to the photo-generated carrier layer; the gate electrode is arranged to be insulated from the channel region, and the voltage on the gate electrode is less than the threshold voltage of the channel region. The optoelectronic sensor device is simple in structure and can generate a strong electrical signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photoelectric sensors, and in particular to a photoelectric sensor device and a display panel. BACKGROUND

[0002] A photoelectric sensor is a device that converts a light signal into an electric signal. The photoelectric sensor is usually of a PIN structure, and the strength of the electric signal generated by the photoelectric sensor depends on the intensity of the light. The electric signal generated under low-intensity light is relatively weak, and therefore an amplifier power supply (APS) circuit needs to be provided to amplify and compensate the generated electric signal, resulting in a complex structure of the photoelectric sensor. SUMMARY

[0003] Embodiments of the present application provide a photoelectric sensor device and a display panel, which generate a relatively strong electric signal while having a simple structure.

[0004] To achieve the above object, embodiments of the present application adopt the following technical solutions:

[0005] In one aspect, a photoelectric sensor device is provided, comprising a gate, an active layer, and a photo-generated carrier layer which are stacked on a substrate;

[0006] The photo-generated carrier layer is configured to generate photo-generated carriers under light;

[0007] The active layer comprises a source region, a drain region, and a channel region disposed between the source region and the drain region, and the channel region is attached to the photo-generated carrier layer.

[0008] The gate is insulated from the channel region, and the voltage on the gate is less than the threshold voltage of the channel region.

[0009] In some embodiments, the photo-generated carrier layer comprises a doped semiconductor layer and an intrinsic semiconductor layer, and the intrinsic semiconductor layer is attached to the channel region.

[0010] In some embodiments, along a direction perpendicular to the substrate, the size of the intrinsic semiconductor layer is greater than the size of the active layer and the doped semiconductor layer.

[0011] In some embodiments, the intrinsic semiconductor layer and the channel region are coincident in the orthographic projection on the substrate.

[0012] In some embodiments, the gate is disposed on a side of the active layer away from the photo-generated carrier layer.

[0013] In some embodiments, the substrate is located on a side of the gate away from the active layer.

[0014] In some embodiments, the gate electrode is a transparent electrode, and the gate electrode is located on a side of the photo-generated carrier layer away from the active layer.

[0015] In some embodiments, the source region and the drain region are P-type semiconductor regions, and the doped semiconductor layer is an N-type semiconductor layer.

[0016] In another aspect, a display panel is provided, which includes the photoelectric sensor device.

[0017] In some embodiments, the display panel includes a plurality of pixel units arranged in an array, and each pixel unit includes a thin film transistor, and an active layer of the thin film transistor is arranged in the same layer as an active layer of the photoelectric sensor device.

[0018] The photoelectric sensor device provided by the embodiments of the present application has an active layer provided with a photo-generated carrier layer. The photo-generated carrier layer can generate photo-generated carriers under illumination. The generated photo-generated carriers can enter a channel region along a bonding surface between the photo-generated carrier layer and the channel region. The photo-generated carriers in the channel region form a current together with carriers accumulated under the driving of a gate electrode. Compared with the current formed by only the photo-generated carriers in the PIN-type photoelectric sensor device in the related art, the current formed by the photo-generated carriers and the carriers accumulated in the channel region has a larger value, thereby playing a role of signal amplification. Therefore, the photoelectric sensor device provided by the embodiments of the present application has a self-amplification effect on a photoelectric signal, does not need to be additionally provided with an APS circuit, and has a simpler structure while generating a stronger electric signal. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0020] Figure 1 FIG. 1 is a structural schematic diagram of a PIN-type photoelectric sensor in the related art;

[0021] Figure 2 FIG. 2 is a structural schematic diagram of a photoelectric sensor device provided by an embodiment of the present application;

[0022] Figures 3 to 7 FIG. 3 is a process flow diagram of a photoelectric sensor device provided by an embodiment of the present application;

[0023] Figures 8 to 13 FIG. 4 is a process flow diagram of a display panel provided by an embodiment of the present application;

[0024] Figure 14Another structural schematic diagram of a display panel provided in the embodiments of the present application.

[0025] Reference signs:

[0026] 1-P type layer; 2-I type layer; 3-N type layer; 4-second electrode; 5-first electrode; 6-photoresist;

[0027] 10-substrate;

[0028] 21-gate electrode; 22-first overlap structure; 23-light shielding layer;

[0029] 30-gate insulating layer;

[0030] 40-polysilicon layer; 41-channel region; 42-source region; 43-drain region; 44-second channel region;

[0031] 50-dielectric layer; 51-second gate insulating layer; 52-dielectric sublayer;

[0032] 61-intrinsic semiconductor layer; 62-doped semiconductor layer;

[0033] 70-planarization layer;

[0034] 81-source electrode; 82-drain electrode; 84-second source electrode; 85-second drain electrode;

[0035] 91-second overlap structure; 92-second gate electrode; 93-third overlap structure. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0037] In the embodiments of the present application, the same items or similar items with basically the same functions and effects are distinguished by using “first”, “second”, “third”, “fourth” and the like, only for clearly describing the technical solutions in the embodiments of the present application, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features.

[0038] In the embodiments of the present application, the meaning of “multiple” is two or more than two, and the meaning of “at least one” is one or more than one, unless otherwise explicitly and specifically limited.

[0039] In the embodiments of the present application, the terms "upper", "lower", and the like indicate the orientation or positional relationship shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0040] The photoelectric sensor is a key element for realizing photoelectric conversion in various photoelectric detection systems, and can convert optical signals (visible and ultraviolet laser light) into electrical signals. The photoelectric sensor in the related art usually includes a PIN type photoelectric sensor device, Figure 1 A structure diagram of the PIN type photoelectric sensor device in the related art is shown in FIG. 1. As shown in FIG. 1, the PIN type photoelectric sensor device includes a P-type layer 1, an I-type layer 2, and an N-type layer 3 which are sequentially stacked, and a first electrode 5 electrically connected with the P-type layer 1 and a second electrode 4 electrically connected with the N-type layer 3. Figure 1

[0041] When working, the strength of the electrical signal generated by the PIN type photoelectric sensor device depends on the intensity of the light, and the electrical signal generated under low-intensity light is relatively weak. Therefore, in order to improve the response of the photoelectric sensor, an APS circuit needs to be set, and the APS circuit is electrically connected with the PIN type photoelectric sensor device to amplify and compensate the electrical signal generated by the PIN type photoelectric sensor device.

[0042] However, the setting of the APS circuit makes the structure of the photoelectric sensor more complex. Moreover, the APS circuit usually includes a thin film transistor (TFT), and when the thin film transistor is an LTPS-TFT, in the process of preparing the photoelectric sensor, due to the process and specific guarantee, the APS circuit substrate is stacked with the PIN type photoelectric sensor device, resulting in a large number of film layer structures of the photoelectric sensor and a complex preparation process.

[0043] In view of this, the present application provides a photoelectric sensor device which has a self-amplification effect on the signal and does not need to additionally set an APS circuit, and has a simple structure.

[0044] Figure 2 A structure diagram of the photoelectric sensor device provided in the embodiments of the present application is shown in FIG. 2. As shown in FIG. 2, the photoelectric sensor device includes a substrate 10 and a gate electrode 21, an active layer, and a photo-generated carrier layer which are stacked on the substrate 10. Figure 2

[0045] The substrate 10 is used to support the film layer structures of the photoelectric sensor device. The substrate 10 can be a glass substrate, a silicon substrate, or an organic substrate, and the material of the substrate 10 is not limited in the present application.

[0046] ​​The photo-generated carrier layer is configured to generate photo-generated carriers under light. The photo-generated carrier layer can be made of a semiconductor material. When the semiconductor material is irradiated with light, if the energy of the photons is equal to or greater than the band gap width of the semiconductor material, the electrons in the valence band absorb the photons and enter the conduction band to generate electron-hole pairs, and the electrons and holes are called photo-generated carriers.

[0047] The active layer includes a source region 42, a drain region 43, and a channel region 41 disposed between the source region 42 and the drain region 43. The source region 42 is configured to be electrically connected to the source electrode 81, the drain region 43 is configured to be electrically connected to the drain electrode 82, and the gate electrode 21 is disposed to be insulated from the channel region 41. When the voltage between the gate electrode 21 and the source electrode 81 is greater than a threshold voltage, the channel region 41 can generate a channel. When a voltage is applied between the source electrode 81 and the drain electrode 82, an electric field is formed in the channel region 41, which drives the movement of carriers in the channel, thereby forming a current.

[0048] The voltage between the gate electrode 21 and the source electrode 81 that is just enough to form a channel in the channel region 41 is called the threshold voltage. When the voltage between the gate electrode 21 and the source electrode 81 is less than the threshold voltage, a channel cannot be formed in the channel region 41, and the channel region 41 operates in a sub-threshold region at this time.

[0049] The active layer can be made of a semiconductor material. Exemplarily, the source region 42 and the drain region 43 are heavily doped low-temperature polysilicon, and the channel region 41 is lightly doped or undoped low-temperature polysilicon. For example, the source region 42 and the drain region 43 are P-type semiconductors, and the channel region 41 is an intrinsic semiconductor. Of course, the materials of the source region 42, the drain region 43, and the channel region 41 can also be different.

[0050] The channel region 41 is attached to the photo-generated carrier layer. Here, attachment means that the channel region 41 is at least partially attached to the photo-generated carrier layer, which can be partial attachment or complete attachment. Complete attachment includes that the orthographic projection of the photo-generated carrier layer on the substrate 10 completely covers the orthographic projection of the channel region 41 on the substrate 10, and also includes that the orthographic projection of the channel region 41 on the substrate 10 completely covers the orthographic projection of the photo-generated carrier layer on the substrate 10.

[0051] The channel region 41 is attached to the photo-generated carrier layer, so that the photo-generated carriers generated by the photo-generated carrier layer after receiving light can enter the channel region 41 along the interface between the channel region 41 and the photo-generated carrier layer. The photo-generated carriers entering the channel region 41 form a current together with the carriers accumulated under the drive of the gate electrode 21. Compared with the current formed by photo-generated carriers alone, the current formed by photo-generated carriers and carriers accumulated in the channel region 41 itself has a larger value, thereby playing a role in signal amplification. That is, the channel region 41 operating in the sub-threshold region under the drive of the gate electrode 21 plays an amplification role on the electrical signal generated by the photoelectric effect.

[0052] The photoelectric sensor provided in the embodiments of the present application has a photo-generated carrier layer on the active layer. The photo-generated carrier layer can generate photo-generated carriers under illumination. The generated photo-generated carriers can enter the channel region 41 along the abutting surface of the photo-generated carrier layer and the channel region 41, and the photo-generated carriers entering the channel region 41 form a current together with the carriers accumulated under the driving of the gate 21. Compared with the current formed by the photo-generated carriers in the PIN type photoelectric sensor in the related art, the current formed by the photo-generated carriers and the carriers accumulated in the channel region 41 has a larger value, thereby playing a role of signal amplification. Therefore, the photoelectric sensor provided in the embodiments of the present application has a self-amplification effect on the photoelectric signal, does not need to additionally set an APS circuit, and has a simpler structure while generating a stronger electric signal.

[0053] In addition, since the APS circuit does not need to be additionally set, the problem of a large number of film layer structures and a complex preparation process caused by the laminated setting of the APS circuit and the photoelectric sensor is solved.

[0054] With reference to Figure 2 The photo-generated carrier layer can include a doped semiconductor layer 62 and an intrinsic semiconductor layer 61, and the doped semiconductor layer 62 and the intrinsic semiconductor layer 61 can be laminated. The intrinsic semiconductor layer 61 refers to a semiconductor layer that is not doped or lightly doped, and the doped semiconductor layer 62 refers to a heavily doped semiconductor layer. For example, the intrinsic semiconductor layer 61 is a polysilicon layer, and the doped semiconductor layer 62 is an N-type semiconductor layer.

[0055] The material of the intrinsic semiconductor layer 61 and the channel region 41 can be the same or different. For example, the intrinsic semiconductor layer 61 and the channel region 41 are both undoped polysilicon layers.

[0056] The intrinsic semiconductor layer 61 is abutted with the channel region 41. The abutting refers to that the channel region 41 is at least partially abutted with the intrinsic semiconductor layer 61, which can be partial abutting or complete abutting. The complete abutting includes that the orthographic projection of the intrinsic semiconductor layer 61 on the substrate 10 completely covers the orthographic projection of the channel region 41 on the substrate 10, or the orthographic projection of the channel region 41 on the substrate 10 completely covers the orthographic projection of the intrinsic semiconductor layer 61 on the substrate 10.

[0057] Within a certain range, the thicker the thickness of the intrinsic semiconductor layer 61 is, the better the absorption of light is, and the more the generated photo-generated carriers are. Therefore, the thickness of the intrinsic semiconductor layer 61 can be appropriately increased. The thickness of the intrinsic semiconductor layer 61 can be greater than the size of the active layer and the doped semiconductor layer 62, thereby improving the response of the photoelectric sensor. The thickness refers to the size in the direction perpendicular to the substrate 10.

[0058] The thickness of the intrinsic semiconductor layer 61 can be flexibly set according to the thickness of the channel region 41 and the thickness of the doped semiconductor layer 62, and the working parameters. For example, the thickness of the intrinsic semiconductor layer 61 can be equal to the thickness of the I-type layer in a PIN-type photoelectric sensor, the thickness of the doped semiconductor layer 62 can be equal to the thickness of the N-type layer in the PIN-type photoelectric sensor, and the thickness of the channel region 41 can be equal to the thickness of the P-type layer in the PIN-type photoelectric sensor. In this way, the PIN-type photoelectric sensor in the related art and the photoelectric sensor in the embodiment of the present application can be integrated in the same backplane without significantly increasing the film layer structure.

[0059] The intrinsic semiconductor layer 61 can coincide with the channel region 41 in the orthographic projection of the substrate 10. This makes the contact area of the intrinsic semiconductor and the channel region 41 larger, so that more photo-generated carriers in the intrinsic semiconductor enter the channel region 41, resulting in a larger current. In addition, the intrinsic semiconductor layer 61 coincides with the channel region 41 in the orthographic projection of the substrate 10, so that the orthographic projection of the intrinsic semiconductor layer 61 on the substrate 10 does not overlap with the orthographic projection of the source region 42 and the drain region 43 on the substrate 10, preventing interference.

[0060] The photo-generated carrier layer needs to receive light to generate photo-generated carriers, so it is necessary to reduce the obstruction between the photo-generated carrier layer and the light source to improve the response of the photoelectric sensor. The gate 21 can be arranged on the side of the active layer away from the photo-generated carrier layer, so that the light irradiated towards the photo-generated carrier layer is not obstructed by the gate 21. Moreover, the gate 21 is closer to the channel region 41, which can reduce the voltage between the gate 21 and the source 81.

[0061] For example, a gate insulating layer 30 is arranged between the gate 21 and the active layer, and the gate 21, the gate insulating layer 30, the active layer, and the photo-generated carrier layer are sequentially stacked.

[0062] Of course, the gate 21 can also be located on the side of the photo-generated carrier layer away from the active layer. At this time, in order to reduce the obstruction of the gate 21 to the light, the gate 21 can be a transparent electrode, for example, the gate 21 is an indium tin oxide electrode. Or the gate 21 has a hollow part in the upper part, so that light can pass through the gate 21 to irradiate the photo-generated carrier layer.

[0063] The substrate 10 can be located on the side of the gate 21 away from the active layer, so as to prevent the substrate 10 from obstructing the photo-generated carrier layer and improving the response of the photoelectric sensor. Of course, the substrate 10 can also be located on the side of the photo-generated carrier layer away from the active layer. At this time, the substrate 10 can be a transparent substrate 10, for example, a glass substrate 10.

[0064] Exemplarily, the photoelectric sensor device comprises a substrate 10 and a gate 21, a gate insulating layer 30, an active layer, a photo-generated carrier layer and a planar layer 70 which are sequentially stacked on the substrate 10. The gate insulating layer 30 is provided with a dielectric layer 50 and an electrode layer in sequence on the side away from the substrate 10, the electrode layer is located between the dielectric layer 50 and the planar layer 70, and the electrode layer comprises a source electrode 81 and a drain electrode 82, the source electrode 81 is electrically connected with the source region 42, and the drain electrode 82 is electrically connected with the drain region 43.

[0065] Exemplarily, the source region 42 and the drain region 43 are P-type semiconductor regions, and the doped semiconductor layer 62 is an N-type semiconductor layer.

[0066] It can be understood that, in actual application, the doping types of the active layer and the photo-generated carrier layer can be changed according to actual needs, which will not be described here.

[0067] The photoelectric sensor device provided by the embodiment of the present application can replace the PIN-type photoelectric sensor device in the related art, or can be used in cooperation with the PIN-type photoelectric sensor in the related art. When used in cooperation, the two can be integrated in the same backplane. In order to simplify the structure of the backplane and reduce the preparation difficulty and preparation cost, the structures of the two can be improved to match the process of the photoelectric sensor device provided by the embodiment of the present application and the PIN-type photoelectric sensor device in the related art.

[0068] Figures 3 to 7 A process flow chart of a backplane is shown in FIG. 1. As shown in FIG. 1, the preparation process comprises the following steps. Figures 3 to 7

[0069] In step 110, a substrate 10 is provided, a first conductive layer is deposited on the substrate 10, and the first conductive layer is patterned to form a gate 21 of a photoelectric sensor device.

[0070] The substrate 10 can be a glass substrate, which has low cost, high hardness and high temperature resistance. The first conductive layer can be a metal layer.

[0071] In step 120, a gate insulating layer 30 (GI) is deposited, and the gate insulating layer 30 covers the substrate 10 and the gate 21. Then, a layer of amorphous silicon (a-Si) is deposited on the gate insulating layer 30, and the a-Si is subjected to excimer laser annealing (ELA) and patterning to form a patterned low-temperature polysilicon 40 structure.

[0072] In the embodiment of the present application, the active layer is taken as an example of a low-temperature polysilicon material, and in actual application, it can also be other semiconductor materials, such as oxide semiconductor, single-crystal semiconductor, etc. The process flow can be improved adaptively on this basis.

[0073] ​Step 130: Deposit an interlayer dielectric (IDL) 50. Form a patterned photoresist 6 on the dielectric layer 50, and then perform P-type doping on the low-temperature polysilicon 40 to form the active layer of the photoelectric sensor. The active layer includes a P-type doped source region 42 and a drain region 43, as well as an undoped channel region 41. At the same time, a P-type layer 1 of the PIN junction is also formed.

[0074] In this process, photoresist 6 covers areas that do not require doping. Furthermore, the type of doping can be flexibly selected according to actual needs. When N-type doping is performed, an N-type layer 3 is formed for the PIN junction.

[0075] Step 140: Deep holes are etched on the dielectric layer 50 at positions corresponding to the P-type layer 1 and the channel region 41, so that the channel region 41 and the P-type layer 1 are at least partially exposed. Then, Ia-Si and Na-Si are sequentially deposited in the deep holes to form the intrinsic semiconductor layer 61 and the doped semiconductor layer 62 of the photoelectric sensor, as well as the I-type layer 2 and the N-type layer 3 of the PIN junction.

[0076] The material deposited in the deep hole can be selected according to actual needs, and no restrictions are imposed here.

[0077] Step 150: Vias are made at the locations of source region 42, drain region 43, and P-type layer 1 to form source electrode 81, drain electrode 82, first electrode 5, and second electrode 4. Source electrode 81 is electrically connected to source region 42, drain electrode 82 is electrically connected to drain region 43, first electrode 5 is electrically connected to P-type layer 1, and second electrode 4 is electrically connected to N-type layer 3. A planarization layer 70 is then applied to form a backplane structure.

[0078] Depend on Figures 3 to 7 It is understood that the photoelectric sensor device in the embodiments of this application and the PIN-type photoelectric sensor device in the related technology can be prepared in the same process flow, so that without changing the original backplane film layer structure, the photoelectric sensor device provided in the embodiments of this application can replace the PIN-type photoelectric sensor device in the related technology, and the photoelectric sensor device in the embodiments of this application and the PIN-type photoelectric sensor device can be prepared simultaneously in the same process flow.

[0079] In addition, the photoelectric sensor provided in this application embodiment can be integrated into the aforementioned back panel, or into the display panel, or into other panels, which will not be listed here one by one.

[0080] When photoelectric sensors are integrated into a display panel, the photoelectric sensors can be compatible with the manufacturing process of the display panel.

[0081] Figures 8 to 13 A process flow diagram of a display panel provided for the implementation of this application. (See diagram below.) Figures 8 to 13 As shown, the process includes:

[0082] In step 210, a substrate 10 is provided, and a second conductive layer is deposited on the substrate 10. After the second conductive layer is patterned, a gate 21, a first overlap structure 22, and a light shielding layer 23 of a TFT in a display panel of the photoelectric sensor device are formed.

[0083] The substrate 10 can be a glass substrate, which has a low cost, a high hardness, and a high temperature resistance. The second conductive layer can be a metal layer.

[0084] In step 220, a gate insulating layer 30 is deposited to cover the substrate 10 and the patterned second conductive layer. Then, an amorphous silicon (a-Si) layer is deposited on the gate insulating layer 30. The a-Si layer is subjected to excimer laser annealing (ELA) and patterning to form a patterned low-temperature polysilicon 40 structure.

[0085] In step 230, a second gate insulating layer 51 is deposited to cover the gate 21 insulating layer 30 and the patterned low-temperature polysilicon 40 structure. A third conductive layer is deposited on the second gate insulating layer 51. The third conductive layer is patterned to form a second gate 92, a second overlap structure 91, and a third overlap structure 93. The third overlap structure 93 is connected to the first overlap structure 22 through a via.

[0086] In step 240, a dielectric layer 52 is deposited to cover the patterned third conductive layer and the second gate insulating layer 51. A photoresist 6 is formed on the dielectric layer 52. The low-temperature polysilicon 40 structure is subjected to P-type doping to form an active layer of the photoelectric sensor device, a P-type layer 1 of a PIN junction, and a second channel region 44 of the TFT.

[0087] In step 250, a deep hole is etched on the dielectric layer 52 at positions corresponding to the P-type layer 1 and the channel region 41, so that the channel region 41 and the P-type layer 1 are at least partially exposed. Then, I-a-Si and N-a-Si are sequentially deposited in the deep hole to form an intrinsic semiconductor layer 61 and a doped semiconductor layer 62 of the photoelectric sensor device, and an I-type layer 2 and an N-type layer 3 of the PIN junction.

[0088] In step 260, a via is opened to form a source 81, a drain 82, a second source 84, a second drain 85, a first electrode 5, and a second electrode 4. A planar layer 70 is covered to form a display panel.

[0089] The display panel provided by the embodiments of the present application is provided with a photo-generated carrier layer on the active layer of the photoelectric sensor device, the photo-generated carrier layer can generate photo-generated carriers under light, the generated photo-generated carriers can enter the channel region 41 along the abutting surface of the photo-generated carrier layer and the channel region 41, and the photo-generated carriers entering the channel region 41 form a current together with the carriers accumulated under the driving of the gate 21. Compared with the current formed by the photo-generated carriers in the PIN type photoelectric sensor device in the related art, the current formed by the photo-generated carriers and the carriers accumulated in the channel region 41 itself has a larger value, thereby playing a role of signal amplification. Therefore, the photoelectric sensor device provided by the embodiments of the present application has a self-amplification effect on the photoelectric signal, does not need to additionally set an APS circuit, and has a simpler structure while generating a stronger electric signal.

[0090] The display panel includes a plurality of pixel units arranged in an array, the pixel unit includes a thin film transistor, and the active layer of the thin film transistor is arranged in the same layer as the active layer of the photoelectric sensor device. The TFT in the display panel can be prepared in a compatible process with the photoelectric sensor device, and the photoelectric sensor device can be integrated in the display panel without changing the original film layer structure of the display panel.

[0091] Figure 14 Another structure diagram of a display panel provided by the embodiments of the present application is shown in the figure, the structure in the dashed box is the TFT of the display panel, as shown in Figure 14 The photoelectric sensor device can also be arranged in a vertical direction perpendicular to the substrate together with the TFT of the display panel, which can reduce the signal crosstalk between the photoelectric sensor device and the TFT and save the arrangement space of the display panel in the direction parallel to the substrate.

[0092] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An optoelectronic sensor device, characterized by The photoelectric sensor comprises a gate, an active layer and a photo-generated carrier layer which are stacked on a substrate; The photo-generated carrier layer is configured to generate photo-generated carriers under light irradiation; The active layer comprises a source region, a drain region and a channel region arranged between the source region and the drain region, and the channel region is attached to the photo-generated carrier layer; The gate is insulated from the channel region, and a voltage on the gate is less than a threshold voltage of the channel region; The photo-generated carrier layer comprises a doped semiconductor layer and an intrinsic semiconductor layer, and the intrinsic semiconductor layer is attached to the channel region; the size of the intrinsic semiconductor layer is greater than the size of the active layer and the doped semiconductor layer; The intrinsic semiconductor layer and the channel region are in the same projection on the substrate.

2. The photosensor device according to any one of claims 1, characterized in that The gate is arranged on a side of the active layer away from the photo-generated carrier layer.

3. The photosensor device according to claim 2, characterized in that The substrate is located on a side of the gate away from the active layer.

4. The photosensor device according to any one of claims 1, wherein The gate is a transparent electrode, and the gate is located on a side of the photo-generated carrier layer away from the active layer.

5. The photosensor device according to claim 1, wherein The source region and the drain region are P-type semiconductor regions, and the doped semiconductor layer is an N-type semiconductor layer.

6. A display panel, characterized by, The photoelectric sensor comprises a gate, an active layer and a photo-generated carrier layer which are stacked on a substrate; 7. The display panel of claim 6, wherein, The display panel comprises a plurality of pixel units arranged in an array, and each pixel unit comprises a thin film transistor, and the active layer of the thin film transistor is arranged in the same layer as the active layer of the photoelectric sensor. The display panel comprises a plurality of pixel units arranged in an array, and each pixel unit comprises a thin film transistor, and the active layer of the thin film transistor is arranged in the same layer as the active layer of the photoelectric sensor.

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