A domestically produced gigabit network outgoing system and server based on VPX architecture

Abstract

This invention relates to a fully domestically produced gigabit network outreach system and server based on the VPX architecture. The system includes: a computing board comprising a domestically produced central processing unit (CPU), a domestically produced MAC controller connected to the CPU via a PCIe bus, and a pair of first domestically produced PHY transceivers connected to the MAC controller via an SMI bus and an RGMII bus; an interface board comprising a pair of second domestically produced PHY transceivers, a pair of domestically produced network transformers correspondingly connected to each second domestically produced PHY transceiver via an MDI bus, and a pair of RJ45 interfaces correspondingly connected to each domestically produced network transformer; and a VPX backplane providing a pair of first gigabit SerDes interfaces, each connecting one first domestically produced PHY transceiver and one second domestically produced PHY transceiver. This invention utilizes fully domestically produced chips to outreach gigabit SerDes interfaces conforming to the VPX standard framework.

Description

Technical Field

[0001] This invention relates to the field of servers, and more particularly to a fully domestically produced gigabit network outgoing system and server based on VPX architecture. Background Technology

[0002] The OpenVPX standard, released by the VITA organization in 2010, is an industry technical standard primarily targeting the military embedded computer market and is one of the most successful embedded computer bus standards. my country has defined detailed hardware architecture specifications for domestically developed computers based on this standard. However, when designing a computer board with four SerDes interfaces, domestically produced components cannot completely replace non-domestic components. This has led developers to modify and customize the VPX interface definition, or use other bus expansion methods to bypass the SerDes interface, resulting in compatibility issues between different products or wasted system resources.

[0003] Currently, when formulating hardware architecture specifications for domestically developed computers, the commonly used design for four-way gigabit SerDes ports is the I350 four-port gigabit Ethernet controller chip, which fully meets functional and performance requirements. Its external interfaces are as follows: uplink PCIe V2.1 x4 / x2 / x1, support for four-way 10 / 100 / 1000M BASE-T communication, support for four-way SerDes 1000BASE-SX fiber optic communication, support for four-way SerDes 1000BASE-KS backplane applications, support for four-way SGMII for external PHY connections, and support for NC-SI. However, when promoting 100% domestic production, the I350 cannot be used, and the WX1860 is generally used as a replacement. The WX1860's external interfaces are as follows: uplink PCIe V2.1 x4 / x2 / x1, support for four-way 10 / 100 / 1000M BASE-T communication, and support for four-way RGMII external PHY connections. However, the WX1860 chip does not support the SerDes interface, which makes it impossible to achieve complete domestic production when bringing out the network, so it urgently needs to be improved. Summary of the Invention

[0004] In view of this, it is necessary to provide a fully domestically produced gigabit network outgoing system and server based on VPX architecture to address the above technical issues.

[0005] According to a first aspect of the present invention, a fully domestically produced gigabit network outgoing system based on a VPX architecture is provided, the system comprising:

[0006] The computing board includes a domestic central processing unit, a domestic MAC controller connected to the domestic central processing unit via a PCIE bus, and a pair of first domestic PHY transceivers connected to the domestic MAC controller via an SMI bus and an RGMII bus, wherein each first domestic PHY transceiver operates in RGMII to SGMII mode.

[0007] The interface board includes a pair of second domestic PHY transceivers, a pair of domestic network transformers connected to each second domestic PHY transceiver via an MDI bus, and a pair of RJ45 interfaces connected to each domestic network transformer. Each second domestic PHY transceiver operates in SGMII power output mode.

[0008] The VPX backplane provides a pair of first gigabit SerDes interfaces, each of which connects to a first domestic PHY transceiver and a second domestic PHY transceiver.

[0009] In some embodiments, the system further includes a switchboard with a domestically produced SWITCH chip;

[0010] The computing board also includes a PCIe bridge chip disposed between the domestic central processing unit and the domestic MAC controller, the PCIe bridge chip being configured to provide a PCIe x2 bus to the domestic MAC controller;

[0011] The computing board also includes a pair of third domestic PHY transceivers connected to the domestic MAC controller via an SMI bus and an RGMII bus, wherein each third domestic PHY transceiver operates in RGMII optical output port mode.

[0012] The backplane is also equipped with a pair of second gigabit SerDes interfaces, which connect the domestically produced switch chip and a pair of third domestically produced PHY transceivers.

[0013] In some embodiments, the PCIe bridge chip leads to a PCIe x2 bus that is PCI Express 2.0.

[0014] In some embodiments, each first gigabit SerDes interface and each second gigabit SerDes interface support 10 / 100 / 1000M rate adaptation.

[0015] In some embodiments, each second domestically produced PHY transceiver is configured by default as rate adaptive and full-duplex.

[0016] In some embodiments, after the interface board is connected to the network cable to establish an external physical connection, each second domestic PHY transceiver performs the first rate duplex auto-negotiation with the first domestic PHY transceiver corresponding to the computing board through the SGMII bus.

[0017] In some embodiments, after the first rate duplex auto-negotiation is completed, the first domestic PHY transceiver performs a second rate duplex auto-negotiation with the domestic MAC controller via the RGMII bus and the SMI bus.

[0018] In some embodiments, the domestically produced central processing unit uses the Phytium D2000 / 8 chip.

[0019] In some embodiments, the domestic MAC controller uses the WX1860AL4 chip, and the first domestic PHY transceiver, the second domestic PHY transceiver, and the third domestic PHY transceiver all use the YT8531S chip.

[0020] According to a second aspect of the present invention, a server is provided, the server comprising the domestically produced gigabit network outgoing system based on the VPX architecture described above.

[0021] The aforementioned fully domestically produced gigabit network outgoing system and server based on the VPX architecture has at least the following beneficial effects: Under the requirement of 100% domestic design, four gigabit SerDes interfaces are brought out based on the OpenVPX standard framework, two of which are used as system interconnect interfaces and two as back-end interfaces. All four SerDes interfaces support 10 / 100 / 1000M adaptive and full / half-duplex modes. This solves the problem that existing fully domestic solutions cannot completely replace non-domestic solutions. By using fully domestically produced chips to bring out gigabit SerDes interfaces that comply with the VPX standard framework, it has better versatility. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0023] Figure 1 A schematic diagram of a domestically produced gigabit network outgoing system based on VPX architecture provided in one embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of the connection lines for another domestically produced gigabit network outgoing system based on the VPX architecture, provided as another embodiment of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0026] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0027] First, to facilitate understanding, the technical terms involved are explained as follows:

[0028] SMI stands for Serial Management Interface, also known as MII Management Interface, and includes two signal lines: MDC and MDIO. MDIO is a PHY management interface used to read / write PHY registers to control PHY behavior or obtain PHY status. MDC provides the clock for MDIO.

[0029] MDI (Media Dependent Interface), also known as an uplink port, is typically used for Ethernet port connections on PCs via NICs (Network Interface Cards) or integrated NIC ports. When the NIC's transmission signals need to be transmitted to the receiving signals of a hub or network switch, a straight-through cable must be used to connect the MDIX port.

[0030] RGMII, or Reduced GMII, is a simplified version of RGMII. It reduces the number of interface signal lines from 24 to 14 (COL / CRS port status indicator signals, not shown here). The clock frequency remains at 125MHz, and the TX / RX data width is reduced from 8 bits to 4 bits. To maintain a transmission rate of 1000Mbps, the RGMII interface samples data on both the rising and falling edges of the clock.

[0031] SGMII, short for Serial GMII, uses a pair of differential signal lines for both transmit and receive. The clock frequency is 625MHz, and sampling occurs on both the rising and falling edges of the clock signal. The reference clock RX_CLK is provided by the PHY and is optional, primarily used when there is no clock on the MAC side. Normally, RX_CLK is not used. The clock for both transmit and receive operations can be recovered from the data.

[0032] MII (Media Independent interface) is an industry standard defined by IEEE-802.3, and it is the interface between the MAC and PHY.

[0033] MAC, or Media Access Control, refers to the Media Access Control sublayer protocol. This part encompasses two concepts: a MAC can be a hardware controller, and the MAC communication protocol itself. This protocol resides in the lower half of the data link layer in the OSI seven-layer model, primarily responsible for controlling and connecting the physical media of the physical layer.

[0034] PHY, or Port Physical Layer, connects a data link layer device (MAC) to a physical medium, such as fiber optic or copper cable. A typical PHY includes PCS (Physical Coding Sublayer) and PMD (Physical Media Dependent Sublayer). PCS encodes and decodes the transmitted and received information to make it easier for the receiver to recover the signal.

[0035] In one embodiment, please refer to Figure 1 As shown, this invention provides a fully domestically produced gigabit network outgoing system based on VPX architecture. Specifically, the system includes the following structure:

[0036] The computing board includes a domestically produced central processing unit (CPU), a domestically produced MAC (Media Access Control) controller connected to the domestically produced CPU via a PCIe bus, and a pair of first domestically produced PHY transceivers connected to the domestically produced MAC controller via an SMI bus and an RGMII bus, wherein each first domestically produced PHY (Port Physical Layer) transceiver operates in RGMII to SGMII mode;

[0037] The interface board includes a pair of second domestic PHY transceivers, a pair of domestic network transformers connected to each second domestic PHY transceiver via an MDI bus, and a pair of RJ45 interfaces connected to each domestic network transformer. Each second domestic PHY transceiver operates in SGMII power output mode.

[0038] The VPX backplane provides a pair of first gigabit SerDes interfaces (not shown in the figure), each of which connects to a first domestic PHY transceiver and a second domestic PHY transceiver.

[0039] The aforementioned fully domestically produced gigabit network outgoing system based on the VPX architecture has the following advantages: Under the requirement of 100% domestic design, four gigabit SerDes interfaces are brought out based on the OpenVPX standard framework, two of which are used as system interconnect interfaces and two as back-end interfaces. All four SerDes interfaces support 10 / 100 / 1000M adaptive and full / half-duplex modes, which solves the problem that existing fully domestic solutions cannot completely replace non-domestic solutions. By using fully domestically produced chips to bring out gigabit SerDes interfaces that comply with the VPX standard framework, it has better versatility.

[0040] In some embodiments, the system further includes a switchboard with a domestically produced SWITCH chip;

[0041] The computing board also includes a PCIe bridge chip disposed between the domestic central processing unit and the domestic MAC controller, the PCIe bridge chip being configured to provide a PCIe x2 bus to the domestic MAC controller;

[0042] The computing board also includes a pair of third domestic PHY transceivers connected to the domestic MAC controller via an SMI bus and an RGMII bus, wherein each third domestic PHY transceiver operates in RGMII optical output port mode.

[0043] The backplane is also equipped with a pair of second gigabit SerDes interfaces (not shown in the figure), which connect the domestically produced SWITCH chip and a pair of third domestically produced PHY transceivers.

[0044] In some embodiments, the PCIe bridge chip leads to a PCIe x2 bus that is PCI Express 2.0.

[0045] In some embodiments, each first gigabit SerDes interface and each second gigabit SerDes interface support 10 / 100 / 1000M speed auto-adaptation.

[0046] In some embodiments, each second domestically produced PHY transceiver is configured by default as rate adaptive and full-duplex.

[0047] In some embodiments, after the interface board is connected to the network cable to establish an external physical connection, each second domestic PHY transceiver performs the first rate duplex auto-negotiation with the first domestic PHY transceiver corresponding to the computing board through the SGMII bus.

[0048] In some embodiments, after the first rate duplex auto-negotiation is completed, the first domestic PHY transceiver performs a second rate duplex auto-negotiation with the domestic MAC controller via the RGMII bus and the SMI bus.

[0049] In some embodiments, the domestically produced central processing unit uses the Phytium D2000 / 8 chip.

[0050] In some embodiments, the domestic MAC controller uses the WX1860AL4 chip, and the first domestic PHY transceiver, the second domestic PHY transceiver, and the third domestic PHY transceiver all use the YT8531S chip.

[0051] In yet another embodiment, please refer to Figure 2 As shown, to facilitate understanding of the present invention, the following example uses the Phytium D2000 / 8 chip as the central processing unit, the WX1860AL4 chip as the MAC controller, and the YT8531S Gigabit Ethernet transceiver as the PHY transceiver. This embodiment provides another domestically produced Gigabit network outgoing system based on the VPX architecture. The principle is as follows: The WX1860 can replace the I350 in MDI (Copper) Ethernet port applications and also has RGMII communication functionality, but lacks SerDes (SGMII) communication functionality. The domestic VPX specification interface definition stipulates that SerDes signals must be used to interconnect with the interface board through the VPX connector. Although using the WX1860 cannot directly meet the VPX specification requirements, since the WX1860 supports RGMII, we can connect to an external PHY through RGMII, and the external PHY can then extend the SerDes interface, thereby meeting the domestic VPX specification interface requirements.

[0052] The YT831S supports the following operating modes: Mode 0: UTP<->RGMII: RGMII output electrical port; Mode 1: Fiber<->RGMII: RGMII output optical port; Mode 2: UTP / Fiber<->RGMII: RGMII output electrical port, optical port automatic detection; Mode 3: UTP<->SGMII: SGMII output electrical port; Mode 4: SGMII(PHY)<->RGMII(MAC): SGMII to RGMII, MAC on the SGMII side; Mode 5: SGMII(MAC)<->RGMII(PHY): RGMII to SGMII, MAC on the RGMII side; Mode 6: UTP<->Fiber(AUTO): Electrical port to optical port adaptive rate; Mode 7: UTP<->Fiber(FORCE): Electrical port to optical port forced gigabit rate.

[0053] The system employs six YT8531S chips, designated A to F, and one WX1860AL4 chip. YT8531S C and YT8531S D serve as the first domestically produced PHY transceiver, YT8531S E and YT8531S F as the second domestically produced PHY transceiver, and YT8531S A and YT8531S B as the third domestically produced PHY transceiver. The specific connection relationships of each component are as follows: YT8531S chips A to D are connected to the WX1860AL4 chip via the SMI bus and RGMII bus. YT8531S A, YT8531S B, YT8531S C, and YT8531S D are each connected to the four Gigabit SerDes interfaces on the backplane via the SGMII bus, and are connected to YT8531S A and YT8531S F as the third domestically produced PHY transceiver. The two Gigabit SerDes interfaces corresponding to B are also connected to the SWITCH chip on the switching board via two SGMII buses. The two Gigabit SerDes interfaces corresponding to YT8531S C and YT8531S D are also connected to YT8531S E and YT8531S F respectively via two SGMII buses. YT8531S E and YT8531S F are connected to two network transformers via MDI buses. Finally, two RJ45 interfaces are led out from the two network transformers.

[0054] It should be noted that in this embodiment, YT8531S C and YT8531S D are configured to operate in Mode 5, YT8531S E and YT8531S F are configured to operate in Mode 3, and YT8531S A and YT8531S B are configured to operate in Mode 1. YT8531S A and YT8531S B need to connect to a switching board (similar to a network switch), so Mode 1 is used; the RGMII is converted to SerDes before connecting to the switching board. YT8531S C and YT831S D need to connect to an interface board and output two UTP ports. Since the VPX backplane can only use SerDes signals (standard limitation), the interface board needs a PHY chip to convert SerDes to UTP. This results in two PHY chips being connected in series on one network channel of the WX1860AL4, unlike the conventional architecture. This utilizes Mode 5 of the YT8531, a rarely used operating mode. In this mode, the RGMII is connected to the MAC (WX1860), acting as the PHY; then, the SGMII is connected to the PHY (YT8531) of the interface board, again acting as the MAC. The YT8531S on the interface board uses the conventional mode 3 to convert the SGMII from the VPX backplane into an Ethernet port. This enables the four Gigabit Ethernet ports to be brought out within the VPX framework, supporting 10 / 100 / 1000M adaptive speeds, and all implemented using domestically produced components.

[0055] During the data link establishment process, the YT8531S E / F is configured by default as rate adaptive and full-duplex, requiring no SMI management. Once the interface board is connected to the network cable and an external physical connection is established, the PHY (YT8531S E) completes rate-duplex auto-negotiation with the YT8531S C on the computing board via the SGMII bus. The YT8531S C then completes rate-duplex auto-negotiation with the WX1860AL4X chip via the RGMII and SMI buses, thus establishing a path between the physical layer and the data link layer.

[0056] The fully domestically produced gigabit network output system based on the VPX architecture in this embodiment has the following beneficial technical effects: under the OpenVPX standard framework, it uses all domestically produced components to realize four gigabit SerDes outputs, fully complies with the standard interface signal definition, and realizes basic functions such as 10 / 100 / 1000M adaptive and full / half-duplex modes of gigabit network ports, and the bandwidth test meets the standards.

[0057] In yet another embodiment, the present invention also provides a server comprising the domestically produced gigabit network outgoing system based on the VPX architecture described in the above embodiments.

[0058] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0059] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A fully domestically produced gigabit network outgoing system based on VPX architecture, characterized in that, The system includes: The computing board includes a domestic central processing unit, a domestic MAC controller connected to the domestic central processing unit via a PCIE bus, and a pair of first domestic PHY transceivers connected to the domestic MAC controller via an SMI bus and an RGMII bus, wherein each first domestic PHY transceiver operates in RGMII to SGMII mode. The interface board includes a pair of second domestic PHY transceivers, a pair of domestic network transformers connected to each second domestic PHY transceiver via an MDI bus, and a pair of RJ45 interfaces connected to each domestic network transformer. Each second domestic PHY transceiver operates in SGMII power output mode. The VPX backplane provides a pair of first gigabit SerDes interfaces, each of which connects to a first domestic PHY transceiver and a second domestic PHY transceiver.

2. The domestically produced gigabit network outgoing system based on VPX architecture according to claim 1, characterized in that, The system also includes a switching board with a domestically produced SWITCH chip; The computing board also includes a PCIe bridge chip disposed between the domestic central processing unit and the domestic MAC controller, the PCIe bridge chip being configured to provide a PCIe x2 bus to the domestic MAC controller; The computing board also includes a pair of third domestic PHY transceivers connected to the domestic MAC controller via an SMI bus and an RGMII bus, wherein each third domestic PHY transceiver operates in RGMII optical output port mode. The backplane is also equipped with a pair of second gigabit SerDes interfaces, which connect the domestically produced switch chip and a pair of third domestically produced PHY transceivers.

3. The domestically produced gigabit network outgoing system based on VPX architecture according to claim 2, characterized in that, The PCIe bridge chip leads to a PCIe x2 bus, which is PCI Express version 2.

0.

4. The domestically produced gigabit network outgoing system based on VPX architecture according to claim 2, characterized in that, Each first gigabit SerDes interface and each second gigabit SerDes interface supports adaptive speeds of 10M, 100M or 1000M.

5. The domestically produced gigabit network outgoing system based on VPX architecture according to claim 4, characterized in that, Each of the second domestically produced PHY transceivers is configured by default as rate adaptive and full-duplex.

6. The domestically produced gigabit network outgoing system based on VPX architecture according to claim 5, characterized in that, After the interface board is connected to the network cable to establish an external physical connection, each second domestic PHY transceiver performs the first rate duplex auto-negotiation with the first domestic PHY transceiver corresponding to the computing board through the SGMII bus.

7. The domestically produced gigabit network outgoing system based on VPX architecture according to claim 6, characterized in that, Once the first rate duplex auto-negotiation is completed, the first domestically produced PHY transceiver performs a second rate duplex auto-negotiation with the domestically produced MAC controller via the RGMII bus and SMI bus.

8. The domestically produced gigabit network outgoing system based on VPX architecture according to any one of claims 1 to 7, characterized in that, The domestically produced central processing unit uses the Phytium D2000 / 8 chip.

9. The domestically produced gigabit network outgoing system based on VPX architecture according to any one of claims 2-7, characterized in that, The domestic MAC controller uses the WX1860AL4 chip, and the first, second, and third domestic PHY transceivers all use the YT8531S chip.

10. A server, characterized in that, The server includes the domestically produced gigabit network outgoing system based on the VPX architecture as described in any one of claims 1-9.

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