Circuit testing method, device, electronic device and storage medium

Abstract

The present application relates to the field of computer technology, and in particular to a circuit testing method, device, electronic device and storage medium for improving the detection efficiency of the tracking encoder circuit function. The method includes: obtaining a test case for testing the tracking encoder circuit, and compiling the test case to generate an executable file and a disassembly file; loading the executable file into the core of the processor, obtaining the retired instruction address and other attribute information output by the core; compressing the retired instruction address and other attribute information to generate a tracking encoder file, and generating an actual instruction address file based on the disassembly file and the tracking encoder file; and, based on the retired instruction address, generating an expected instruction address file; comparing the expected instruction address file with the actual instruction address file, and analyzing the circuit function of the tracking encoder according to the comparison result. Based on the above method, the tracking encoder circuit function loopholes can be quickly discovered and the detection efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a circuit testing method, device, electronic device, and storage medium. Background Art

[0002] With the rapid development of computer technology, software applications for various scenarios have also emerged, such as video software, music software, and office software. Before the software is put into use, it is necessary to test whether the core can execute normally according to the corresponding software program. This requires reproducing all retired instruction addresses (Program Counter, PC) executed by the core to test the software.

[0003] In related technologies, a trace encoder (TE) can be used to reproduce all retired PCs executed by the core. Therefore, whether the TE circuit can function properly is crucial for software testing.

[0004] Traditional TE circuit testing is achieved through a modular testing approach. This involves creating a perfect reference model of the trace encoder (TE gold model) corresponding to the TE circuit, along with numerous test cases. The expected PC file output by the TE gold model is then compared with the actual PC file output by the TE to test for vulnerabilities in the TE circuit. However, this traditional modular testing approach requires creating different TE gold models for different trace protocols, as well as numerous test cases. This makes it difficult to quickly identify functional vulnerabilities in the TE circuit during early testing.

[0005] Therefore, how to quickly detect the function of TE circuits is an urgent problem to be solved. Summary of the Invention

[0006] The embodiments of the present application provide a circuit testing method, device, electronic device, and storage medium for improving the detection efficiency of TE circuit functions.

[0007] An embodiment of the present application provides a circuit testing method, comprising:

[0008] Obtaining a test case for testing a tracking encoder circuit, and compiling the test case to generate an executable file and a disassembly file;

[0009] Loading the executable file into a core of a processor, and obtaining retired instruction addresses and other attribute information output by the core;

[0010] Compressing the retired instruction addresses and other attribute information to generate a trace encoder file, and generating an actual instruction address file based on the disassembly file and the trace encoder file; and generating an expected instruction address file based on the retired instruction addresses;

[0011] The expected instruction address file is compared with the actual instruction address file, and the circuit function of the tracking encoder is analyzed based on the comparison result.

[0012] Optionally, compressing the retired instruction address and other attribute information to generate a tracking encoder file includes:

[0013] inputting the retirement instruction address and other attribute information into the tracking encoder;

[0014] Based on the tracking protocol, obtaining at least one compressed data packet corresponding to the tracking protocol and generated by the tracking encoder;

[0015] The at least one compressed data packet is placed in the trace encoder file.

[0016] Optionally, generating an actual instruction address file based on the disassembly file and the trace encoder file includes:

[0017] Decompressing the tracking encoder file based on the tracking decoder model to obtain a decompressed data packet;

[0018] Obtaining a starting retirement instruction address according to a starting decompressed data packet in the decompressed data packet, and writing the starting retirement instruction address into the actual instruction address file;

[0019] Based on the starting retirement instruction address, searching for a corresponding reference instruction address in the disassembly file, and reading an instruction attribute corresponding to the reference instruction address;

[0020] The actual instruction address file is generated according to the instruction attributes.

[0021] Optionally, generating the actual instruction address file according to the instruction attribute includes:

[0022] If the instruction attribute represents a linear instruction, then by searching the disassembly file, at least one linear instruction address that follows the reference instruction address is sequentially written into the actual instruction address file; until a nonlinear instruction address is found, the corresponding first jump instruction address is obtained based on the nonlinear decompressed data packet in the decompressed data packet, and the nonlinear instruction address and the first jump instruction address are written into the actual instruction address file; or

[0023] If the instruction attribute represents a non-linear instruction, a corresponding second jump instruction address is obtained based on the initial decompressed data packet, and the second jump instruction address is written into the actual instruction address file.

[0024] Optionally, analyzing the circuit function of the tracking encoder according to the comparison result includes:

[0025] When it is determined based on the comparison result that the expected instruction address file and the actual instruction address file are consistent, the circuit function of the tracking encoder is correct; or

[0026] When it is determined based on the comparison result that the expected instruction address file and the actual instruction address file are inconsistent, the circuit function of the tracking encoder is incorrect.

[0027] Optionally, the test case is at least one of a historical test case that has tested the kernel and a newly written test case.

[0028] An embodiment of the present application provides a circuit testing device, comprising:

[0029] A compiling unit, configured to obtain a test case for testing a tracking encoder circuit, and compile the test case into an executable file and a disassembly file;

[0030] an acquiring unit, configured to load the executable file into a core of a processor and acquire the retired instruction address and other attribute information output by the core;

[0031] a generating unit, configured to compress the retired instruction addresses and other attribute information to generate a trace encoder file, and to generate an actual instruction address file based on the disassembly file and the trace encoder file; and to generate an expected instruction address file based on the retired instruction addresses;

[0032] The comparison unit is used to compare the expected instruction address file with the actual instruction address file, and analyze the circuit function of the tracking encoder according to the comparison result.

[0033] Optionally, the generating unit is specifically configured to:

[0034] inputting the retirement instruction address and other attribute information into the tracking encoder;

[0035] Based on the tracking protocol, obtaining at least one compressed data packet corresponding to the tracking protocol and generated by the tracking encoder;

[0036] The at least one compressed data packet is placed in the trace encoder file.

[0037] Optionally, the generating unit is specifically configured to:

[0038] Decompressing the tracking encoder file based on the tracking decoder model to obtain a decompressed data packet;

[0039] Obtaining a starting retirement instruction address according to a starting decompressed data packet in the decompressed data packet, and writing the starting retirement instruction address into the actual instruction address file;

[0040] Based on the starting retirement instruction address, searching for a corresponding reference instruction address in the disassembly file, and reading an instruction attribute corresponding to the reference instruction address;

[0041] The actual instruction address file is generated according to the instruction attributes.

[0042] Optionally, the generating unit is specifically configured to:

[0043] If the instruction attribute represents a linear instruction, then by searching the disassembly file, at least one linear instruction address that follows the reference instruction address is sequentially written into the actual instruction address file; until a nonlinear instruction address is found, the corresponding first jump instruction address is obtained based on the nonlinear decompressed data packet in the decompressed data packet, and the nonlinear instruction address and the first jump instruction address are written into the actual instruction address file; or

[0044] If the instruction attribute represents a non-linear instruction, a corresponding second jump instruction address is obtained based on the initial decompressed data packet, and the second jump instruction address is written into the actual instruction address file.

[0045] Optionally, the comparison unit is specifically used for:

[0046] When it is determined based on the comparison result that the expected instruction address file and the actual instruction address file are consistent, the circuit function of the tracking encoder is correct; or

[0047] When it is determined based on the comparison result that the expected instruction address file and the actual instruction address file are inconsistent, the circuit function of the tracking encoder is incorrect.

[0048] Optionally, the test case is at least one of a historical test case that has tested the kernel and a newly written test case.

[0049] An embodiment of the present application provides an electronic device, which includes a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor performs the steps of any one of the above-mentioned circuit testing methods.

[0050] An embodiment of the present application provides a computer-readable storage medium, which includes a computer program. When the computer program is run on an electronic device, the computer program is used to enable the electronic device to execute the steps of any one of the above-mentioned circuit testing methods.

[0051] A computer program product provided in an embodiment of the present application includes a computer program, which is stored in a computer-readable storage medium; when a processor of an electronic device reads the computer program from the computer-readable storage medium, the processor executes the computer program, causing the electronic device to perform the steps of any of the above-mentioned circuit testing methods.

[0052] The beneficial effects of this application are as follows:

[0053] The embodiments of the present application provide a circuit testing method, device, electronic device and storage medium. Considering that the traditional TE circuit test is to input the test case into the TE gold model and the TE circuit respectively, and compare the expected instruction address file output by the TE gold model with the actual instruction address file output by the TE circuit, so as to test whether the TE circuit has vulnerabilities. The TE gold model functions of different tracing protocols are different and have low reusability. The present application provides a fast and universal circuit testing method. In the embodiments of the present application, an actual instruction address file is generated based on the disassembly file and the tracing encoder file, and an expected instruction address file is generated based on the retired instruction address output by the kernel. In this way, there is no need to write different TE gold models according to different tracing protocols, so that the test method and test device have universality, and the tracing encoder circuit function vulnerabilities can be quickly discovered in the early stage of testing, thereby improving the detection efficiency of the tracing encoder circuit function.

[0054] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0056] Figure 1 This is a schematic diagram of an application scenario in an embodiment of the present application;

[0057] Figure 2This is a flowchart of an implementation method of a circuit test in an embodiment of the present application;

[0058] Figure 3 A schematic diagram of a circuit testing method in an embodiment of the present application;

[0059] Figure 4 A schematic diagram of an expected PC file and an actual PC file in an embodiment of the present application;

[0060] Figure 5 A schematic diagram of another expected PC file and an actual PC file in an embodiment of the present application;

[0061] Figure 6 A schematic diagram of a specific implementation flow of a circuit testing method in an embodiment of the present application;

[0062] Figure 7 A schematic diagram of the structure of a circuit testing device according to an embodiment of the present application;

[0063] Figure 8 A schematic diagram of the structure of an electronic device in an embodiment of the present application;

[0064] Figure 9 A schematic diagram of the hardware structure of a computing device using an embodiment of the present application. DETAILED DESCRIPTION

[0065] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the technical solutions of the present application, but not all of them. Based on the embodiments described in this application document, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the technical solutions of the present application.

[0066] The following is an introduction to some concepts involved in the embodiments of this application.

[0067] A test case is a set of test inputs, execution conditions, and expected results compiled for a specific purpose, used to verify whether a specific software requirement is met. In this embodiment of the application, the test case is used to test whether the circuit function of the tracking encoder is correct.

[0068] Retirement and Retirement PC: Retirement indicates that an instruction has completed all operations and exited normally. The instruction address corresponding to the retired instruction is the retirement PC. The embodiments of this application involve a starting retirement PC, a linear retirement PC, and a nonlinear retirement PC. The starting retirement PC represents the first retired instruction address among the retirement instruction addresses output by the core; the linear retirement PC represents the instruction address corresponding to the linear retirement instruction; and the nonlinear retirement PC represents the instruction address corresponding to the nonlinear retirement instruction.

[0069] Reference instruction address: refers to the instruction address in the disassembly file that is the same as the starting retirement PC.

[0070] Executable file: refers to a file generated by compiling a test case through a compiler, for example, an Executable and Linkable Format (ELF) file.

[0071] Disassembly file: refers to the file obtained by disassembling the executable file generated by compiling the test case through the command tool.

[0072] Trace protocol: including but not limited to 5001 Forum standard (Nexus 5001 Forum TM Standard) protocol, Efficient Trace for RISC-V protocol.

[0073] Trace encoder: used to reproduce all retired PCs executed by the core. In the embodiment of the present application, based on the trace protocol, the trace encoder is used to generate a compressed data packet from the retired PCs and other attribute information output by the core. For example, based on the Nexus 5001 Forum TM For the Standard protocol, the compressed data packet generated by the trace encoder is called a Nexus Public Message. For the Efficient Trace for RISC-V protocol, the compressed data packet generated by the trace encoder is called an Instruction Trace encoder output packet.

[0074] Trace decoder: Based on the trace protocol, it is used to decompress the compressed data packets output by the trace encoder to obtain decompressed data packets.

[0075] The preferred embodiments of the present application are described below in conjunction with the drawings in the specification. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present application and are not used to limit the present application. In addition, the embodiments and features in the embodiments of the present application can be combined with each other if there is no conflict.

[0076] See Figure 1 , which is a schematic diagram of an application scenario of an embodiment of the present application. The application scenario diagram includes a CPU circuit 110 and an electronic device 120.

[0077] It should be noted that the circuit testing methods in each embodiment of the present application can be executed by an electronic device 120. The electronic device 120 may include a compilation module, a parsing module, and a PC comparison module. The CPU circuit 110 includes a core circuit and a TE circuit. For example, the electronic device 120 loads the executable file generated by the compilation module into the core circuit. The parsing module then parses the retired PC and corresponding attribute information output by the core circuit to generate an actual PC file and an expected PC file. Finally, the PC comparison module compares the actual PC file with the expected PC file, thereby realizing the detection of the TE circuit function.

[0078] Optionally, the electronic device may be a terminal device or a server, that is, the method may be executed by the terminal device or the server alone, or may be executed by the terminal device and the server together.

[0079] In the embodiments of the present application, the terminal device includes but is not limited to mobile phones, tablet computers, laptop computers, desktop computers and other devices; a client related to circuit testing can be installed on the terminal device, and the client can be software, or a web page, applet, etc. The server is a background server corresponding to the software or web page, applet, etc., or a server specifically used for circuit testing, which is not specifically limited in this application. The server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms.

[0080] In an optional embodiment, the CPU circuit 110 and the electronic device 120 may communicate with each other via a communication network.

[0081] In an optional implementation, the communication network is a wired network or a wireless network.

[0082] It should be noted that the CPU circuit can also be included in the electronic device. Figure 1 This is just a simple example and is not limited in this article.

[0083] The following describes the circuit testing method provided by the exemplary embodiment of the present application in combination with the application scenarios described above and with reference to the accompanying drawings. It should be noted that the above application scenarios are only shown to facilitate understanding of the spirit and principles of the present application, and the implementation of the present application is not limited in this respect.

[0084] See Figure 2 As shown, it is an implementation flow chart of a circuit testing method provided in an embodiment of the present application, with the terminal device as the execution subject. The specific implementation process of the method includes the following steps S201-S204:

[0085] S201: The terminal device obtains a test case for testing a tracking encoder circuit, and compiles the test case to generate an executable file and a disassembly file.

[0086] See Figure 3 , which is a schematic diagram of a circuit testing method provided by an embodiment of the present application. In this figure, the tracking encoder is one of the components of the CPU circuit in the terminal device, and the CPU circuit is composed of a core circuit and a tracking encoder circuit. In this method, the tracking encoder is the design under test (DUT).

[0087] The test case may be at least one of a historical test case for a tested core and a newly written test case. The test case may be written in C language or assembly language. The historical test case for a tested core refers to a test case used to test whether the core circuit functions correctly. Such a test case can be used to test whether the TE circuit functions correctly, such as a test case for testing linear instructions or a test case for testing jump instructions. A newly written test case refers to a test case written to test whether the TE circuit functions normally, such as a test case for testing abnormal conditions.

[0088] In the present application, when compiling the test case to generate an executable file, the test case can be compiled by the GNU compiler (GNU Compiler Collection, GCC) to generate a feasibility file, for example, the generated executable file is an ELF file.

[0089] The executable file includes but is not limited to: a segment header table, a code segment, a read-only data segment, a data segment, a symbol table, relocation information of the code segment, and relocation information of the data segment.

[0090] Compiling a test case to generate a disassembly file refers to disassembling the executable file generated by compiling the test case using a command tool. For example, an ELF file can be disassembled using a command tool (objdump) to generate a disassembly file.

[0091] The disassembly file includes a label address, a label name, an instruction address, an instruction machine code, and an instruction disassembled from the instruction machine code, wherein the label refers to the first address of each section of the disassembly file.

[0092] It should be noted that the test cases listed above are just simple examples and are not specifically limited in this article.

[0093] In the above method, historical test cases of the tested core are used, and there is no need to write a large number of test cases, which can improve the test efficiency of the circuit, shorten the test cycle, and reduce the test cost.

[0094] S202: Load the executable file into the core of the processor, and obtain the retired instruction address and other attribute information output by the core.

[0095] Specifically, other attribute information refers to information related to retired instructions, including but not limited to: instruction type, permission, instruction length, etc. Instruction type can be linear instruction, nonlinear instruction, etc.; permission represents the corresponding permission mode after the CPU executes the instruction, such as machine mode, supervisor mode, and general user mode; instruction length includes but is not limited to: 16-bit instruction length, 32-bit instruction length, etc.

[0096] S203: compressing retired instruction addresses and other attribute information to generate a trace encoder file, and generating an actual instruction address file based on the disassembly file and the trace encoder file; and generating an expected instruction address file based on the retired instruction addresses.

[0097] Specifically, compressing the retirement instruction address and other attribute information to generate a tracking encoder file means compressing the starting retirement PC, nonlinear retirement PC and corresponding attribute information in the retirement instruction address to generate a tracking encoder file.

[0098] Among them, when compressing the retired instruction address and other attribute information to generate the tracking encoder file, an optional implementation method is as follows:

[0099] ① Input the retirement instruction address and other attribute information into the tracking encoder;

[0100] ② Based on the tracking protocol, obtaining at least one compressed data packet corresponding to the tracking protocol generated by the tracking encoder;

[0101] ③ Place at least one compressed data packet in the tracking encoder file.

[0102] Specifically, tracking protocols include but are not limited to the following two: Nexus 5001 Forum TM Standard protocol, Efficient Trace for RISC-V protocol.

[0103] The compressed data includes but is not limited to the following: initial compressed data packet, non-linear compressed data packet, etc. Among them, the initial compressed data packet represents a data packet compressed based on the initial retired PC and related attributes, and the non-linear compressed data packet represents a data packet compressed based on the non-linear retired PC and related attributes.

[0104] Taking the Efficient Trace for RISC-V protocol as an example, based on this tracing protocol, the compressed data packet generated by the trace encoder is called: Instruction Trace encoder output packet (instruction trace encoder output packet), and then at least one Instruction Trace encoder output packet is composed of a trace encoder file.

[0105] For example, based on the Efficient Trace for RISC-V protocol, the trace encoder file generated by the trace encoder contains two compressed data packets. The first compressed data packet is the starting compressed data packet, which contains the starting retired PC 8000_0300; the second compressed data packet is the nonlinear compressed data packet, which contains the nonlinear retired PC 8000_030c.

[0106] It should be noted that the Efficient Trace for RISC-V protocol, the number of compressed data packets, the starting retirement PC, and the nonlinear retirement PC listed above are just simple examples and are not specifically limited in this article.

[0107] In the above method, the tracking encoder file generated by the tracking encoder does not contain the linear retired PC and the corresponding attribute information, that is, the linear retired PC and the corresponding attribute information do not need to be compressed to generate a data packet, which can save traffic.

[0108] By disassembling the file and the trace encoder file, the actual instruction address file is generated. There is no need to write different TE gold models according to different trace protocols, which can improve the detection efficiency of the trace encoder circuit.

[0109] An optional implementation is to generate an actual instruction address file based on the disassembly file and the trace encoder file:

[0110] ① Based on the tracking decoder model, decompress the tracking encoder file to obtain the decompressed data packet;

[0111] ②According to the starting decompressed data packet in the decompressed data packet, obtain the starting retirement instruction address and write the starting retirement instruction address into the actual instruction address file;

[0112] ③ Based on the starting retired instruction address, find the corresponding reference instruction address in the disassembly file and read the instruction attribute corresponding to the reference instruction address;

[0113] ④Generate actual instruction address file based on instruction attributes.

[0114] In an embodiment of the present application, different trace decoder models correspond to different trace protocols; the starting decompressed data packet representation is a data packet obtained by decompressing the starting compressed data packet; the reference instruction address representation is the instruction address in the disassembly file that is the same as the starting retired PC; the instruction attributes may include: linear instructions and non-linear instructions, wherein linear instructions include but are not limited to addition (add), exclusive OR (xor), storage (store), etc.; non-linear instructions include but are not limited to exceptions (exception), indirect jump instructions (jalr), and branch instructions when the carry flag is set (branch if equal, beq).

[0115] For example, decompressing two compressed data packets in a tracking encoder file yields two decompressed data packets, wherein the starting retirement PC in the first decompressed data packet is 8000_0300, and the nonlinear retirement PC in the second decompressed data packet is 8000_030c.

[0116] Write the starting retirement PC8000_0300 into the actual PC file, and find the corresponding reference PC in the disassembly file based on the starting retirement PC8000_0300. The reference PC is 8000_0300, and then check the corresponding instruction properties.

[0117] It should be noted that the number of compressed / decompressed data packets, starting retirement PC, nonlinear retirement PC and reference PC listed above are just simple examples and are not specifically limited in this article.

[0118] Among them, the actual instruction address file is generated according to the instruction attributes, as follows:

[0119] 1. If the instruction attribute represents a linear instruction, then by searching the disassembly file, at least one linear instruction address following the reference instruction address is written into the actual instruction address file in sequence; until a nonlinear instruction address is found, the corresponding first jump instruction address is obtained based on the nonlinear decompressed data packet in the decompressed data packet, and the nonlinear instruction address and the first jump instruction address are written into the actual instruction address file.

[0120] Specifically, a nonlinear instruction address is found, and the nonlinear instruction corresponding to the nonlinear instruction address does not indicate the next instruction address. It is necessary to obtain the next instruction address according to the nonlinear decompression data packet, that is, the first jump instruction address.

[0121] For example, the reference instruction corresponding to reference PC 8000_0300 is add, which means it is a linear instruction. By searching the disassembly file, the four instruction addresses following reference PC 8000_0300 are 8000_0302, 8000_0304, 8000_0308, and 8000_030c, respectively. 8000_0302, 8000_0304, and 8000_0308 are linear PCs, which are written into the actual PC file. 8000_030c is a nonlinear PC, and the jump PC found in the nonlinear decompression data packet is 8000_0312. Both 8000_030c and 8000_0312 are written into the actual PC file. The actual PCs in the actual PC file obtained are: 8000_0300, 8000_0302, 8000_0304, 8000_0308, 8000_030c, and 8000_0312.

[0122] It should be noted that the reference PCs, linear retirement PCs, jump PCs and the number of actual PCs in the actual PC files listed above are just simple examples and are not specifically limited in this article.

[0123] 2. If the instruction attribute represents a non-linear instruction, then based on the initial decompressed data packet, a corresponding second jump instruction address is obtained, and the second jump instruction address is written into the actual instruction address file.

[0124] Specifically, the start instruction attribute represents a non-linear instruction. The non-linear instruction does not indicate the next instruction address. It is necessary to obtain the next instruction address according to the start decompressed data packet, that is, the second jump instruction address.

[0125] For example, the reference instruction corresponding to reference PC 8000_0300 is jalr, which means it is a nonlinear instruction. The jump PC in the initial decompressed data packet is found to be 8000_0310, and 8000_0300 and 8000_0310 are written to the actual PC file. The actual PCs in the actual PC file are 8000_0300 and 8000_0310, respectively.

[0126] It should be noted that the number of actual PCs in the reference PC, jump PC and actual PC files listed above is just a simple example and is not specifically limited in this article.

[0127] In the above manner, based on the trace encoder file and the disassembled file, the actual retired PC file can be quickly generated.

[0128] S204: Compare the expected instruction address file with the actual instruction address file, and analyze the circuit function of the tracking encoder based on the comparison result.

[0129] In the embodiment of the present application, the circuit function of the tracking encoder is analyzed based on the comparison results, and there are two situations:

[0130] Case 1: When it is determined based on the comparison result that the expected instruction address file and the actual instruction address file are consistent, the circuit function of the tracking encoder is correct.

[0131] See Figure 4 As shown in FIG, which is a schematic diagram of an expected PC file and an actual PC file provided in an embodiment of the present application. In this figure, each row of PC in the expected PC file and the actual PC file is the same, that is, the expected PC file and the actual PC file are consistent, indicating that the circuit function of the tracking encoder is correct.

[0132] Case 2: When it is determined based on the comparison result that the expected instruction address file and the actual instruction address file are inconsistent, the circuit function of the tracking encoder is incorrect.

[0133] See Figure 5 As shown in FIG, which is a schematic diagram of another expected PC file and actual PC file provided in an embodiment of the present application. In this figure, the expected PC file and the actual PC file have different PCs starting from line 4, that is, the expected PC file and the actual PC file are consistent, indicating that the circuit function of the tracking encoder is incorrect.

[0134] Based on the above method, functional vulnerabilities in the tracking encoder circuit can be quickly discovered.

[0135] See Figure 6 As shown, it is a schematic diagram of a specific implementation process of a circuit testing method in an embodiment of the present application. The specific implementation process is as follows:

[0136] Step S601: Obtain test cases, compile and generate executable files and disassembly files;

[0137] Step S602: Load the executable file into the core of the processor, and obtain the retired instruction address and other attribute information output by the core;

[0138] Step S603: Based on the trace encoder, compress the retired instruction address and other attribute information to generate a trace encoder file;

[0139] Step S604: Generate an actual instruction address file based on the disassembly file and the trace encoder file;

[0140] Step S605: Generate an expected instruction address file based on the retired instruction address;

[0141] Step S606: Compare the expected instruction address file with the actual instruction address file;

[0142] Step S607: Determine whether the expected instruction address file is consistent with the actual instruction address file. If so, execute step S608; otherwise, execute step S609.

[0143] Step S608: Determine whether the circuit function of the tracking encoder is correct;

[0144] Step S609: Determine whether the circuit function of the tracking encoder is incorrect.

[0145] Based on the same inventive concept, the present application also provides a circuit testing device. Figure 7 As shown, it is a schematic diagram of the structure of a circuit testing device 700, which may include:

[0146] A compiling unit 701 is configured to obtain a test case for testing a tracking encoder circuit and compile the test case into an executable file and a disassembly file;

[0147] An acquisition unit 702 is configured to load the executable file into the core of the processor and acquire the retired instruction address and other attribute information output by the core;

[0148] A generating unit 703 is configured to compress the retired instruction addresses and other attribute information to generate a trace encoder file, and to generate an actual instruction address file based on the disassembly file and the trace encoder file; and to generate an expected instruction address file based on the retired instruction addresses;

[0149] The comparison unit 704 is configured to compare the expected instruction address file with the actual instruction address file, and analyze the circuit function of the tracking encoder based on the comparison result.

[0150] Optionally, the generating unit 703 is specifically configured to:

[0151] inputting the retirement instruction address and other attribute information into a tracking encoder;

[0152] Based on the tracking protocol, obtaining at least one compressed data packet corresponding to the tracking protocol and generated by the tracking encoder;

[0153] Place at least one compressed data packet in the trace encoder file.

[0154] Optionally, the generating unit 703 is specifically configured to:

[0155] Based on the tracking decoder model, the tracking encoder file is decompressed to obtain the decompressed data packet;

[0156] Obtaining a start retirement instruction address according to a start decompressed data packet in the decompressed data packet, and writing the start retirement instruction address into an actual instruction address file;

[0157] Based on the starting retired instruction address, find the corresponding reference instruction address in the disassembly file and read the instruction attribute corresponding to the reference instruction address;

[0158] Generate actual instruction address file based on instruction attributes.

[0159] Optionally, the generating unit 703 is specifically configured to:

[0160] If the instruction attribute represents a linear instruction, then by searching the disassembly file, at least one linear instruction address that follows the reference instruction address is sequentially written into the actual instruction address file; until a nonlinear instruction address is found, the corresponding first jump instruction address is obtained based on the nonlinear decompressed data packet in the decompressed data packet, and the nonlinear instruction address and the first jump instruction address are written into the actual instruction address file; or

[0161] If the instruction attribute represents a non-linear instruction, a corresponding second jump instruction address is obtained based on the initial decompressed data packet, and the second jump instruction address is written into the actual instruction address file.

[0162] Optionally, the comparison unit 704 is specifically configured to:

[0163] When it is determined based on the comparison result that the expected instruction address file and the actual instruction address file are consistent, the circuit function of the tracking encoder is correct; or

[0164] When it is determined based on the comparison result that the expected instruction address file and the actual instruction address file are inconsistent, the circuit function of the tracking encoder is incorrect.

[0165] Optionally, the test case is at least one of a historical test case of a tested kernel and a newly written test case.

[0166] For the convenience of description, the above parts are divided into modules (or units) according to their functions and described separately. Of course, when implementing this application, the functions of each module (or unit) can be implemented in the same or multiple software or hardware.

[0167] After introducing the circuit testing method and apparatus according to an exemplary embodiment of the present application, an electronic device according to another exemplary embodiment of the present application is introduced next.

[0168] Those skilled in the art will appreciate that various aspects of the present application can be implemented as systems, methods, or program products. Therefore, various aspects of the present application can be specifically implemented in the following forms: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation that combines hardware and software aspects, which may be collectively referred to herein as a "circuit," "module," or "system."

[0169] Based on the same inventive concept as the above method embodiment, an electronic device is also provided in the embodiment of the present application. In this embodiment, the structure of the electronic device can be as follows Figure 8 As shown, it includes a memory 801 , a communication module 803 and one or more processors 802 .

[0170] Memory 801 is used to store computer programs executed by processor 802. Memory 801 may mainly include a program storage area and a data storage area. The program storage area may store an operating system and programs required for running instant messaging functions, while the data storage area may store various instant messaging messages and operating instruction sets.

[0171] Memory 801 may be a volatile memory, such as random-access memory (RAM); a non-volatile memory, such as read-only memory, flash memory, a hard disk drive (HDD), or a solid-state drive (SSD); or any other medium capable of carrying or storing a desired computer program in the form of instructions or data structures and accessible by a computer, but is not limited thereto. Memory 801 may be a combination of the above memories.

[0172] The processor 802 may include one or more central processing units (CPUs) or digital processing units, etc. The processor 802 is configured to implement the circuit testing method described above when calling the computer program stored in the memory 801 .

[0173] The communication module 803 is used to communicate with terminal devices and other servers.

[0174] The specific connection medium between the memory 801, the communication module 803 and the processor 802 is not limited in the embodiment of the present application. Figure 8 In the embodiment, the memory 801 and the processor 802 are connected via a bus 804. Figure 8 The connections between the other components are shown in bold lines, which are only for illustration and are not intended to be limiting. The bus 804 can be divided into an address bus, a data bus, a control bus, etc. For ease of description, Figure 8 The diagram shows a single thick line, but this does not indicate that there is only one bus or one type of bus.

[0175] The memory 801 stores a computer storage medium, which stores computer executable instructions. The computer executable instructions are used to implement the circuit testing method of the embodiment of the present application. The processor 802 is used to execute the above-mentioned circuit testing method, such as Figure 2 shown.

[0176] Refer to the following Figure 9 hereinafter, a computing device 900 according to this embodiment of the present application is described. Figure 9 The computing device 900 is merely an example and should not limit the functions and scope of use of the embodiments of the present application.

[0177] like Figure 9 The computing device 900 is implemented as a general-purpose computing device. Components of the computing device 900 may include, but are not limited to, the at least one processing unit 901 described above, the at least one storage unit 902 described above, and a bus 903 connecting various system components (including the storage unit 902 and the processing unit 901).

[0178] Bus 903 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, and a processor or local bus using any of a variety of bus architectures.

[0179] The storage unit 902 may include a readable medium in the form of a volatile memory, such as a random access memory (RAM) 921 and / or a cache memory 922 , and may further include a read-only memory (ROM) 923 .

[0180] The storage unit 902 may also include a program / utility 925 having a set (at least one) of program modules 924, such program modules 924 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0181] The computing device 900 may also communicate with one or more external devices 904 (e.g., a keyboard, a pointing device, etc.), one or more devices that enable a user to interact with the computing device 900, and / or any device that enables the computing device 900 to communicate with one or more other computing devices (e.g., a router, a modem, etc.). Such communication may be performed via an input / output (I / O) interface 905. Furthermore, the computing device 900 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 906. Figure 9 As shown, network adapter 906 communicates with other modules used in computing device 900 via bus 903. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with computing device 900, including but not limited to microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0182] In some possible implementations, various aspects of the circuit testing method provided in the present application may also be implemented in the form of a program product, which includes a computer program. When the program product is run on an electronic device, the computer program is used to enable the electronic device to execute the steps of the circuit testing method according to various exemplary embodiments of the present application described above in this specification. For example, the electronic device may execute the following steps: Figure 2 Follow the steps shown in .

[0183] The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0184] The program product of the embodiment of the present application may be a portable compact disc read-only memory (CD-ROM) and include a computer program, and can be run on a computing device. However, the program product of the present application is not limited thereto. In this document, a readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with a command execution system, device, or device.

[0185] A readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries a readable computer program. Such a propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with a command execution system, apparatus, or device.

[0186] The computer program embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0187] The computer program for performing the operations of the present application may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, and the like, as well as conventional procedural programming languages such as "C" or similar programming languages. The computer program may be executed entirely on the user computing device, partially on the user device, as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0188] It should be noted that although several units or subunits of the device are mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, depending on the embodiment of the application, the features and functions of two or more units described above can be embodied in a single unit. Conversely, the features and functions of a single unit described above can be further divided and embodied by multiple units.

[0189] Furthermore, although the operations of the method of the present application are described in a particular order in the accompanying drawings, this does not require or imply that the operations must be performed in this particular order, or that all illustrated operations must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0190] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0191] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0192] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0193] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0194] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A circuit testing method, characterized in that: The method comprises: Obtaining a test case for testing a tracking encoder circuit, and compiling the test case to generate an executable file and a disassembly file; Loading the executable file into a core of a processor, and obtaining retired instruction addresses and other attribute information output by the core; The retired instruction address and other attribute information are compressed to generate a tracing encoder file, and the tracing encoder file is decompressed based on a tracing decoder model to obtain a decompressed data packet; a starting retired instruction address is obtained based on a starting decompressed data packet in the decompressed data packet, and the starting retired instruction address is written into an actual instruction address file; based on the starting retired instruction address, a corresponding reference instruction address in the disassembly file is searched, and an instruction attribute corresponding to the reference instruction address is read; the actual instruction address file is generated based on the instruction attribute; wherein, if the instruction attribute represents a nonlinear instruction, a corresponding second jump instruction address is obtained based on the starting decompressed data packet, and the second jump instruction address is written into the actual instruction address file; and based on the retired instruction address, an expected instruction address file is generated; The expected instruction address file is compared with the actual instruction address file, and the circuit function of the tracking encoder is analyzed based on the comparison result.

2. The method according to claim 1, wherein The step of compressing the retired instruction address and other attribute information to generate a tracking encoder file includes: inputting the retirement instruction address and other attribute information into the tracking encoder; Based on the tracking protocol, obtaining at least one compressed data packet corresponding to the tracking protocol and generated by the tracking encoder; The at least one compressed data packet is placed in the trace encoder file.

3. The method according to claim 1, wherein The generating of the actual instruction address file according to the instruction attribute further includes: If the instruction attribute represents a linear instruction, then by searching the disassembly file, at least one linear instruction address following the reference instruction address is written into the actual instruction address file in sequence; until a nonlinear instruction address is found, the corresponding first jump instruction address is obtained based on the nonlinear decompressed data packet in the decompressed data packet, and the nonlinear instruction address and the first jump instruction address are written into the actual instruction address file.

4. The method according to claim 1, wherein Analyzing the circuit function of the tracking encoder according to the comparison results includes: When it is determined based on the comparison result that the expected instruction address file and the actual instruction address file are consistent, the circuit function of the tracking encoder is correct; or When it is determined based on the comparison result that the expected instruction address file and the actual instruction address file are inconsistent, the circuit function of the tracking encoder is incorrect.

5. The method according to claim 1, wherein The test case is at least one of a historical test case that has tested the kernel and a newly written test case.

6. A circuit testing device, characterized in that: The device comprises: A compiling unit, configured to obtain a test case for testing a tracking encoder circuit, and compile the test case into an executable file and a disassembly file; an acquiring unit, configured to load the executable file into a core of a processor and acquire the retired instruction address and other attribute information output by the core; A generating unit is configured to compress the retired instruction address and other attribute information to generate a tracing encoder file, and decompress the tracing encoder file based on a tracing decoder model to obtain a decompressed data packet; obtain a starting retired instruction address based on a starting decompressed data packet in the decompressed data packet, and write the starting retired instruction address into an actual instruction address file; search for a corresponding reference instruction address in the disassembly file based on the starting retired instruction address, and read an instruction attribute corresponding to the reference instruction address; generate the actual instruction address file based on the instruction attribute; wherein, if the instruction attribute represents a nonlinear instruction, obtain a corresponding second jump instruction address based on the starting decompressed data packet, and write the second jump instruction address into the actual instruction address file; and generate an expected instruction address file based on the retired instruction address; The comparison unit is used to compare the expected instruction address file with the actual instruction address file, and analyze the circuit function of the tracking encoder according to the comparison result.

7. The device according to claim 6, characterized in that The generating unit is specifically configured to: inputting the retirement instruction address and other attribute information into the tracking encoder; Based on the tracking protocol, obtaining at least one compressed data packet corresponding to the tracking protocol and generated by the tracking encoder; The at least one compressed data packet is placed in the trace encoder file.

8. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor is enabled to perform the steps of any one of the methods of claims 1 to 5.

9. A computer-readable storage medium, characterized in that The method comprises a computer program. When the computer program is run on an electronic device, the computer program is used to enable the electronic device to execute the steps of any one of the methods according to claims 1 to 5.

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