Method, device, equipment and medium for detecting power-on timing sequence

Abstract

The present disclosure provides a method, device, equipment and medium for detecting power-on timing of a power supply, which relates to the field of semiconductor technology and is applied to a semiconductor chip. The semiconductor chip includes a power-on module, a combinational logic module and a plurality of power modules. The method specifically includes: sending a test stimulus to enable the semiconductor chip to enter the power-on process, monitoring a plurality of power-on signals sent by the power-on module, and dividing the plurality of power-on signals into a plurality of power-on time periods, monitoring the enable signal of the power module in the plurality of power-on time periods, determining the actual working status of the plurality of power modules in different power-on time periods, and further determining whether the working status of the plurality of power modules meets the expected working status. Through the above method, not only the relationship between the power module and the power-on signal can be accurately obtained, but also whether the actual working status of the power module meets the expected working status can be detected.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method, apparatus, device, and medium for detecting a power-on timing sequence of a power supply. Background Art

[0002] Semiconductor chips, such as dynamic random access memory (DRAM), include multiple types of power modules distributed throughout the chip to ensure proper operation. Some types of power modules can number in the thousands.

[0003] Therefore, during the power-on process of DRAM products, a large number of power modules are powered on in a certain order to ensure stable operation of the DRAM products. However, in the related art, it is impossible to accurately determine which power-on signals enable the power modules.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] The present disclosure provides a method, device, equipment and medium for detecting power-on timing of a power supply, which can not only accurately derive the relationship between the power module and the power-on signal, but also further detect whether the actual working state of the power module after being enabled meets the expected working state.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0007] In a first aspect, embodiments of the present disclosure provide a method for detecting a power-on timing sequence of a power supply, the method being applied to a semiconductor chip, the semiconductor chip comprising a power-on module, a combinational logic module, and a plurality of power supply modules; the power-on module being configured to sequentially generate power-on signals at different time points during a power-on process of the semiconductor chip, and the combinational logic module being configured to generate enable signals for the plurality of power supply modules based on the power-on signals;

[0008] The method comprises:

[0009] Sending a test stimulus to cause the semiconductor chip to enter a power-on process;

[0010] Monitoring the power-on signals sequentially issued by the power-on modules, and dividing the power-on time periods into different ones according to the generation order of the power-on signals;

[0011] monitoring the enable signals of the plurality of power modules to determine actual working states of the plurality of power modules in different power-on time periods;

[0012] Confirm whether the expected working states of the multiple power modules corresponding to the test stimulus are consistent with the actual working states of the multiple power modules.

[0013] In a possible embodiment, monitoring the power-on signals sequentially emitted by the power-on modules and dividing the power-on time periods into different periods according to the order in which the power-on signals are generated includes:

[0014] Obtain multiple time points when the power-on signals are generated, and divide the time period between any adjacent time point Ti when the i-th power-on signal is generated and the time point Ti+1 when the i+1-th power-on signal is generated as the i-th power-on period, where i is a positive integer greater than 0.

[0015] In a possible embodiment, monitoring the enable signals of the plurality of power modules to determine the actual working states of the plurality of power modules in different power-on time periods includes:

[0016] When the enable signal of the power module is at an invalid level during the current power-on period, determining that the actual working state of the power module during the current power-on period is a non-working state;

[0017] When the enable signal of the power module is converted from an invalid level to a valid level during the current power-on period, it is determined that the actual working state of the power module during the current power-on period is the starting working state;

[0018] When the enable signal of the power module is at a continuously valid level during the current power-on period, determining that the actual working state of the power module during the current power-on period is a working state;

[0019] When the enable signal of the power module is converted from an invalid level to a valid level and from a valid level to an invalid level during the current power-on period, it is determined that the actual working state of the power module during the current power-on period is a fault state.

[0020] In a possible embodiment, monitoring the enable signals of the plurality of power modules to determine the actual working states of the plurality of power modules in different power-on time periods further includes:

[0021] When the power module is in the initial working state during the i-th power-on period, it is determined that the power module is enabled by triggering the i-th power-on signal;

[0022] A mapping relationship between the power module and the power-on signal that triggers the power module to be enabled is established.

[0023] In a possible embodiment, the expected working states of the multiple power modules corresponding to the test stimulus include a mapping relationship between the power modules and power-on signals expected to trigger their enabling;

[0024] Confirming whether the expected working states of the plurality of power modules corresponding to the test stimulus are consistent with the actual working states of the plurality of power modules includes:

[0025] Confirm whether the mapping relationship between the power module and the power-on signal that triggers the enabling of the power module is consistent with the mapping relationship between the power module and the power-on signal that is expected to trigger the enabling of the power module.

[0026] In a possible embodiment, the method further includes a step of naming the power module, wherein the name of the power module includes the hierarchical path information of the power module and the instance name information of the power module.

[0027] In a possible embodiment, monitoring the enable signals of the plurality of power modules to determine the actual working states of the plurality of power modules in different power-on time periods further includes:

[0028] The number of power modules in the initial working state and the working state in different power-on time periods is counted.

[0029] In a possible embodiment, counting the total number of power modules in the initial working state and the working state in different power-on time periods includes:

[0030] According to the instance name information in the name of the power module, the number of power modules in the initial working state and the working state in different power-on time periods is classified and counted.

[0031] In a possible embodiment, the expected working states of the multiple power modules corresponding to the test stimulus include a classified and statistical number of expected power modules in the starting working state and the working state in different power-on time periods according to instance name information of the power modules;

[0032] Confirming whether the expected working states of the plurality of power modules corresponding to the test stimulus are consistent with the actual working states of the plurality of power modules includes:

[0033] Confirm whether the number of power modules with the same instance name information that are in the initial working state and the working state during each power-on period is consistent with the expected number of power modules.

[0034] In a possible embodiment, monitoring the enable signals of the plurality of power modules to determine the actual working states of the plurality of power modules in different power-on time periods further includes:

[0035] A report is generated, wherein the report includes the names of the multiple power modules, the actual working status of the multiple power modules in each power-on period, and the number of the power modules in the working status in each power-on period.

[0036] In a second aspect, embodiments of the present disclosure provide a device for detecting a power-on timing sequence of a power supply, the device being applied to a semiconductor chip, the semiconductor chip comprising a power-on module, a combinational logic module, and a plurality of power modules; the power-on module being configured to sequentially generate power-on signals at different time points during a power-on process of the semiconductor chip, and the combinational logic module being configured to generate enable signals for the plurality of power modules based on the power-on signals;

[0037] Wherein, the device comprises:

[0038] a sending unit, configured to send a test stimulus to cause the semiconductor chip to enter a power-on process;

[0039] A monitoring unit, configured to monitor the power-on signals sequentially sent by the power-on modules and divide the power-on time periods into different time periods according to the order in which the power-on signals are generated;

[0040] The monitoring unit is further configured to monitor the enable signals of the plurality of power modules to determine the actual working states of the plurality of power modules in different power-on time periods;

[0041] The confirmation unit is used to confirm whether the expected working states of the multiple power modules corresponding to the test stimulus are consistent with the actual working states of the multiple power modules.

[0042] In a possible embodiment, the monitoring unit is further configured to:

[0043] Obtain multiple time points when the power-on signals are generated, and divide the time period between any adjacent time point Ti when the i-th power-on signal is generated and the time point Ti+1 when the i+1-th power-on signal is generated as the i-th power-on period, where i is a positive integer greater than 0.

[0044] In a possible embodiment, the monitoring unit is further configured to:

[0045] When the enable signal of the power module is at an invalid level during the current power-on period, determining that the actual working state of the power module during the current power-on period is a non-working state;

[0046] When the enable signal of the power module is converted from an invalid level to a valid level during the current power-on period, it is determined that the actual working state of the power module during the current power-on period is the starting working state;

[0047] When the enable signal of the power module is at a continuously valid level during the current power-on period, determining that the actual working state of the power module during the current power-on period is a working state;

[0048] When the enable signal of the power module is converted from an invalid level to a valid level and from a valid level to an invalid level during the current power-on period, it is determined that the actual working state of the power module during the current power-on period is a fault state.

[0049] In a possible embodiment, the monitoring unit is further configured to:

[0050] When the power module is in the initial working state during the i-th power-on period, it is determined that the power module is enabled by triggering the i-th power-on signal;

[0051] A mapping relationship between the power module and the power-on signal that triggers the power module to be enabled is established.

[0052] In a third aspect, an embodiment of the present disclosure provides a computer device, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the method described in the first aspect above by executing the executable instructions.

[0053] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the method described in the first aspect when executed by a processor.

[0054] In a fifth aspect, according to another aspect of the present disclosure, a computer program product or computer program is further provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform any of the methods described above.

[0055] A method for detecting power-on timing provided by some embodiments of the present disclosure is applied to a semiconductor chip, wherein the semiconductor chip includes a power-on module, a combinational logic module, and multiple power modules. The power-on module is configured to sequentially generate power-on signals at different time points during the power-on process of the semiconductor chip, and the combinational logic module is configured to generate enable signals for multiple power modules based on the power-on signals. The method divides the different power-on signals generated at different time points into different power-on periods in sequence, and determines the actual working states of the multiple power modules in different power-on periods by monitoring the enable signals of multiple power modules. On the one hand, the relationship between the power module and the power-on signal is accurately derived, and it is determined which power module is enabled by which power-on signal. It is accurately understood which power modules are enabled by the power-on signal during different power-on processes of the semiconductor chip, and the functions that can be achieved during different power-on processes of the semiconductor chip can be accurately known. On the other hand, it can also detect whether the actual working state of the power module meets the expected working state.

[0056] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0058] Figure 1 A schematic diagram showing the structure of a system for detecting power-on timing in an embodiment of the present disclosure is shown;

[0059] Figure 2 A schematic structural diagram of a semiconductor chip according to an embodiment of the present disclosure is shown;

[0060] Figure 3 A schematic diagram showing a flow chart of a method for detecting a power-on timing sequence in an embodiment of the present disclosure is shown;

[0061] Figure 4 A schematic diagram showing generation of adjacent power-up signals according to an embodiment of the present disclosure is shown;

[0062] Figure 5 A schematic diagram showing a power-on signal triggering an enable signal in an embodiment of the present disclosure is shown;

[0063] Figure 6 A schematic diagram showing signal waveforms corresponding to a method for detecting a power-on timing sequence in an embodiment of the present disclosure is shown;

[0064] Figure 7 A schematic diagram showing a printing report in an embodiment of the present disclosure;

[0065] Figure 8 A schematic diagram showing a flow chart of a method for detecting a power-on timing sequence in an embodiment of the present disclosure is shown;

[0066] Figure 9 A schematic structural diagram of a device for detecting a power-on timing sequence in an embodiment of the present disclosure is shown;

[0067] Figure 10 A schematic structural diagram of a computer device according to an embodiment of the present disclosure is shown;

[0068] Figure 11 A schematic diagram illustrating a computer program product according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0069] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0070] In addition, the accompanying drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0071] Since the types and numbers of power modules in a semiconductor chip are very large, it is impossible to accurately determine which power-on signals enable the power modules during the power-on process of the semiconductor chip in the prior art.

[0072] Based on this, the present disclosure provides a method for detecting power-on timing, which is applied to a semiconductor chip. The semiconductor chip includes a power-on module, a combinational logic module and multiple power modules. The method specifically includes: when the semiconductor chip enters the power-on process, monitoring multiple power-on signals sent by the power-on module, and dividing the multiple power-on signals into multiple power-on time periods, and then monitoring the enable signal of the power module in multiple power-on time periods to determine the actual working status of the multiple power modules in different power-on time periods, and further determining whether the working status of the multiple power modules is normal. Through the above method, not only can it be accurately determined which power-on signals trigger the enable signals of which power modules, but it can also be detected whether the working status of the power module meets the expected working status.

[0073] In order to facilitate an overall understanding of the technical solution provided by the embodiment of the present disclosure, the semiconductor chip provided by the embodiment of the present disclosure will be described below.

[0074] Figure 1 FIG. 1 shows a schematic diagram of a system for detecting power-on timing according to an embodiment of the present disclosure. Figure 1 As shown, a system 100 for detecting a power-on sequence includes a computer device 101 and a semiconductor chip 102 .

[0075] Among them, the computer device 101 is used to send a test stimulus to the semiconductor chip 102 to enable the semiconductor chip to enter the power-on process, and monitor multiple power-on signals issued by the power-on module, and divide different power-on time periods according to the generation order of multiple power-on signals; monitor the enable signals of multiple power modules to determine the actual working status of multiple power modules in different power-on time periods; confirm whether the expected working status of multiple power modules corresponding to the test stimulus is consistent with the actual working status of multiple power modules.

[0076] Exemplarily, the computer device 101 may include a Verilog verification platform, and a test stimulus is sent to the semiconductor chip 102 via the Verilog verification platform.

[0077] The semiconductor chip 102 is used to receive a test stimulus and enter a power-on process, wherein the semiconductor chip in the present disclosure may be a dynamic random access memory.

[0078] Furthermore, Figure 2 A schematic structural diagram of a semiconductor chip provided by an embodiment of the present disclosure is shown. The semiconductor chip 102 includes a power-up module 112 , a first power module 122 - 1 , a second power module 122 - 2 , a third power module 122 - 3 , and a combinational logic module 132 .

[0079] The semiconductor chip 102 is used to receive a test stimulus, enter a power-on process, and generate a plurality of power-on signals during the power-on process through the power-on module 112 to enable the plurality of power modules.

[0080] The combinational logic module 132 is configured to generate enable signals for the plurality of power modules based on the power-on signal.

[0081] This exemplary implementation is described in detail below with reference to the accompanying drawings and examples.

[0082] Figure 3 A flow chart of a method for detecting a power-on timing sequence in an embodiment of the present disclosure is shown. The method is executed by a computer device and is applied to Figure 2 Semiconductor chips in Figure 3 As shown, the method for detecting the power-on timing sequence provided in the embodiment of the present disclosure includes the following steps:

[0083] S302: Sending a test stimulus to enable the semiconductor chip to enter a power-on process.

[0084] In one possible embodiment, a computer device sends a test stimulus to a semiconductor chip to cause the semiconductor chip to enter a power-up process. The power-up process can be understood as a process in which, after receiving the test stimulus, the semiconductor chip sends a power-up signal via a power-up module, causing the power module to power on.

[0085] S304: monitoring multiple power-on signals sent by the power-on module, and dividing different power-on time periods according to the generation order of the multiple power-on signals.

[0086] In a possible embodiment, since the current value of the semiconductor chip is relatively large during the power-on process, in order to alleviate the problem of excessive current pressure on the semiconductor chip caused by the excessive current value, after the semiconductor chip receives the test stimulus, the power-on module divides the time period into different time periods to send out power-on signals to complete the power-on process of the semiconductor chip.

[0087] By isolating the timing of different power-on signals and monitoring multiple power-on signals sent by the power-on module, computer equipment can not only power on the power module through the power-on signal, but also effectively reduce the current value of the semiconductor chip during the power-on process, thereby alleviating the current pressure of the semiconductor chip.

[0088] Specifically, the method for dividing the power-on time period between multiple power-on signals is as follows: obtain the time points when multiple power-on signals are generated, and divide the time period between any adjacent time point Ti when the i-th power-on signal is generated and the time point Ti+1 when the i+1-th power-on signal is generated in the timing sequence into the i-th power-on time period, where i is a positive integer greater than 0.

[0089] For example, Figure 4 A schematic diagram showing the generation of adjacent power-up signals is shown in FIG. Figure 4 As shown, the first power-on signal and the second power-on signal are used as an example for description. The first power-on signal and the second power-on signal are two adjacent power-on signals. Figure 4 As can be seen from the figure, the first power-on signal is generated at time T1, and the second power-on signal is generated at time T2. The time difference between T2 and T1 is a time period, that is, a power-on period. The power-on period T2-T1 is the first power-on period corresponding to the first power-on signal.

[0090] In another possible implementation, for any semiconductor chip, the timing of the power-on signal emitted by the power-on module of the semiconductor chip can be monitored first, and multiple power-on time periods of the semiconductor chip can be pre-divided. Then, the enable signal of the power module can be monitored according to the multiple pre-divided power-on time periods.

[0091] S306: Monitor the enable signals of the multiple power modules to determine actual working states of the multiple power modules in different power-on periods.

[0092] In one possible embodiment, after dividing the power-on time periods, the power-on process can be decomposed into a process of issuing a power-on signal in each power-on time period, enabling the power module by issuing a power-on signal in each power-on time period, and powering on the semiconductor chip. The enable signal is generated by the power-on signal through a combinational logic circuit.

[0093] Because in actual situations, the time interval between two adjacent power-on signal outputs is much longer than the time it takes for the power-on signal to generate an enable signal through the combinational logic circuit, the following method is designed based on this rule:

[0094] During the time period between the time point when each power-on signal is generated and the time point when its adjacent power-on signal is generated, the enable signals of multiple power modules are monitored to determine which power modules are enabled. The power modules enabled during the power-on period between two adjacent power-on signals are enabled by the previous power-on signal of the two adjacent power-on signals.

[0095] This can determine the trigger relationship between the power-on signal and the enable signal, and further determine which power-on signal specifically enables the power module. The power module can be enabled as "Enable", and the power module can be disabled as "Disable".

[0096] For example, the first power-on signal and the second power-on signal are used as examples for explanation. The power module includes a first power module and a second power module, and the enable signal includes a first enable signal of the first power module and a second enable signal of the second power module. The first power-on signal generates the first enable signal and the second enable signal through combinational logic.

[0097] If it is monitored that both the first enable signal and the second enable signal are converted from an invalid level to a valid level within the first power-on period, it is determined that the first power module and the second power module are triggered by the first power-on signal within the first power-on period.

[0098] Here, it is taken as an example that the invalid level is a low level and the valid level is a high level.

[0099] Figure 5 A schematic diagram showing a power-on signal triggering an enable signal is shown in FIG. Figure 5 As shown, if the first enable signal of the first power module and the second enable signal of the second power module change from a low level state to a high level state during the first power-on period, it can be determined that the first enable signal and the second enable signal are enabled by the first power-on signal. Based on this relationship, the correspondence between the first power-on signal and the first power module and the second power module can be determined, and it can be concluded that the first power module and the second power module are enabled by the first power-on signal. The first power module and the second power module are power modules of the same type and located at different positions on the semiconductor chip.

[0100] During the monitoring process, the name of the power module can be determined in advance based on the type of the power module and the position of the power module on the semiconductor chip.

[0101] For example, the name of the first power module may be Viso_ActAmp_AnalogChL;

[0102] The name of the second power module may be Viso_ActAmp_AnalogChR.

[0103] Viso_ActAmp indicates the types of the first power module and the second power module, from which it can be seen that the first power module and the second power module are power modules of the same type.

[0104] AnalogChL indicates that the first power module is used on AnalogChL, and AnalogChR indicates that the second power module is used on AnalogChR. This indicates the positions of the first and second power modules and can also be understood as the hierarchical path information between the first and second power modules.

[0105] It should be noted that in the above method, the enable signals of some power modules in the semiconductor chip can be selectively monitored, or the enable signals of all power modules can be monitored. Which power modules need to be monitored is preset before the detection.

[0106] In the above manner, after the enable signal of the power module is monitored, the actual working state of the power module can be determined based on the enable signal of the power module.

[0107] Based on the level of the enable signal of the power module, the actual working status can be divided into the following situations:

[0108] (1) Non-working state

[0109] When the enable signal of the power module is at an invalid level during the current power-on period, it is determined that the actual working state of the power module during the current power-on period is a non-working state.

[0110] (2) Initial working state

[0111] When the enable signal of the power module is converted from an invalid level to a valid level in the current power-on period, it is determined that the actual working state of the power module in the current power-on period is the initial working state.

[0112] For example, in Figure 5 In the example, the enable signal of the power module is obtained during the power-on period T1-T2, and both power modules are in the initial working state.

[0113] (3) Working status

[0114] When the enable signal of the power module is at a continuously valid level during the current power-on period, it is determined that the actual working state of the power module during the current power-on period is the working state.

[0115] For example, Figure 5 As shown, if during the power-on period after time T2, the first enable signal and the second enable signal both maintain a valid level, i.e., a high level state, it can be confirmed that the actual working states of the first power module and the second power module are in working state.

[0116] (4) Fault status

[0117] When the enable signal of the power module is converted from an invalid level to a valid level and from a valid level to an invalid level in the current power-on period, it is determined that the actual working state of the power module in the current power-on period is a fault state.

[0118] In the judgment process of the above four actual working states, the invalid level can be understood as a low level, and the valid level can be understood as a high level.

[0119] For the starting working state among the above four actual working states, the relationship between the power supply module and the power-on signal can be established through the actual working state. The specific method can be: if the power supply module is in the starting working state during the i-th power-on period, it is determined that the power supply module is triggered and enabled by the i-th power-on signal, and a mapping relationship between the power supply module and the power-on signal that triggers its enablement is established.

[0120] For example, Figure 5 As shown, during the power-on period T1-T2, according to the changes of the first enable signal and the second enable signal, after determining that the actual working state of the first power module and the second power module is the starting working state, it can be determined that the first power module and the second power module are both triggered by the first power-on signal, and a mapping relationship between the first power module and the second power module can be established.

[0121] S308: Confirm whether the expected working states of the multiple power modules corresponding to the test stimulus are consistent with the actual working states of the multiple power modules.

[0122] In a possible embodiment, after the computer device determines the actual working status of the multiple power modules corresponding to the test stimulus, it compares the actual working status with the expected working status of the multiple power modules corresponding to the test stimulus to determine whether the multiple power modules corresponding to the test stimulus meet expectations.

[0123] If so, the test process can be ended. If not, the relevant staff can be notified to modify the power module in the semiconductor chip whose actual working state does not match the expected working state.

[0124] For example, if the actual working state of the first power supply module is expected to be the initial working state and to remain in the working state, then Figure 5 As shown, the actual working state of the first power module in the first power-on period is consistent with the expected working state. If it is in the working state in other subsequent power-on periods, it means that the actual working state of the first power module is consistent with the expected working state.

[0125] Furthermore, whether the actual working state of the power supply module conforms to the expected working state can also be determined in the following way: by confirming whether the mapping relationship between the power supply module and the power-on signal that triggers its enablement is consistent with the mapping relationship between the power supply module and the power-on signal that is expected to trigger its enablement.

[0126] The expected working states of the multiple power modules corresponding to the test stimulus include a mapping relationship between the power modules and the power-on signals expected to trigger the enabling of the power modules.

[0127] For example, if the first power module is in the expected working state, there is a mapping relationship between the first power module and the second power-on signal, that is, the power-on signal that triggers the first power module to be enabled should be the second power-on signal. Figure 5 A mapping relationship is established between the first power-on signal and the first power module, and it is determined that the actual working state of the first power module is inconsistent with the expected working state.

[0128] Furthermore, whether the actual working states of the multiple power modules conform to the expected working states can be determined through the waveforms of the power-on signal and the enable signal.

[0129] For example, Figure 6 FIG. 1 is a schematic diagram showing a signal waveform corresponding to a method for detecting a power-on timing sequence in an embodiment of the present disclosure. Figure 6 As shown, it is taken as an example that the power-on signal includes a first power-on signal, a second power-on signal, a third power-on signal and a fourth power-on signal. Figure 6 PwrOn0 is the first power-on signal, PwrOn1 is the second power-on signal, PwrOn2 is the third power-on signal, and PwrOn3 is the fourth power-on signal.

[0130] For example, the power supply module includes a first power supply module, a second power supply module, and a third power supply module.

[0131] Among them, according to the specific types and positions of the first power module, the second power module and the third power module, the first power module, the second power module and the third power module can be named respectively, the first power module is Viso_ActAmp_AnalogChL, the second power module is Viso_ActAmp_AnalogChR, and the third power module is Vbn_Clamp_AnalogChR. Figure 6 In the example, the enable signal of the first power module is identified by the name of the power module, for example, Viso_ActAmp_AnalogChL.

[0132] For example, the enable signal includes a first enable signal of the first power module, a second enable signal of the second power module, and a third enable signal of the third power module.

[0133] Figure 6 T2-T1 is the first power-on period, which is the power-on period corresponding to the first power-on signal PwrOn0, T3-T2 is the second power-on period, which is the power-on period corresponding to the second power-on signal PwrOn1, and T4-T3 is the second power-on period, which is the power-on period corresponding to the third power-on signal PwrOn2. Figure 6 The signal waveform diagram is only for illustration purposes and may include more power-on signals and power-on periods, which will not be described in detail. Figure 6 The time T5 is the time when the fifth power-on signal is generated, and T5-T4 is the fourth power-on period.

[0134] For example, from Figure 6 It can be seen that the first enable signal and the second enable signal change from a low level state to a high level state in the second power-on period, and the third enable signal changes from a low level state to a high level state and then to a low level state in the third power-on period.

[0135] The expected working state of each power module may also include waveform diagrams of the power-on signal and the enable signal. By directly comparing the signal waveform diagram in the expected working state with the signal waveform diagram of the actual monitored power-on signal and the enable signal, it is possible to determine whether the actual working state of each power module is consistent with the expected working state.

[0136] For example, if the expected working state of the third power module is to enable the third power module, the third enable signal should change from a low level state to a high level state and remain in the high level state.

[0137] Figure 6 In the process, the actual working state of the third power supply module is judged according to the third enable signal. An electronic pulse (glitch) signal appears during the triggering process, which can be understood as a glitch in the waveform. This is inconsistent with the expected working state, and a prompt signal needs to be sent to prompt the modification of the circuit of the semiconductor chip so that the actual working state of the third power supply module after modification meets the expected working state.

[0138] Furthermore, in order to determine the actual working state of the power module, the number of power modules in the initial working state and the working state in different power-on time periods may be counted.

[0139] Illustratively, after monitoring the enable signal of the power module and determining the actual working state of the power module, the number of power modules in the initial working state and the working state in the actual working state of the power module can be counted.

[0140] A specific counting method may be: according to the instance name information in the name of the power module, classify and count the number of power modules in the starting working state and the working state in different power-on time periods.

[0141] By using the instance name information of the power module, when monitoring the enable signal of the power module, it is possible to determine which power module is enabled, and thus the number of power modules in the initial working state and the working state can be counted.

[0142] For example, if the first enable signal changes from an invalid level to a valid level during the first power-on period, the power module in the initial working state during the first power-on period is the first power module, and the number of power modules counted in the first power-on period is increased by 1.

[0143] Furthermore, after the statistics are completed, the number of power modules in the initial working state and the working state counted in different power-on time periods can be compared with the expected working state.

[0144] For example, in the expected working state, the number of power modules in the initial working state and the working state in the first power-on period is 3, and according to Figure 6 As shown in the signal waveform diagram, there are two power modules in the initial working state and the working state during the first power-on period. Therefore, the actual working state of one power module may be inconsistent with the expected working state.

[0145] If the number of power modules in the initial working state and working state during the first power-on period is 2, according to Figure 6 As shown in the signal waveform diagram, the number of power modules in the initial working state and the working state during the first power-on period is 2, so the actual working state of the power module during the first power-on period is consistent with the expected working state.

[0146] After judging in this way, further judgment can be made, specifically as follows: confirm whether the number of power modules with the same instance name information that are in the initial working state and the working state during each power-on period is consistent with the expected number of power modules.

[0147] Among them, the expected working states of the multiple power modules corresponding to the test stimulus may include: the expected number of power modules in the initial working state and the working state in different power-on time periods, which is classified and counted according to the instance name information of the power modules.

[0148] For example, if the number of power modules in the initial working state and the working state in the first power-on period is 2, and the instance name information of the power modules in the initial working state and the working state are respectively: Viso_ActAmp_AnalogChL and Viso_ActAmp_AnalogChR.

[0149] according to Figure 6As shown in the signal waveform diagram, the number of power modules in the starting working state and the working state during the first power-on period is 2, and the instance name information of the power modules in the starting working state and the working state is also Viso_ActAmp_AnalogChL and Viso_ActAmp_AnalogChR. Therefore, the actual working state of the power module during the first power-on period is consistent with the expected working state.

[0150] Further, if Figure 6 As shown, before the time point T1 at which the first power-on signal is generated, there can be a non-powered period before the power-on period, which can be referred to as Time 0.

[0151] During the power-off period, the enable signals of the power modules at an invalid level may be monitored, and the quantity information of the power modules may be obtained according to the enable signals of the power modules at an invalid level monitored.

[0152] For example, in the Time0 stage, it is necessary to count the number of power modules that need to be detected. By monitoring the enable signals corresponding to the power modules that need to be detected, it is confirmed how many enable signals are 0, which can be understood as a low-level state, and the total number of power modules with enable signals of 0 is recorded.

[0153] For example, the number of power modules can be counted by assuming that the power modules to be detected are enabled and accumulating the number of enabled power modules. The assumption that the power modules to be detected are enabled here refers to enabling them in the algorithm, not actually enabling the power modules, for the convenience of statistics. Figure 6 During the non-power-on period before the time point T1 at which the first power-on signal is generated, the power supply module is not enabled and is in a low level state.

[0154] Furthermore, the following method can be designed to process the signal, specifically: outputting a printed report based on the monitored actual working status of the power module in different power-on time periods.

[0155] The printed report records the level status of the enable signal in different power-on periods to indicate the actual working status of the power module in different power-on periods, and records the number of power modules at different positions on the semiconductor chip that are of the same type and at a valid level.

[0156] according to Figure 6The waveform of the signal can be output as a printed report. The report can include the names of multiple power modules, the actual working status of multiple power modules in each power-on period, and the number of power modules in working state in each power-on period. The signal waveform of the power-on signal and enable signal can also be printed out through the report. When it is necessary to check the signal according to the specific waveform, the waveform can be viewed.

[0157] Figure 7 A schematic diagram of printing a report is shown, Figure 7 shown.

[0158] When printing a report, the names of the first power module, the second power module, and the third power module can be directly printed out and used to identify the first power module, the second power module, and the third power module in the printed report. Specifically, Viso_ActAmp_AnalogChL in the printed report means the level status of the first power module.

[0159] "Viso_ActAmp" indicates the total number of power modules in the initial working state and the working state during the power-on period. It can be understood as the total number of power modules that are enabled during the power-on period and remain in the enabled state. It can also be understood as the total number of power modules that start to output power voltage and continue to output power voltage during the power-on period.

[0160] During the non-powered period, the number of power modules that need to be detected is counted. Therefore, when printing a report, the number of power modules that need to be detected counted during the non-powered period can be printed.

[0161] Specifically, based on the enable signal at a valid level in the monitored power module, a printed report is output, wherein the print report records the enable signal of the power module at a valid level and records the number of power modules of the same type at different positions on the semiconductor chip.

[0162] Here, the effective level is a low level state and the effective level is a high level state as an example.

[0163] For example, when printing a report, information indicating that the power module is disabled can be printed as information indicating that the power module is enabled during the "power-on period," thereby creating convenient conditions for statistics. This means that during monitoring, the low-level state is used for monitoring and counting, but when printing a report, the state is printed as a high-level state.

[0164] It should be noted that printing the information that the power module is not enabled as information that the power module is enabled in the "power-on period" can be understood as enabling the power module in the algorithm. In fact, no power is powered on during the non-powered period, such as Figure 6As shown in the waveform of the signal in FIG, all enable signals are in a low level state.

[0165] If you only look at Figure 7 From the report on the power-off period, we can see that there are three power modules when printing. Assuming that all three power modules are in a high-level state, only two are counted. This indicates that there may be a problem with the Vbn_Clamp_AnalogChR power module in the report.

[0166] During the power-on period, Figure 7 The level status of each power module in the is represented by 0 and 1, where 0 represents a low level state and 1 represents a high level state; 0-1 represents a change from a low level state to a high level state; 0-1-0 represents a change from a low level state to a high level state and then from a high level state to a low level state.

[0167] according to Figure 7 As shown, in each power-on period, the level states of the power modules are: in the first power-on period, the level states of the three power modules are all in a low level state; in the second power-on period, the level states of the first power module and the second power module change from a low level state to a high level state; in the third power-on period, the level states of the first power module and the second power module remain in a high level state, and the level state of the third power module changes from a low level state to a high level state, and then from a high level state to a low level state; in the fourth power-on period, the level states of the three power modules remain unchanged.

[0168] pass Figure 7 It can be seen from the printed report that the third power supply module has an electronic pulse in the third power-on period and remains in a low level state in the subsequent power-on period. It is not enabled, so a prompt message can be issued to prompt the circuit of the semiconductor chip to be modified.

[0169] Furthermore, the purpose of printing a report is to verify whether the actual operating state of the power module meets the expected operating state. For a particular power module A, the waveform of its enable signal during the Kth power-on period may not be a glitch. For example, the enable signal of power module A may change from a low level state to a high level state during the Kth power-on period, remain at a high level state during the K+2th power-on period, and then return to a low level state. In this case, if the expected operating state of power module A is not as expected, a prompt message will also need to be issued, and the semiconductor chip circuit will need to be modified.

[0170] For example, by Figure 7The printed report shown can determine the number of power modules enabled by each power-on signal. For example, in the first power-on period, the number of enabled power modules is 0, so the first power-on signal enables 0 power modules. In the second power-on period, the number of enabled power modules is 2, so the first power-on signal enables 2 power modules.

[0171] In a possible embodiment, if during the first power-on period, it is monitored that five power modules output power voltage, then the first power-on signal controls the five power modules, and the types and positions of the five power modules controlled by the first power-on signal can be seen in the printed report.

[0172] In the second power-on period, it is monitored that 15 power modules output power voltage, and the second power-on signal controls 10 power modules.

[0173] Through the method for detecting power-on timing disclosed in the present invention, not only the total number of power modules can be effectively determined, but also the relationship between the power-on signal and the enable signal of each power module can be used to understand which power modules different power-on signals act on during the power-on period of the semiconductor chip. Among the tens of thousands of power modules in the semiconductor chip, the time period in which each power module is enabled can be accurately understood, and the semiconductor chip can be used to accurately complete the task.

[0174] Furthermore, the present disclosure also displays different types of power modules and the number of power modules controlled by power-on signals in text form. By printing reports, it is possible to detect whether the actual working status of the power module meets the expected working status, check whether there are electronic pulses in the power module in the circuit of the semiconductor chip, and improve the accuracy of the semiconductor chip during subsequent use.

[0175] Figure 8 A flow chart of another method for detecting power-on timing is shown in FIG. Figure 8 As shown, the following steps are included:

[0176] S802: Send a test stimulus to enable the semiconductor chip to enter a power-on process.

[0177] S804: During the non-powered period, assuming that all power modules are enabled, monitor the enable signal at a high level.

[0178] S806: Obtain information on the quantity of power modules according to the monitored enable signal at a high level.

[0179] S808: monitoring multiple power-on signals sent by the power-on module, and dividing different power-on time periods according to the generation order of the multiple power-on signals.

[0180] S810: Print a report based on the monitored power-on signal and the enable signal of the power module.

[0181] S812: According to the printed report, confirm whether the expected working states of the multiple power modules corresponding to the test stimulus are consistent with the actual working states of the multiple power modules; if not, execute step S814; if consistent, end.

[0182] S814: Sending a prompt signal to prompt modification of the circuit of the semiconductor chip.

[0183] Based on the same inventive concept, the present disclosure also provides an apparatus for detecting a power-on timing sequence, as described in the following embodiment. Since the principles of the apparatus embodiment are similar to those of the above-described method embodiment, the implementation of the apparatus embodiment can refer to the implementation of the above-described method embodiment, and any repetitions will not be repeated.

[0184] Figure 9 The schematic diagram of the structure of a device for detecting power-on timing of a power supply in an embodiment of the present disclosure is shown. The device is applied to a semiconductor chip, which includes a power-on module and multiple power modules; the power-on module is used to generate multiple power-on signals at different time points during the power-on process of the semiconductor chip to generate enable signals for multiple power modules. Figure 9 As shown, the device 90 for detecting the power-on timing sequence includes:

[0185] The sending unit 901 is used to send a test stimulus to enable the semiconductor chip to enter a power-on process;

[0186] A monitoring unit 902 is configured to monitor multiple power-on signals sent by the power-on module and divide different power-on time periods according to the generation order of the multiple power-on signals;

[0187] The monitoring unit 902 is further configured to monitor the enable signals of the multiple power modules to determine the actual working status of the multiple power modules in different power-on periods;

[0188] The confirmation unit 903 is configured to confirm whether the expected working states of the multiple power modules corresponding to the test stimulus are consistent with the actual working states of the multiple power modules.

[0189] In a specific implementation, the computer device can execute the implementation methods provided by the various steps in any of the above method embodiments through its built-in functional modules. For details, please refer to the implementation methods provided by the various steps in the figure shown in the above method embodiments, which will not be repeated here.

[0190] Figure 10 This is a schematic diagram of the structure of a computer device provided by an embodiment of the present disclosure. Figure 10As shown, the computer device in the embodiment of the present disclosure may include: one or more processors 1001, a memory 1002, and an input / output interface 1003. The processor 1001, the memory 1002, and the input / output interface 1003 are connected via a bus 1004. The memory 1002 is used to store computer programs, which include program instructions. The input / output interface 1003 is used to receive and output data, such as for performing data exchange between a host computer and the computer device, or for performing data exchange between virtual machines in the host computer. The processor 1001 is used to execute the program instructions stored in the memory 1002.

[0191] The processor 1001 may perform the following operations:

[0192] Send a test stimulus to enable the semiconductor chip to enter the power-on process; monitor multiple power-on signals sent by the power-on module, and divide different power-on time periods according to the generation order of multiple power-on signals; monitor the enable signals of multiple power modules to determine the actual working status of multiple power modules in different power-on time periods; confirm whether the expected working status of multiple power modules corresponding to the test stimulus is consistent with the actual working status of multiple power modules.

[0193] In some feasible implementations, the processor 1001 may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor, or the processor may be any conventional processor, etc.

[0194] The memory 1002 may include a read-only memory and a random access memory, and provides instructions and data to the processor 1001 and the input / output interface 1003. A portion of the memory 1002 may also include a non-volatile random access memory. For example, the memory 1002 may also store device type information.

[0195] In a specific implementation, the computer device can execute the implementation methods provided by the various steps in any of the above method embodiments through its built-in functional modules. For details, please refer to the implementation methods provided by the various steps in the figure shown in the above method embodiments, which will not be repeated here.

[0196] The embodiments of the present disclosure provide a computer device including a processor, an input / output interface, and a memory. The processor obtains a computer program in the memory to execute the steps of the method shown in any of the above embodiments.

[0197] The present disclosure also provides a computer-readable storage medium storing a computer program. Figure 11 A schematic diagram of a computer-readable storage medium according to an embodiment of the present disclosure is shown. Figure 11 As shown, the computer-readable storage medium 1100 stores a program product capable of implementing the above-mentioned method of the present disclosure. The computer program is suitable for being loaded by the processor and executing the method for detecting the power-on timing provided by the various steps in any of the above-mentioned embodiments. For details, please refer to the implementation methods provided by the various steps in any of the above-mentioned embodiments, which will not be repeated here. In addition, the description of the beneficial effects of adopting the same method will not be repeated. For technical details not disclosed in the computer-readable storage medium embodiment involved in the present disclosure, please refer to the description of the method embodiment of the present disclosure. As an example, the computer program can be deployed to be executed on a computer device, or on multiple computer devices located at one location, or on multiple computer devices distributed at multiple locations and interconnected by a communication network.

[0198] The computer-readable storage medium can be the device for detecting the power-on timing of any of the aforementioned embodiments or the internal storage unit of the computer device, such as the hard disk or memory of the computer device. The computer-readable storage medium can also be an external storage device of the computer device, such as a plug-in hard disk, a smart memory card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the computer device. Furthermore, the computer-readable storage medium can also include both the internal storage unit of the computer device and an external storage device. The computer-readable storage medium is used to store the computer program and other programs and data required by the computer device. The computer-readable storage medium can also be used to temporarily store data that has been output or is to be output.

[0199] The present disclosure also provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the method provided in any of the optional embodiments described above.

[0200] The terms "first", "second", etc. in the description, claims, and drawings of the embodiments of the present disclosure are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product, or device that includes a series of steps or units is not limited to the listed steps or modules, but may optionally include steps or modules that are not listed, or may optionally include other steps and units inherent to these processes, methods, apparatuses, products, or devices.

[0201] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in this description according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this disclosure.

[0202] The methods and related devices provided by the embodiments of the present disclosure are described with reference to the method flow charts and / or structural diagrams provided by the embodiments of the present disclosure. Specifically, each process and / or block in the method flow charts and / or structural diagrams, as well as the combination of processes and / or blocks in the flow charts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable application display device to generate a machine, so that the instructions executed by the processor of the computer or other programmable application display device generate instructions for implementing the process. Figure 1 Schematic diagram of one or more processes and / or structures Figure 1 These computer program instructions can also be stored in a computer readable memory that can guide a computer or other programmable application display device to work in a specific way, so that the instructions stored in the computer readable memory produce a product including an instruction device, which implements the function specified in the process. Figure 1 Schematic diagram of one or more processes and / or structures Figure 1 These computer program instructions can also be loaded onto a computer or other programmable application display device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide the functions for implementing the process. Figure 1 The flow or flows and / or structures illustrate the steps of the functions specified in one block or multiple blocks.

[0203] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope of the present disclosure being indicated by the appended claims.

Claims

1. A method for detecting a power-on timing sequence, characterized in that: The method is applied to a semiconductor chip, which includes a power-on module, a combinational logic module, and multiple power modules; the power-on module is configured to sequentially generate power-on signals at different time points during the power-on process of the semiconductor chip, and the combinational logic module is configured to generate enable signals for the multiple power modules based on the power-on signals; The method comprises: Sending a test stimulus to cause the semiconductor chip to enter a power-on process; Monitoring the power-on signals sequentially issued by the power-on modules, and dividing the power-on time periods into different ones according to the generation order of the power-on signals; monitoring the enable signals of the plurality of power modules to determine actual working states of the plurality of power modules in different power-on time periods; confirming whether the expected working states of the plurality of power modules corresponding to the test stimulus are consistent with the actual working states of the plurality of power modules; The monitoring of the power-on signals sequentially issued by the power-on modules and the division of the different power-on time periods according to the order in which the power-on signals are generated include: Obtaining multiple time points when the power-on signals are generated, dividing the time period between any adjacent time point Ti when the i-th power-on signal is generated and the time point Ti+1 when the i+1-th power-on signal is generated as the i-th power-on period, where i is a positive integer greater than 0; The monitoring of the enable signals of the plurality of power modules to determine the actual working states of the plurality of power modules in different power-on time periods includes: When the enable signal of the power module is at an invalid level during the current power-on period, determining that the actual working state of the power module during the current power-on period is a non-working state; When the enable signal of the power module is converted from an invalid level to a valid level during the current power-on period, it is determined that the actual working state of the power module during the current power-on period is the starting working state; When the enable signal of the power module is at a continuously valid level during the current power-on period, determining that the actual working state of the power module during the current power-on period is a working state; When the enable signal of the power module is converted from an invalid level to a valid level and from a valid level to an invalid level during the current power-on period, it is determined that the actual working state of the power module during the current power-on period is a fault state.

2. The method according to claim 1, wherein Monitoring the enable signals of the plurality of power modules to determine actual working states of the plurality of power modules in different power-on time periods further includes: When the power module is in the initial working state during the i-th power-on period, it is determined that the power module is enabled by triggering the i-th power-on signal; A mapping relationship between the power module and the power-on signal that triggers the power module to be enabled is established.

3. The method according to claim 2, wherein The expected working states of the plurality of power modules corresponding to the test stimulus include a mapping relationship between the power modules and power-on signals expected to trigger their enabling; Confirming whether the expected working states of the plurality of power modules corresponding to the test stimulus are consistent with the actual working states of the plurality of power modules includes: Confirm whether the mapping relationship between the power module and the power-on signal that triggers the enabling of the power module is consistent with the mapping relationship between the power module and the power-on signal that is expected to trigger the enabling of the power module.

4. The method according to claim 1, wherein The method further includes a step of naming the power module, wherein the name of the power module includes hierarchical path information of the power module and instance name information of the power module.

5. The method according to claim 4, wherein Monitoring the enable signals of the plurality of power modules to determine actual working states of the plurality of power modules in different power-on time periods further includes: The number of power modules in the initial working state and the working state in different power-on time periods is counted.

6. The method according to claim 5, wherein Counting the total number of power modules in the initial working state and the working state in different power-on time periods includes: According to the instance name information in the name of the power module, the number of power modules in the initial working state and the working state in different power-on time periods is classified and counted.

7. The method according to claim 6, characterized in that The expected working states of the plurality of power modules corresponding to the test stimulus include the number of expected power modules in the initial working state and the working state in different power-on time periods, which is classified and counted according to the instance name information of the power modules; Confirming whether the expected working states of the plurality of power modules corresponding to the test stimulus are consistent with the actual working states of the plurality of power modules includes: Confirm whether the number of power modules with the same instance name information that are in the initial working state and the working state during each power-on period is consistent with the expected number of power modules.

8. The method according to claim 7, wherein Monitoring the enable signals of the plurality of power modules to determine actual working states of the plurality of power modules in different power-on time periods further includes: A report is generated, wherein the report includes the names of the multiple power modules, the actual working status of the multiple power modules in each power-on period, and the number of the power modules in the working status in each power-on period.

9. A device for detecting power-on timing, characterized in that: The device is applied to a semiconductor chip, which includes a power-on module, a combinational logic module, and a plurality of power modules; the power-on module is configured to sequentially generate power-on signals at different time points during the power-on process of the semiconductor chip, and the combinational logic module is configured to generate enable signals for the plurality of power modules based on the power-on signals; Wherein, the device comprises: a sending unit, configured to send a test stimulus to cause the semiconductor chip to enter a power-on process; A monitoring unit, configured to monitor the power-on signals sequentially sent by the power-on modules and divide the power-on time periods into different time periods according to the order in which the power-on signals are generated; The monitoring unit is further configured to monitor the enable signals of the plurality of power modules to determine the actual working states of the plurality of power modules in different power-on time periods; a confirmation unit, configured to confirm whether the expected working states of the plurality of power modules corresponding to the test stimulus are consistent with the actual working states of the plurality of power modules; The monitoring of the power-on signals sequentially issued by the power-on modules and the division of the different power-on time periods according to the order in which the power-on signals are generated include: Obtaining multiple time points when the power-on signals are generated, dividing the time period between any adjacent time point Ti when the i-th power-on signal is generated and the time point Ti+1 when the i+1-th power-on signal is generated as the i-th power-on period, where i is a positive integer greater than 0; The monitoring of the enable signals of the plurality of power modules to determine the actual working states of the plurality of power modules in different power-on time periods includes: When the enable signal of the power module is at an invalid level during the current power-on period, determining that the actual working state of the power module during the current power-on period is a non-working state; When the enable signal of the power module is converted from an invalid level to a valid level during the current power-on period, it is determined that the actual working state of the power module during the current power-on period is the starting working state; When the enable signal of the power module is at a continuously valid level during the current power-on period, determining that the actual working state of the power module during the current power-on period is a working state; When the enable signal of the power module is converted from an invalid level to a valid level and from a valid level to an invalid level during the current power-on period, it is determined that the actual working state of the power module during the current power-on period is a fault state.

10. A computer device, characterized in that: Includes processor, memory, input and output interfaces; The processor is connected to the memory and the input / output interface respectively, wherein the input / output interface is used to receive and output data, the memory is used to store a computer program, and the processor is used to call the computer program so that the computer device executes the method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which is suitable for being loaded and executed by a processor, so that a computer device having the processor executes the method according to any one of claims 1 to 8.

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