Static discharge inspection method, device and equipment for stacked chips and storage medium

Abstract

The embodiment of the invention discloses an electrostatic discharge inspection method and device for stacked chips, equipment and a storage medium, relates to the technical field of semiconductor circuits, and can save inspection time and computing resources so as to effectively improve inspection efficiency. The method comprises the steps that to-be-inspected discharge paths of stacked chips are divided into a first type of discharge paths and a second type of discharge paths, the first type of discharge paths represent electrostatic discharge paths coinciding with those in two-dimensional electrostatic discharge inspection, and the second type of discharge paths represent electrostatic discharge paths crossing core particles; performing two-dimensional electrostatic discharge inspection on each core particle forming the stacked chip so as to cover the first type of discharge path; and based on a shortest discharge path principle, screening out a target discharge path from the second type of discharge paths to perform electrostatic discharge inspection, wherein the target discharge path represents the shortest electrostatic discharge path in the electrostatic discharge paths crossing the core particles. The method and the device are suitable for electrostatic discharge inspection scenes of semiconductor chips.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a method, device, equipment, and storage medium for detecting electrostatic discharge of stacked chips. Background Art

[0002] With the rapid development of semiconductor technology, three-dimensional (3D) integrated chips, with their high-density interconnects and superior performance, have become a key area of ​​focus in advanced packaging. Furthermore, chip electrostatic discharge (ESD) testing is a critical technology for ensuring chip reliability, encompassing multiple stages including design, manufacturing, packaging, and testing. With advancements in process technology and the development of 3D integration, the challenges of ESD protection are increasing. In 3D integrated chips, ESD currents can potentially leak across die, making it more difficult to verify the integrity and functionality of ESD protection paths.

[0003] In existing technology, ESD testing for 3D integrated chips primarily relies on the same ESD testing methods used for 2D integrated chips. This involves traversing all possible ESD discharge paths and performing point-to-point (P2P) resistance checks to ensure that the resistance of metal connections meets process requirements, thereby ensuring effective ESD current discharge. However, directly applying the traversal testing method used for 2D integrated chips in 3D integrated chips requires analyzing both the ESD paths within the 2D core and the 3D paths across the cores. This results in a dramatic increase in the number of inspection paths and computational complexity, resulting in excessive inspection time, significant computational resource consumption, and the potential for the inspection program to fail to complete, severely impacting inspection efficiency. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a method, apparatus, device, and storage medium for electrostatic discharge inspection of stacked chips, which can save inspection time and computing resources, thereby effectively improving inspection efficiency.

[0005] In a first aspect, an embodiment of the present application provides an electrostatic discharge inspection method for stacked chips, comprising: dividing the discharge paths to be inspected of the stacked chip into a first type of discharge path and a second type of discharge path, wherein the first type of discharge path represents the electrostatic discharge path that overlaps with the two-dimensional electrostatic discharge inspection, and the second type of discharge path represents the electrostatic discharge path spanning between core particles; performing a two-dimensional electrostatic discharge inspection on each core particle constituting the stacked chip to cover the first type of discharge path; and, based on the shortest discharge path principle, screening out a target discharge path from the second type of discharge path for electrostatic discharge inspection; wherein the target discharge path represents the shortest electrostatic discharge path among the electrostatic discharge paths spanning between core particles.

[0006] According to a specific implementation method of an embodiment of the present application, the electrostatic discharge path that overlaps with the two-dimensional electrostatic discharge inspection includes: the electrostatic discharge path within the bottom core particle, and the electrostatic discharge path spanning between core particles includes: the electrostatic discharge path spanning at least two layers of core particles from the bottom core particle upward.

[0007] According to a specific implementation method of an embodiment of the present application, the two-dimensional electrostatic discharge inspection is performed on each core particle constituting the stacked chip, including: extracting metal connection relationship information and identifying the position and connection relationship of the electrostatic protection unit placed in the layout file based on the data information of each component core particle input, wherein the metal connection relationship information includes the power routing information and signal routing information between the metal layer of each component core particle, silicon through-hole structure, conductive bump, hybrid bonding structure and device; calculating the resistance of the first type of discharge path based on the metal connection relationship information and identifying the position and connection relationship of the electrostatic protection unit placed in the layout file; and determining whether it complies with the two-dimensional electrostatic discharge inspection design rules based on the resistance.

[0008] According to a specific implementation method of an embodiment of the present application, the calculation of the resistance of the first type of discharge path includes: calculating the resistance between each of the conductive bumps or hybrid bonding structures and each electrostatic protection unit connected to it; and calculating the resistance between each of the electrostatic protection units and each electrostatic protection unit connected to it; and calculating the resistance between each of the electrostatic protection units and each of the internal circuits of the core particles that constitute the stacked chip and have a direct connection with it.

[0009] According to a specific implementation method of an embodiment of the present application, determining whether it complies with the two-dimensional electrostatic discharge inspection design rules based on the resistance includes: comparing the resistance with the first design specification resistance; wherein the two-dimensional electrostatic discharge inspection design rules include the design specification resistance of the first type of discharge path; if the resistance is less than the design specification resistance of the first type of discharge path, determining that the electrostatic discharge inspection of the stacked chip complies with the two-dimensional electrostatic discharge inspection design rules; if the resistance is greater than the design specification resistance of the first type of discharge path, determining that the electrostatic discharge inspection of the stacked chip does not comply with the two-dimensional electrostatic discharge inspection design rules, and iteratively returning to modify the layout files of each component core particle of the stacked chip until the resistance of the first type of discharge path is less than the design specification resistance of the first type of discharge path.

[0010] According to a specific implementation method of an embodiment of the present application, based on the principle of the shortest discharge path, a target discharge path is screened out from the second type of discharge path for electrostatic discharge inspection, including: based on the principle of the shortest discharge path in which current preferentially flows through a low-resistance channel, the shortest current discharge path is screened out from the second type of discharge path as the target discharge path; the layout data and bonding information of each component core particle of the stacked chip are obtained, and the physical connection relationship between the hybrid bonding structure and the conductive bump, the network connection relationship between the discharge point and the hybrid bonding structure, and the network connection relationship between the hybrid bonding structure and the electrostatic protection unit are extracted from the layout data and bonding information; the first resistance between the hybrid bonding structure and the corresponding conductive bump is calculated; and the second resistance between the discharge point and the connected hybrid bonding structure is calculated; and the third resistance between the hybrid bonding structure and the electrostatic protection unit is calculated; based on the first resistance, the second resistance and the third resistance, it is determined whether the three-dimensional electrostatic discharge inspection design rules are met.

[0011] According to a specific implementation of an embodiment of the present application, determining whether a three-dimensional electrostatic discharge inspection design rule is met based on the first resistor, the second resistor, and the third resistor includes: adding the resistance between the conductive bump or hybrid bonding structure and each electrostatic protection unit connected thereto to the first resistor obtained by segmentation to obtain a first target discharge path resistance; or adding the second resistor obtained by segmentation to the third resistor to obtain a second target discharge path resistance; comparing the first target discharge path resistance or the second target discharge path resistance with a second design specification resistance; wherein the three-dimensional electrostatic discharge inspection design rule includes the design specification resistance of the target discharge path; if the first target discharge path resistance or the second target discharge path resistance is both less than the design specification resistance of the target discharge path, determining that the electrostatic discharge inspection of the stacked chip meets the three-dimensional electrostatic discharge inspection design rule; if the first target discharge path resistance or the second target discharge path resistance is greater than the design specification resistance of the target discharge path, determining that the electrostatic discharge inspection of the stacked chip does not meet the three-dimensional electrostatic discharge inspection design rule, and iteratively returning to modify the layout files of each component core of the stacked chip until the resistance of the second type of discharge path is less than the three-dimensional electrostatic discharge inspection design rule.

[0012] In the second aspect, an embodiment of the present application provides an electrostatic discharge inspection device for stacked chips, including: a path classification unit, used to divide the discharge paths to be inspected of the stacked chip into a first type of discharge path and a second type of discharge path, wherein the first type of discharge path represents the electrostatic discharge path that overlaps with the two-dimensional electrostatic discharge inspection, and the second type of discharge path represents the electrostatic discharge path spanning between core particles; an electrostatic discharge inspection unit, used to perform a two-dimensional electrostatic discharge inspection on each core particle constituting the stacked chip to cover the first type of discharge path; and, based on the shortest discharge path principle, screen out a target discharge path from the second type of discharge path for electrostatic discharge inspection; wherein the target discharge path represents the shortest electrostatic discharge path among the electrostatic discharge paths spanning between core particles.

[0013] According to a specific implementation method of an embodiment of the present application, the electrostatic discharge path that overlaps with the two-dimensional electrostatic discharge inspection includes: the electrostatic discharge path within the bottom core particle, and the electrostatic discharge path spanning between core particles includes: the electrostatic discharge path spanning at least two layers of core particles from the bottom core particle upward.

[0014] According to a specific implementation method of an embodiment of the present application, the electrostatic discharge inspection unit includes: a first extraction module, which is used to extract metal connection relationship information and identify the position and connection relationship of the electrostatic protection unit in the layout file based on the data information of each component core particle input, wherein the metal connection relationship information includes the power routing information and signal routing information between the metal layers of each component core particle, silicon through-hole structure, conductive bumps, hybrid bonding structure and devices; a first calculation module, which is used to calculate the resistance of the first type of discharge path based on the metal connection relationship information and the position and connection relationship of the electrostatic protection unit in the layout file; a first determination module, which is used to determine whether it complies with the two-dimensional electrostatic discharge inspection design rules based on the resistance.

[0015] According to a specific implementation method of an embodiment of the present application, the first calculation module includes: a calculation sub-module, used to calculate the resistance between each of the conductive bumps or hybrid bonding structures and each electrostatic protection unit connected to it; and, calculate the resistance between each of the electrostatic protection units and each of the electrostatic protection units connected to it; and, calculate the resistance between each of the electrostatic protection units and each of the internal circuits of the core particles that constitute the stacked chip and have a direct connection with it.

[0016] According to a specific implementation method of an embodiment of the present application, the first determination module includes: a first comparison submodule, used to compare the resistance with a first design specification resistance; wherein the two-dimensional electrostatic discharge inspection design rule includes the design specification resistance of the first type of discharge path; the first determination submodule, used to determine that the electrostatic discharge inspection of the stacked chip complies with the two-dimensional electrostatic discharge inspection design rule if the resistance is less than the design specification resistance of the first type of discharge path; the second determination submodule, used to determine that the electrostatic discharge inspection of the stacked chip does not comply with the two-dimensional electrostatic discharge inspection design rule if the resistance is greater than the design specification resistance of the first type of discharge path, and iteratively return to modify the layout file of each component core particle of the stacked chip until the resistance of the first type of discharge path is less than the design specification resistance of the first type of discharge path.

[0017] According to a specific implementation method of an embodiment of the present application, the electrostatic discharge inspection unit further includes: a screening module, which is used to screen out the shortest current discharge path from the second type of discharge path as the target discharge path based on the principle that current preferentially flows through the shortest discharge path of the low-resistance channel; a second extraction module, which is used to obtain the layout data and bonding information of the core particles of each component of the stacked chip, and extract the physical connection relationship between the hybrid bonding structure and the conductive bump, the network connection relationship between the discharge point and the hybrid bonding structure, and the network connection relationship between the hybrid bonding structure and the electrostatic protection unit from the layout data and bonding information; a second calculation module, which is used to calculate the first resistance between the hybrid bonding structure and the corresponding conductive bump; and, calculate the second resistance between the discharge point and the connected hybrid bonding structure; and, calculate the third resistance between the hybrid bonding structure and the electrostatic protection unit; a second determination module, which is used to determine whether it complies with the three-dimensional electrostatic discharge inspection design rules based on the first resistance, the second resistance and the third resistance.

[0018] According to a specific implementation of the embodiment of the present application, the second determination module includes: an addition submodule for adding the resistance between the conductive bump or hybrid bonding structure and each electrostatic protection unit connected thereto and the first resistance obtained by segmentation to obtain the first target discharge path resistance; or, adding the second resistance obtained by segmentation and a third resistance to obtain the second target discharge path resistance; a second comparison submodule for comparing the first target discharge path resistance or the second target discharge path resistance with the second design specification resistance; wherein the three-dimensional electrostatic discharge inspection design rule includes the design specification resistance of the target discharge path; The third determination submodule is used to determine that the electrostatic discharge inspection of the stacked chip complies with the three-dimensional electrostatic discharge inspection design rules if the first target discharge path resistance or the second target discharge path resistance is less than the design specification resistance of the target discharge path; the fourth determination submodule is used to determine that the electrostatic discharge inspection of the stacked chip does not comply with the three-dimensional electrostatic discharge inspection design rules if the first target discharge path resistance or the second target discharge path resistance is greater than the design specification resistance of the target discharge path, and iteratively return to modify the layout files of each component core particle of the stacked chip until the resistance of the second type of discharge path is less than the three-dimensional electrostatic discharge inspection design rules.

[0019] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; a power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, thereby realizing any of the electrostatic discharge inspection methods for stacked chips described in the first aspect.

[0020] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores one or more computer programs. When the one or more computer programs are executed by one or more processors, the electrostatic discharge inspection method for stacked chips described in any one of the first aspects is implemented.

[0021] The embodiment of the present application provides an electrostatic discharge inspection method, device, equipment and storage medium for stacked chips, which divides the discharge path to be inspected of the stacked chip into a first type of discharge path and a second type of discharge path, wherein the first type of discharge path represents the electrostatic discharge path that overlaps with the two-dimensional electrostatic discharge inspection, and the second type of discharge path represents the electrostatic discharge path that spans between core particles; performs a two-dimensional electrostatic discharge inspection on each core particle constituting the stacked chip to cover the first type of discharge path; and, based on the shortest discharge path principle, selects a target discharge path from the second type of discharge path for electrostatic discharge inspection; wherein the target discharge path represents the shortest electrostatic discharge path among the electrostatic discharge paths spanning between core particles. In this way, the discharge path to be inspected of the stacked chip is divided into a first type of discharge path and a second type of discharge path, and the two-dimensional electrostatic discharge inspection results are directly reused for the first type of discharge path, and the first type of discharge path is covered by the previous two-dimensional electrostatic point inspection of each core particle without repeated inspection; only the target discharge path in the second type of discharge path needs to be inspected, which avoids the redundant operation of full path scanning and simplifies the inspection path, can save inspection time and computing resources, and thus effectively improve inspection efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 A flow chart of an electrostatic discharge inspection method for stacked chips provided in an embodiment of the present application; Figure 2 A schematic diagram of the first type of discharge path in the stacked chips provided in an embodiment of the present application; Figure 3 A schematic diagram of the second type of discharge path in the stacked chips provided in an embodiment of the present application; Figure 4 Schematic diagram of ESD path classification of stacked chips provided in an embodiment of the present application; Figure 5 A two-dimensional electrostatic discharge inspection flow chart provided for an embodiment of the present application; Figure 6 A schematic diagram of a target discharge path structure provided in an embodiment of the present application; Figure 7 A flow chart of a resistance calculation method provided in an embodiment of the present application; Figure 8 A schematic diagram of another target discharge path structure provided in an embodiment of the present application; Figure 9 A flow chart of another resistance calculation method provided in an embodiment of the present application; Figure 10 A schematic structural diagram of an electrostatic discharge inspection device for stacked chips provided in an embodiment of the present application; Figure 11 A schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0025] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0026] In a first aspect, embodiments of the present application provide an electrostatic discharge inspection method for stacked chips, which can effectively improve verification efficiency and accuracy.

[0027] like Figure 1 As shown, an embodiment of the present application provides an electrostatic discharge inspection method for stacked chips, comprising: S11, dividing the discharge paths to be inspected of the stacked chips into a first type of discharge paths and a second type of discharge paths, wherein the first type of discharge paths represent electrostatic discharge paths that overlap with those in the two-dimensional electrostatic discharge inspection, and the second type of discharge paths represent electrostatic discharge paths that span between die; In 3D integrated chips, the ESD current discharge path is more complex than in traditional two-dimensional (2D) chips, involving both internal and inter-die paths. To improve inspection efficiency, this application divides the ESD discharge paths to be inspected into two categories: first-category discharge paths and second-category discharge paths.

[0028] The first type of discharge path characterization is the electrostatic discharge path that coincides with the two-dimensional electrostatic discharge inspection. Figure 2 This is a schematic diagram of the first type of discharge path in the stacked chips provided in the embodiment of the present application, see Figure 2 The first type of discharge path is a path where current flows only within the same die and does not involve cross-die interconnects. In some examples, this can be a path within a single die, from an input or output pad (I / O pad) through an ESD protection cell to power or ground. It can also be an ESD discharge path between ESD protection cells in the same power domain within the same die.

[0029] The second type of discharge path represents the electrostatic discharge path across the core particles. Figure 3 This is a schematic diagram of the second type of discharge path in the stacked chips provided in the embodiment of the present application, see Figure 3 The second type of discharge path involves an ESD discharge path that spans multiple die and relies on a 3D interconnect structure to form a complete path. In some cases, this type of discharge path can be a path from an internal discharge point on an upper die through an ESD cell or through-silicon via (TSV) to a conductive bump (power or ground) on a lower die. During ESD inspections, we can focus on analyzing the resistance, current carrying capacity, and layout rationality of cross-die interconnects, employing a path simplification strategy to avoid redundant calculations.

[0030] This path classification method improves inspection efficiency, separates 2D and 3D path inspections, reduces duplicate calculations, and accelerates the verification process. It also ensures comprehensiveness, covering both traditional 2D ESD protection requirements and optimizing cross-chip path analysis for 3D integration characteristics.

[0031] S12, performing a two-dimensional electrostatic discharge inspection on each core particle constituting the stacked chip to cover the first type of discharge path; and, based on the shortest discharge path principle, screening out a target discharge path from the second type of discharge path for electrostatic discharge inspection; wherein, the target discharge path represents the shortest electrostatic discharge path among the electrostatic discharge paths across the core particles.

[0032] After the ESD discharge paths to be inspected in the stacked chips are classified, an electrostatic discharge inspection is performed on the first type of discharge paths and the second type of discharge paths.

[0033] For the first type of discharge path, traditional 2D ESD inspection is performed independently within each die that makes up the stacked chip to verify the integrity of its internal ESD protection network. This inspection covers the connection between the die's internal I / O pads and the ESD protection unit, the discharge paths within each power domain within the same die (a power domain is a collection of circuit modules within a chip that share the same power supply network), and the compliance of metal wiring resistance with process rules. This ESD inspection for the first type of discharge path directly reuses established 2D inspection methods, avoiding duplication of development, eliminating cross-die path interference, and simplifying the inspection complexity of a single die.

[0034] For the second type of discharge path, the shortest electrostatic discharge path among the electrostatic discharge paths between the core particles is first screened out according to the shortest path principle, that is, the target discharge path. The shortest path is usually a high-risk path.

[0035] Then, the target discharge path is checked for electrostatic discharge, which reduces the number of paths to be checked and avoids the computational overhead of a full traversal, while focusing on high-risk paths to ensure the ESD reliability of critical interconnects.

[0036] The embodiment of the present application provides an electrostatic discharge inspection method for stacked chips, which divides the discharge paths to be inspected of the stacked chips into a first type of discharge path and a second type of discharge path, wherein the first type of discharge path represents the electrostatic discharge path that overlaps with the two-dimensional electrostatic discharge inspection, and the second type of discharge path represents the electrostatic discharge path that spans between core particles; performs a two-dimensional electrostatic discharge inspection on each core particle constituting the stacked chip to cover the first type of discharge path; and, based on the shortest discharge path principle, selects a target discharge path from the second type of discharge path for electrostatic discharge inspection; wherein the target discharge path represents the shortest electrostatic discharge path among the electrostatic discharge paths spanning between core particles. In this way, the discharge paths to be inspected of the stacked chips are divided into the first type of discharge path and the second type of discharge path, and the two-dimensional electrostatic discharge inspection results are directly reused for the first type of discharge path, and the first type of discharge path is covered by the previous two-dimensional electrostatic discharge inspection of each core particle without repeated inspection; only the target discharge path in the second type of discharge path needs to be inspected, which avoids the redundant operation of full path scanning and simplifies the inspection path, can save inspection time and computing resources, and thus effectively improve inspection efficiency.

[0037] In some embodiments, the electrostatic discharge path that overlaps with the two-dimensional electrostatic discharge inspection includes: an electrostatic discharge path within the bottom core particle, and the electrostatic discharge path that spans between core particles includes: an electrostatic discharge path that spans at least two layers of core particles from the bottom core particle upward.

[0038] In some examples, the ESD analysis of three-dimensional stacked chips includes two-dimensional ESD inspection of the core particles that make up the stacked chip and ESD inspection of the electrostatic discharge paths between the core particles. Therefore, the ESD discharge paths to be inspected in the stacked chip must first be classified. In this embodiment, when specifically classifying the ESD discharge paths to be inspected in the stacked chip, the analysis can be based on the characteristics that the first type of discharge path is generally an electrostatic discharge path within the bottom core particle, and the second type of discharge path is an electrostatic discharge path that vertically spans at least two layers of core particles from the bottom core particle upward. Among them, the first type of discharge path is a two-dimensional discharge path, and the second type of discharge path is a path for electrostatic discharge from one core particle to another in the three-dimensional stacked chip, which may propagate vertically or horizontally. In some examples, the second type of discharge path can be composed of multiple two-dimensional paths, i.e., local paths within each layer of core particles, spliced ​​together through vertical interconnection.

[0039] Since ESD testing includes two test models, the Human Body Model (HBM) and the Charged Device Model (CDM), the HBM model simulates the situation when a charged person touches a pin on a partially grounded device, transferring static charge from the person to the device and then discharging through the ground pin. The CDM simulates the situation when an integrated circuit is charged during manufacturing, transportation, and field use, and then self-discharges when it contacts the ground or other conductors. The specific classification process for the ESD discharge paths to be tested is as follows: In HBM mode, when current enters the stacked chip from the bottom chip, there are two scenarios. First, when the upper chip does not have an ESD protection unit, the ESD current can only be discharged through the ESD protection unit of the bottom chip. This discharge path does not involve the upper chip and occurs only in the bottom chip. This path overlaps with the path required for 2D ESD testing of the bottom chip alone. Therefore, the path in this case is a Type 1 discharge path. Second, when the upper chip has an ESD protection unit, the ESD current flows through bump 1 of the bottom chip. When traversing the path, the ESD protection unit connected to bump 1 in the upper chip is considered. At this time, two discharge paths need to be considered. One is to discharge only within the bottom core particle, which is consistent with the situation where the upper core particle has no ESD protection unit. The path in this case is the first type of discharge path; the other is to trigger the ESD protection unit in the upper core particle to complete the current discharge. The current enters the chip from bump 1 of the bottom core particle, flows into the upper core particle through TSV and hybrid bonding structure (Hybrid bonding), flows through the ESD protection unit with a connection relationship in the upper core particle, and then passes through the metal of the upper core particle to Hybrid bonding, flows into the bottom core particle through TSV, and flows out through bump 2 of the bottom core particle that is grounded. This ESD current flows through two core particles before completing the discharge. This path is the second type of discharge path. To facilitate the description of the overall solution of this application, this path is set as cross-core path 1. The subsequent settings are for this purpose and will not be repeated.

[0040] In CDM mode, ESD charge accumulates within the chip, and the discharge point is internal to the chip, which can be divided into four cases. In the first case, when there is no ESD protection unit inside the upper chip, and the discharge point is inside the upper chip, the ESD current in the upper chip flows through the metal of the upper chip to the hybrid bonding structure, flows through the TSV into the lower chip, and then flows through the ESD protection unit in the lower chip to the ground bump for discharge. This path belongs to the second type of discharge path, which is set as cross-chip path 2.

[0041] In the second case, when there is no ESD protection unit inside the upper core particle and the discharge point is inside the bottom core particle, the ESD current can only be discharged through the ESD protection unit of the bottom core particle. This discharge path does not involve the upper core particle and is only carried out in the bottom core particle. This path is the first type of discharge path.

[0042] In the third case, when an ESD protection unit is placed inside the upper-layer chip and the discharge point is within the upper-layer chip, the ESD protection unit in the lower-layer chip that is connected to the metal at the discharge location is considered when traversing the path. In this case, two discharge paths need to be considered. First, the ESD current flows through the ESD protection unit inside the upper-layer chip, through the metal of the upper-layer chip to the hybrid bonding, through the TSV into the lower-layer chip, and finally discharges through the ground bump of the lower-layer chip. This path belongs to the second type of discharge path and is set as cross-chip path 3. Second, the ESD current flows from the metal of the upper-layer chip to the hybrid bonding, through the TSV into the lower-layer chip, through the ESD protection unit in the lower-layer chip, and finally discharges through the ground bump. This path belongs to the second type of discharge path and is set as cross-chip path 4.

[0043] In the fourth case, when an ESD protection unit is placed inside the upper-layer core and the discharge point is inside the lower-layer core, the ESD protection unit in the upper-layer core connected to the metal at the discharge location is considered when traversing the path. In this case, two discharge paths need to be considered. First, the ESD current is discharged through the ESD protection unit of the lower-layer core to the ground bump. This path is the first type of discharge path. Second, the ESD current flows into the upper-layer core through TSV and hybrid bonding, passes through the ESD protection unit inside the upper-layer core, then through the metal of the upper-layer core to hybrid bonding, flows through TSV into the lower-layer core, and is discharged through the ground bump of the lower-layer core. This path belongs to the second type of discharge path, which is set as cross-core path 5.

[0044] Figure 4 The ESD path classification diagram of the stacked chips provided in the embodiment of the present application is as follows: Figure 4 Based on the above analysis, circle A represents the 2D ESD inspection traversal path for each component core, and circle B represents the ESD inspection traversal path for the stacked chip. The intersection of the two circles represents paths in the stacked chip ESD inspection traversal path that overlap with the 2D ESD inspection paths for each component core. These overlapping paths are first-class discharge paths and exist in the underlying core, totaling four types. The portion of circle B that does not intersect with circle A represents the cross-core 3D ESD discharge paths after 3D integration, i.e., second-class discharge paths, totaling five types. Circle c represents the paths that need to be inspected after the cross-core paths are streamlined and are included in circle B. In some cases, inspecting both A and c can improve efficiency while ensuring thorough inspection.

[0045] Figure 5 For the two-dimensional electrostatic discharge inspection flow chart provided in the embodiment of this application, see Figure 5 In some embodiments, performing a two-dimensional electrostatic discharge inspection on each die constituting the stacked chip includes: S21, inputting data information of each component core particle; When performing two-dimensional electrostatic discharge inspection on each core particle constituting the stacked chip, data input and information extraction are first performed. In some examples, the complete layout file of each component core particle, the metal layer or interconnection parameters provided by the process design kit, and the ESD design rule file can be input.

[0046] S22, extracting metal connection relationship information and identifying the location and connection relationship of the electrostatic protection unit in the layout file, wherein the metal connection relationship information includes power routing information and signal routing information between each component core metal layer, through silicon via structure, conductive bump, hybrid bonding structure and device; When extracting key information, metal connection relationships can be extracted and ESD protection units can be identified. In some examples, the routing topology of each metal layer, 3D interconnect structure, and power or ground network distribution can be extracted to obtain power and signal routing information between each component core metal layer, through-silicon via (TSV) structure, conductive bumps, hybrid bonding structure, and device. For 3D interconnect structures, the extracted information includes the coordinates and electrical parameters of the TSV structure, the layout and material resistance of the conductive bumps, and the interface characteristics of the hybrid bonding structure. For power or ground network distribution, the extracted information includes the connection of power rings and power bars, and the isolation of different voltage domains. When identifying the placement of ESD protection units in the layout file, all ESD devices are located and their connection relationships are analyzed, such as the input path from the I / O pad to the ESD unit and the discharge path from the ESD unit to the power domain network.

[0047] S23, calculating the resistance of the first type of discharge path according to the metal connection relationship information and the position and connection relationship of the electrostatic protection unit in the identification layout file; When calculating the resistance of the first type of discharge path, the calculation object is limited to the 2D path within the current chip. In some cases, the metal trace resistance, contact resistance, and ESD device on-resistance in the path can be calculated. The resistance of all metal segments, contact holes, and devices in the path are then summed to obtain the total resistance of the complete path.

[0048] S24 , determining whether the resistance complies with a two-dimensional electrostatic discharge inspection design rule based on the resistance.

[0049] Verify whether the total resistance meets the two-dimensional electrostatic discharge inspection design rules provided by the process factory. This process finely extracts the connection relationship between the metal and ESD units inside the core particle, combined with physical resistance calculation, to ensure that the 2D ESD protection network meets the reliability requirements, laying the foundation for subsequent cross-core path inspection.

[0050] See also Figure 5 In some embodiments, calculating the resistance of the first type of discharge path includes: S23a, calculating the resistance between each of the conductive bumps or hybrid bonding structures and each electrostatic protection unit connected thereto; Perform point-to-point resistance checks on all metal paths between conductive bumps or hybrid bonding structures and ESD cells directly connected to them ("they" refers to conductive bumps or hybrid bonding structures) to ensure that external ESD stress can be quickly introduced into the protection cells to avoid thermal damage near the bumps. Figure 2 For the path marked ①, calculate the resistance between each bump or hybrid bonding and each connected ESD protection unit. The bottom-layer core starts with the bump. Upper-layer cores have no bumps and must be calculated only from the hybrid bonding process.

[0051] S23b, and calculating the resistance between each of the electrostatic protection units and each of the electrostatic protection units connected thereto; Perform point-to-point resistance checks on the interconnection paths between multiple ESD protection units in the same power domain within the same die. For details, see Figure 2 In step ②, calculate the resistance between each ESD protection unit and each ESD protection unit connected to it.

[0052] S23c, and calculating the resistance between each of the electrostatic protection units and the internal circuit of each of the cores constituting the stacked chip that is directly connected thereto.

[0053] Perform point-to-point resistance checks on the metal connection paths from the ESD protection unit to the core circuits it protects ("it" refers to the ESD protection unit). Specifically, see Figure 2 For step ③, calculate the resistance between each ESD protection unit and each internal circuit of the chip that is directly connected to it.

[0054] This hierarchical resistance calculation method can accurately evaluate the ESD network reliability of the 2D portion of a 3D chip, providing baseline data for cross-chip path inspection.

[0055] See also Figure 5In some embodiments, determining whether the resistance complies with a two-dimensional electrostatic discharge inspection design rule based on the resistance includes: comparing the resistance with a first design specification resistance; wherein the two-dimensional electrostatic discharge inspection design rule includes a design specification resistance for a first type of discharge path; S24a, if the resistance is less than the design specification resistance of the first type of discharge path, determining that the electrostatic discharge inspection of the stacked chip complies with the two-dimensional electrostatic discharge inspection design rule; The 2D ESD check design rules include a design specification resistance for the first-type discharge path. This resistance is determined based on the process factory's basic rules and chip-level customization requirements. The calculated actual resistance of the first-type path is extracted and compared with the predefined design specification resistance. If the actual resistance is less than the design specification resistance of the first-type discharge path, the stacked chip ESD check is determined to comply with the 2D ESD check design rules, and the path passes the check.

[0056] S24b, if the resistance is greater than the design specification resistance of the first type of discharge path, it is determined that the electrostatic discharge inspection of the stacked chip does not comply with the two-dimensional electrostatic discharge inspection design rules, and iteratively returns to modify the layout files of each component core particle of the stacked chip until the resistance of the first type of discharge path is less than the design specification resistance of the first type of discharge path.

[0057] If the actual resistance of the first-type path exceeds the design specification resistance of the first-type discharge path, the stacked chip's ESD check is determined to not comply with the 2D ESD check design rules. For paths that do not comply with the rules, the tool iteratively returns to modify the layout file. In some cases, layout modifications can include metal routing optimization, contact structure enhancement, ESD cell layout adjustment, and process layer optimization. The tool automatically marks the offending paths and recommends modification solutions. After each iteration, the resistance is recalculated until the resistance of the second-type discharge path is less than the design specification resistance of the first-type discharge path. This ensures that all single-chip paths meet ESD discharge requirements. This rule-driven, automated iteration improves inspection efficiency.

[0058] In some embodiments, based on the principle of the shortest discharge path, a target discharge path is screened out from the second type of discharge path for electrostatic discharge inspection, including: based on the principle of the shortest discharge path in which current preferentially flows through a low-resistance channel, the shortest current discharge path is screened out from the second type of discharge path as the target discharge path; the layout data and bonding information of each component core particle of the stacked chip are obtained, and the physical connection relationship between the hybrid bonding structure and the conductive bump, the network connection relationship between the discharge point and the hybrid bonding structure, and the network connection relationship between the hybrid bonding structure and the electrostatic protection unit are extracted from the layout data and bonding information; the first resistance between the hybrid bonding structure and the corresponding conductive bump is calculated; and the second resistance between the discharge point and the connected hybrid bonding structure is calculated; and the third resistance between the hybrid bonding structure and the electrostatic protection unit is calculated; based on the first resistance, the second resistance and the third resistance, it is determined whether the three-dimensional electrostatic discharge inspection design rules are met.

[0059] The shortest current discharge path is selected from the second type of discharge path as the target discharge path. The shortest path is not the shortest geometric distance, but the complete discharge channel with the smallest resistance, which is dominated by the resistance of the cross-chip interconnect structure. The shortest path screening can ensure that the ESD current is quickly discharged through the low-resistance path, avoiding shunting to the high-resistance path and causing protection failure. At the same time, it reduces the number of paths to be checked and improves verification efficiency.

[0060] See also Figure 4 Among the five existing second-type discharge paths, only the cross-die discharge path that is the shortest path needs to be checked. Cross-die paths that are not the shortest discharge path do not need to be checked. In other words, screening out cross-die paths that are not the shortest discharge path does not affect the comprehensiveness of the stacked chip ESD inspection.

[0061] For example, in the shortest path screening process, for cross-die path 1, in HBM mode, current enters the chip from bump 1 on the bottom die, flows through TSVs and hybrid bonding to the upper die, passes through the connected ESD protection unit in the upper die, then passes through the metal of the upper die to hybrid bonding, flows through TSVs into the bottom die, and exits through bump 2 on the bottom die, which is connected to ground. This discharge point can be directly discharged through the ESD protection unit in the bottom die, providing a shorter discharge path. This cross-die path is not the shortest discharge path and does not need to be checked.

[0062] For cross-chip path 2, in CDM mode, the discharge point is inside the bottom chip. The ESD current flows through the TSV and hybrid bonding to the upper chip, passes through the ESD protection unit inside the upper chip, and then through the metal of the upper chip to the hybrid bonding. It flows through the TSV to the bottom chip, and is discharged through the ground bump of the bottom chip. This discharge point can be discharged directly through the ESD protection unit of the bottom chip, providing a shorter discharge path. This cross-chip path is not the shortest discharge path and does not need to be checked.

[0063] For cross-die path 3, in CDM mode, the discharge point is inside the upper die. The ESD current flows from the metal of the upper die to the hybrid bonding, then through the TSV into the lower die. It then flows through the ESD protection unit in the lower die and is discharged to the ground bump. This discharge point can be discharged directly through the ESD protection unit in the upper die, providing a shorter discharge path. This cross-die path is not the shortest discharge path and does not need to be checked.

[0064] For cross-chip path 4, in CDM mode, the discharge point is inside the upper chip. The ESD current flows through the ESD protection unit inside the upper chip, through the metal of the upper chip to the hybrid bonding, flows into the bottom chip through the TSV, and is discharged through the ground bump of the bottom chip. This path has no shorter alternative discharge path and needs to be checked.

[0065] For cross-chip path 5, in CDM mode, the discharge point is inside the upper chip. The ESD current in the upper chip flows through the metal of the upper chip to the hybrid bonding, flows through the TSV into the bottom chip, and then flows through the ESD protection unit in the bottom chip to the ground bump for complete discharge. This path has no shorter alternative discharge path and needs to be checked.

[0066] Through the above analysis, only cross-chip path 4 and cross-chip path 5 are target discharge paths that need to be checked.

[0067] Next, the core information is parsed from the layout and bonding data. In some examples, it is necessary to parse the physical connection relationship between the hybrid bonding structure and the conductive bumps, the network connection relationship between the discharge point and the hybrid bonding structure, and the network connection relationship between the hybrid bonding structure and the electrostatic protection unit.

[0068] Then, the resistance of the cross-chip path is calculated in sections, and the first resistance between the hybrid bonding structure and the corresponding conductive bump is calculated; the second resistance between the discharge point and the connected hybrid bonding structure is calculated; and the third resistance between the hybrid bonding structure and the electrostatic protection unit is calculated. For the resistance calculation process, the target discharge paths that need to be checked, cross-chip path 4 and cross-chip path 5, obtained from the above analysis, are taken as examples. Specifically, for cross-chip path 4, cross-chip path 4 is in CDM discharge mode, and the ESD protection unit is placed on the upper chip. Figure 6 A schematic diagram of a target discharge path structure provided in an embodiment of the present application is shown in FIG. Figure 6 The discharge point is inside the upper chip. The ESD current flows through the ESD protection unit inside the upper chip, the metal of the upper chip to the hybrid bonding, flows into the bottom chip through the TSV, and is discharged through the ground bump on the bottom chip. The P2P resistance we need to check for this cross-chip path has two sections. The first section corresponds to Figure 6 Mark ④ is the resistance between the discharge point of the upper core particle and the ESD protection unit inside the upper core particle. This resistance can be directly found in the 2D inspection results of the upper core particle, and the calculation method will not be introduced separately. Figure 6 The middle mark ⑤ is the resistance between the ESD protection unit inside the upper core particle and the bump of the bottom core particle. This resistance is the resistance across the core particles and needs to be calculated separately. The second resistance can be further divided into two sections, corresponding to Figure 6 For the resistors in sections ⑤-1 and ⑤-2, the resistor in section ⑤-1 is located in the upper core particle. The resistance to be calculated is the resistance between the hybrid bonding and each ESD protection unit connected to it. This resistance can be found directly in the 2D inspection results of the upper core particle. The resistor in section ⑤-2 is located in the lower core particle. The resistance to be calculated is the resistance between the hybrid bonding and the ground bump. Figure 7 The resistance calculation method flow chart provided in the embodiment of the present application is as follows: Figure 7First, clarify the connection relationship between hybrid bonding and bumps. Specifically, determine which hybrid bonding connects each bump to the upper-layer chip. Since the layout file for the lower-layer chip doesn't include hybrid bonding, it's impossible to locate the hybrid bonding locations of each bump in the layout file. Therefore, it's necessary to calculate a fixed correspondence between the coordinates of each hybrid bonding and the coordinates of the bump. This allows for resistance calculation based on the coordinates. Finally, add the resistance of segments ⑤-1 and ⑤-2 to obtain the resistance of segment ⑤. This completes the P2P resistance calculation for segments ④ and ⑤ in cross-chip path 4, which require inspection.

[0069] For cross-chip path 5, cross-chip path 5 is in CDM discharge mode, and no ESD protection unit is placed on the upper chip. Figure 8 Another target discharge path structure diagram provided in the embodiment of the present application is as follows: Figure 8 In the case where the discharge point is within the upper-layer chip, the ESD current in the upper-layer chip flows through the metal of the upper-layer chip to the hybrid bonding, then through the TSV into the lower-layer chip, and finally through the ESD protection unit within the lower-layer chip to the ground bump for discharge. The key to checking this discharge situation is to confirm whether the protection capability of the ESD protection unit in the lower-layer chip covers the upper-layer chip. The protection capability of the ESD protection unit in a power domain of the lower-layer chip must cover all internal discharge locations in that power domain of the upper-layer chip. However, if there are too many discharge points in a chip, calculating the path from each discharge point in each power domain of the upper-layer chip to the ESD protection unit in the lower-layer chip would result in excessive computational complexity. To ensure coverage, simply select the discharge point farthest from the ESD protection unit in each power domain of the upper-layer chip for ESD testing. If the farthest discharge point passes the test, the remaining closer discharge points will also pass the test. After selecting the discharge points to be calculated for each power domain, the P2P resistance test begins.

[0070] The P2P resistor that needs to be checked can be divided into two sections. The first section corresponds to Figure 8 Mark ⑥ is the resistance between the discharge point of the upper core particle and the ESD protection unit inside the bottom core particle. This resistance is the resistance across the core particles and needs to be calculated separately. The second section corresponds to Figure 11 The middle mark ⑦ is the resistance between the ESD protection unit and the bump inside the bottom core particle. This resistance can be found directly in the 2D inspection results of the upper core particle. For the resistance marked ⑥, split calculation is performed. Part of the section that needs to calculate the resistance is in the upper core particle, corresponding to Figure 8 In the section ⑥-1, part of the section that needs to calculate the resistance is in the bottom core particle, corresponding to Figure 8 Section ⑥-2 is marked in the middle. For the resistors in section ⑥-1, which are located in the upper core, the resistance to be calculated is the resistance between the farthest discharge point of each power domain and the hybrid bonding connected to it. For the resistors in section ⑥-2, which are located in the bottom core, the resistance to be calculated is the resistance between the hybrid bonding and the ESD protection unit placed in the bottom core. Figure 9 This is another resistance calculation method flow chart provided in the embodiment of the present application, the P2P resistance calculation method of sections ⑥-1 and ⑥-2 is as follows Figure 9 By inputting the bump and hybrid bonding information, the corresponding connection relationship between the discharge point, hybrid bonding, and ESD protection unit is clarified. Specifically, it is clear through which hybrid bonding each discharge point that needs to be checked flows into the underlying core particles, and which ESD protection units these hybrid bondings are connected to, so as to calculate the resistance between the discharge point and the hybrid bonding, and the resistance between these hybrid bondings and the ESD protection unit. Similarly, since the layout file of the underlying core particles does not contain hybrid bonding, it is impossible to directly locate the hybrid bonding position that needs to be calculated in the layout file of the underlying core particles. Therefore, it is necessary to calculate the fixed position correspondence between the coordinates of each hybrid bonding and the coordinates of the bump, map the hybrid bonding coordinates of the upper core particles to the underlying core particles, and then calculate the resistance based on the coordinate position.

[0071] Finally, the resistance of section ⑥-1 and section ⑥-2 are added together to obtain the resistance of the complete section ⑥. The P2P resistance calculation of sections ⑥ and ⑦ that need to be checked in cross-chip path 5 is completed.

[0072] Compare the resistance results calculated from the two cross-chip paths mentioned above with the design rules provided by the process factory to determine whether they meet the 3D ESD inspection design rules.

[0073] In some embodiments, determining whether a three-dimensional electrostatic discharge (ESD) inspection design rule is met based on the first resistor, the second resistor, and the third resistor includes: adding the resistance between the conductive bump or hybrid bonding structure and each electrostatic protection unit connected thereto to the first resistor obtained by segmentation to obtain a first target discharge path resistance; or adding the second resistor obtained by segmentation to the third resistor to obtain a second target discharge path resistance; and comparing the first target discharge path resistance or the second target discharge path resistance with a second design specification resistance. The three-dimensional ESD inspection design rule includes the design specification resistance of the target discharge path; if the first target discharge path resistance or the second target discharge path resistance is both less than the design specification resistance of the target discharge path, determining that the ESD inspection of the stacked chip meets the three-dimensional ESD inspection design rule; if the first target discharge path resistance or the second target discharge path resistance is greater than the design specification resistance of the target discharge path, determining that the ESD inspection of the stacked chip does not meet the three-dimensional ESD inspection design rule, and iteratively returning to modify the layout files of each component core of the stacked chip until the resistance of the second type of discharge path is less than the three-dimensional ESD inspection design rule.

[0074] By streamlining the cross-chip paths to obtain target discharge paths, such as cross-chip path 4 and cross-chip path 5, efficiency can be improved while ensuring sufficient inspection.

[0075] When calculating the resistance of two cross-chip paths, in some examples, a first resistance, a second resistance, and a third resistance are obtained. In the aforementioned two-dimensional ESD test, the resistance between the conductive bump or hybrid bonding structure and each ESD protection unit connected to it is calculated. The first resistance (such as the resistance of segment ⑤-2 in the aforementioned embodiment) and the resistance obtained in the two-dimensional ESD test (such as the resistance of segment ⑤-1 in the aforementioned embodiment) are added together to obtain the first target discharge path resistance. Alternatively, the second resistance (such as the resistance of segment ⑥-1 in the aforementioned embodiment) and the third resistance (such as the resistance of segment ⑥-2 in the aforementioned embodiment) obtained in the segmented manner are added together to obtain the second target discharge path resistance. The calculation process needs to consider the temperature coefficient of each resistance component and the impact of process fluctuations. The worst-case maximum value is generally used for accumulation. The second design specification resistance is generally determined based on the 3D integrated chip ESD design rules, chip architecture requirements, and reliability margin provided by the process manufacturer.

[0076] The calculated resistance of the first or second target discharge path is numerically compared with the second design specification resistance. If either the first or second target discharge path resistance is less than the second design specification resistance, the path is deemed to comply with the 3D ESD check design rules, and the difference between the actual resistance and the specification value is recorded. If either the first or second target discharge path resistance is greater than the second design specification resistance, the path is deemed to violate the design rules, and a detailed violation analysis report is generated, indicating the primary resistance contributions. For non-compliant paths, an automated optimization process is initiated to identify the primary resistance contributions and provide targeted modification suggestions based on the violation type. For example, for metal traces with excessive resistance, widening the trace or shortening its length is recommended; for interconnect structures with high resistance, increasing the number of TSVs or switching to a low-resistance bonding process is recommended; and for ESD cell performance issues, optimizing device size or changing the device type is recommended. A revised layout plan is then automatically generated, and the resistance values ​​are recalculated until the specification is met.

[0077] In some embodiments, the electrostatic discharge method for stacked chips provided in this application is applicable to 3D integrated chips and 3D packaged chips; in terms of chip structure, it is also applicable to the vertical stacking form of two or more chips with the front side facing the back side (F2B) and the vertical stacking form of two or more chips with the front side facing the front side (F2F).

[0078] In a second aspect, an embodiment of the present application provides an electrostatic discharge inspection device for stacked chips, which can save inspection time and computing resources, thereby effectively improving inspection efficiency.

[0079] like Figure 10 As shown, an embodiment of the present application further provides an electrostatic discharge inspection device for stacked chips, comprising: a path classification unit 31 for classifying the discharge paths to be inspected of the stacked chips into a first type of discharge paths and a second type of discharge paths, wherein the first type of discharge paths represent electrostatic discharge paths that overlap with those in the two-dimensional electrostatic discharge inspection, and the second type of discharge paths represent electrostatic discharge paths that span between die; The electrostatic discharge inspection unit 32 is used to perform two-dimensional electrostatic discharge inspection on each core particle constituting the stacked chip to cover the first type of discharge path; and based on the shortest discharge path principle, select a target discharge path from the second type of discharge path for electrostatic discharge inspection; wherein the target discharge path represents the shortest electrostatic discharge path among the electrostatic discharge paths across the core particles.

[0080] The embodiment of the present application provides an electrostatic discharge inspection device for stacked chips, which divides the discharge paths to be inspected of the stacked chips into a first type of discharge path and a second type of discharge path, wherein the first type of discharge path represents the electrostatic discharge path that overlaps with the two-dimensional electrostatic discharge inspection, and the second type of discharge path represents the electrostatic discharge path that spans between core particles; performs a two-dimensional electrostatic discharge inspection on each core particle constituting the stacked chip to cover the first type of discharge path; and, based on the shortest discharge path principle, selects a target discharge path from the second type of discharge path for electrostatic discharge inspection; wherein the target discharge path represents the shortest electrostatic discharge path among the electrostatic discharge paths spanning between core particles. In this way, the discharge paths to be inspected of the stacked chips are divided into the first type of discharge path and the second type of discharge path, and the two-dimensional electrostatic discharge inspection results are directly reused for the first type of discharge path, and the first type of discharge path is covered by the previous two-dimensional electrostatic point inspection of each core particle without repeated inspection; only the target discharge path in the second type of discharge path needs to be inspected, which avoids the redundant operation of full path scanning and simplifies the inspection path, can save inspection time and computing resources, and thus effectively improve inspection efficiency.

[0081] In some embodiments, the electrostatic discharge path that overlaps with the two-dimensional electrostatic discharge inspection includes: an electrostatic discharge path within the bottom core particle, and the electrostatic discharge path that spans between core particles includes: an electrostatic discharge path that spans at least two layers of core particles from the bottom core particle upward.

[0082] In some embodiments, the electrostatic discharge inspection unit includes: a first extraction module, which is used to extract metal connection relationship information and identify the position and connection relationship of the electrostatic protection unit in the layout file based on the input data information of each component core particle, wherein the metal connection relationship information includes the metal layer of each component core particle, silicon through-hole structure, conductive bump, hybrid bonding structure and power routing information and signal routing information between devices; a first calculation module, which is used to calculate the resistance of the first type of discharge path based on the metal connection relationship information and the position and connection relationship of the electrostatic protection unit in the layout file; a first determination module, which is used to determine whether it complies with the two-dimensional electrostatic discharge inspection design rules based on the resistance.

[0083] In some embodiments, the first calculation module includes: a calculation submodule for calculating the resistance between each of the conductive bumps or hybrid bonding structures and each electrostatic protection unit connected thereto; and, calculating the resistance between each of the electrostatic protection units and each of the electrostatic protection units connected thereto; and, calculating the resistance between each of the electrostatic protection units and each of the internal circuits of the core particles constituting the stacked chip that are directly connected thereto.

[0084] In some embodiments, the first determination module includes: a first comparison submodule, used to compare the resistance with a first design specification resistance; wherein the two-dimensional electrostatic discharge inspection design rule includes the design specification resistance of a first type of discharge path; the first determination submodule, used to determine that the electrostatic discharge inspection of the stacked chip complies with the two-dimensional electrostatic discharge inspection design rule if the resistance is less than the design specification resistance of the first type of discharge path; the second determination submodule, used to determine that the electrostatic discharge inspection of the stacked chip does not comply with the two-dimensional electrostatic discharge inspection design rule if the resistance is greater than the design specification resistance of the first type of discharge path, and iteratively return to modify the layout files of each component core particle of the stacked chip until the resistance of the first type of discharge path is less than the design specification resistance of the first type of discharge path.

[0085] In some embodiments, the electrostatic discharge inspection unit further includes: a screening module for screening out the shortest current discharge path from the second type of discharge path as the target discharge path based on the principle that current preferentially flows through the shortest discharge path of the low-resistance channel; a second extraction module for obtaining the layout data and bonding information of the core particles of each component of the stacked chip, and extracting the physical connection relationship between the hybrid bonding structure and the conductive bump, the network connection relationship between the discharge point and the hybrid bonding structure, and the network connection relationship between the hybrid bonding structure and the electrostatic protection unit from the layout data and bonding information; a second calculation module for calculating the first resistance between the hybrid bonding structure and the corresponding conductive bump; and calculating the second resistance between the discharge point and the connected hybrid bonding structure; and calculating the third resistance between the hybrid bonding structure and the electrostatic protection unit; a second determination module for determining whether it complies with the three-dimensional electrostatic discharge inspection design rules based on the first resistance, the second resistance and the third resistance.

[0086] In some embodiments, the second determination module includes: an accumulation submodule, which is used to accumulate the first resistance obtained by segmentation and the resistance between the conductive bump or hybrid bonding structure and each electrostatic protection unit connected thereto, and accumulate the second resistance and the third resistance obtained by segmentation to obtain the resistance of the target discharge path; a second comparison submodule, which is used to compare the resistance of the target discharge path with the second design specification resistance; wherein the three-dimensional electrostatic discharge inspection design rule includes the design specification resistance of the target discharge path; a third determination submodule, which is used to determine that the electrostatic discharge inspection of the stacked chip complies with the three-dimensional electrostatic discharge inspection design rule if the resistance of the target discharge path is less than the design specification resistance of the target discharge path; a fourth determination submodule, which is used to determine that the electrostatic discharge inspection of the stacked chip does not comply with the three-dimensional electrostatic discharge inspection design rule if the resistance is greater than the design specification resistance of the target discharge path, and iteratively return to modify the layout file of each component core of the stacked chip until the resistance of the second type of discharge path is less than the three-dimensional electrostatic discharge inspection design rule.

[0087] On the third aspect, the embodiments of the present application also provide an electronic device that can save inspection time and computing resources, thereby effectively improving inspection efficiency.

[0088] like Figure 11 As shown, the electronic device provided by the embodiment of the present application may include: a shell 51, a processor 52, a memory 53, a circuit board 54 and a power supply circuit 55, wherein the circuit board 54 is placed inside the space enclosed by the shell 51, and the processor 52 and the memory 53 are arranged on the circuit board 54; the power supply circuit 55 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 53 is used to store executable program code; the processor 52 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 53, so as to execute the electrostatic discharge inspection method of stacked chips provided in any of the aforementioned embodiments.

[0089] The specific execution process of the above steps by the processor 52 and the steps further executed by the processor 52 by running the executable program code can be found in the description of the above embodiment and will not be repeated here.

[0090] Fourthly, an embodiment of the present application also provides a computer-readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement any of the stacked chip electrostatic discharge inspection methods provided in the aforementioned embodiments, thereby also achieving the corresponding technical effects, which have been described in detail above and will not be repeated here.

[0091] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0092] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0093] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0094] For the convenience of description, the above device is described as being divided into various units / modules based on their functions. Of course, when implementing this application, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0095] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above-described method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0096] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A method for inspecting electrostatic discharge of stacked chips, characterized in that: include: Dividing the discharge paths to be inspected of the stacked chips into a first type of discharge paths and a second type of discharge paths, wherein the first type of discharge paths represent electrostatic discharge paths that overlap with those in the two-dimensional electrostatic discharge inspection, and the second type of discharge paths represent electrostatic discharge paths that span between die; performing a two-dimensional electrostatic discharge inspection on each die constituting the stacked chip to cover the first type of discharge path; and Based on the shortest discharge path principle, a target discharge path is selected from the second type of discharge paths for electrostatic discharge inspection; wherein the target discharge path represents the shortest electrostatic discharge path among the electrostatic discharge paths spanning between core particles.

2. The electrostatic discharge inspection method according to claim 1, wherein: The performing of a two-dimensional electrostatic discharge inspection on each die constituting the stacked chip includes: Extract metal connection relationship information and identify the location and connection relationship of ESD protection units in the layout file based on the input data information of each component core particle, wherein the metal connection relationship information includes the power routing information and signal routing information between the metal layers of each component core particle, through-silicon via structures, conductive bumps, hybrid bonding structures, and devices; Calculating the resistance of the first type of discharge path based on the metal connection relationship information and the position and connection relationship of the electrostatic protection unit in the identification layout file; According to the resistance, whether a two-dimensional electrostatic discharge inspection design rule is met is determined.

3. The electrostatic discharge inspection method according to claim 2, wherein: The calculating the resistance of the first type of discharge path includes: Calculating the resistance between each of the conductive bumps or hybrid bonding structures and each electrostatic protection unit connected thereto; and Calculating the resistance between each of the electrostatic protection units and each of the electrostatic protection units connected thereto; and The resistance between each electrostatic protection unit and the internal circuit of each chip forming the stacked chip that is directly connected to the electrostatic protection unit is calculated.

4. The electrostatic discharge inspection method according to claim 2 or 3, characterized in that: Determining whether the resistance complies with a two-dimensional electrostatic discharge inspection design rule includes: Comparing the resistance with a first design specification resistance; wherein the two-dimensional electrostatic discharge inspection design rule includes a design specification resistance of a first type of discharge path; If the resistance is less than the design specification resistance of the first type of discharge path, determining that the electrostatic discharge inspection of the stacked chip complies with the two-dimensional electrostatic discharge inspection design rule; If the resistance is greater than the design specification resistance of the first type of discharge path, it is determined that the electrostatic discharge inspection of the stacked chip does not comply with the two-dimensional electrostatic discharge inspection design rules, and the layout files of each component core of the stacked chip are modified iteratively until the resistance of the first type of discharge path is less than the design specification resistance of the first type of discharge path.

5. The electrostatic discharge inspection method according to claim 1, wherein: The method of screening a target discharge path from the second type of discharge paths for electrostatic discharge inspection based on the shortest discharge path principle includes: Based on the principle that current preferentially flows through the shortest discharge path of the low-resistance channel, the shortest current discharge path is selected from the second type of discharge paths as the target discharge path; Obtaining layout data and bonding information of each component core particle of the stacked chip, and extracting the physical connection relationship between the hybrid bonding structure and the conductive bump, the network connection relationship between the discharge point and the hybrid bonding structure, and the network connection relationship between the hybrid bonding structure and the electrostatic protection unit from the layout data and bonding information; Calculating a first resistance between the hybrid bonding structure and the corresponding conductive bump; and calculating a second resistance between the discharge point and the connected hybrid bonding structure; and calculating a third resistance between the hybrid bonding structure and the electrostatic protection unit; Whether the three-dimensional electrostatic discharge inspection design rule is met is determined according to the first resistor, the second resistor and the third resistor.

6. The electrostatic discharge inspection method according to claim 3 or 5, characterized in that: The determining whether the three-dimensional electrostatic discharge inspection design rule is met based on the first resistor, the second resistor, and the third resistor includes: The resistance between the conductive bump or hybrid bonding structure and each electrostatic protection unit connected thereto is added to the first resistance obtained by segmentation to obtain a first target discharge path resistance; Alternatively, the second resistance and the third resistance obtained by segmentation are added to obtain a second target discharge path resistance; comparing the first target discharge path resistance or the second target discharge path resistance with a second design specification resistance; wherein the 3D electrostatic discharge inspection design rule includes the design specification resistance of the target discharge path; If the first target discharge path resistance or the second target discharge path resistance is both less than the design specification resistance of the target discharge path, determining that the electrostatic discharge inspection of the stacked chip complies with the three-dimensional electrostatic discharge inspection design rule; If the resistance of the first target discharge path or the resistance of the second target discharge path is greater than the design specification resistance of the target discharge path, it is determined that the electrostatic discharge inspection of the stacked chip does not comply with the three-dimensional electrostatic discharge inspection design rules, and the layout files of each component core particle of the stacked chip are iteratively returned to modify until the resistance of the second type of discharge path is less than the three-dimensional electrostatic discharge inspection design rules.

7. An electrostatic discharge inspection device for stacked chips, characterized in that: include: a path classification unit, configured to classify the discharge paths to be inspected of the stacked chips into a first type of discharge paths and a second type of discharge paths, wherein the first type of discharge paths represent electrostatic discharge paths that overlap with those in the two-dimensional electrostatic discharge inspection, and the second type of discharge paths represent electrostatic discharge paths that span between die; An electrostatic discharge inspection unit is used to perform two-dimensional electrostatic discharge inspection on each core particle constituting the stacked chip to cover the first type of discharge path; and based on the shortest discharge path principle, select a target discharge path from the second type of discharge path for electrostatic discharge inspection; wherein, the target discharge path represents the shortest electrostatic discharge path among the electrostatic discharge paths across the core particles.

8. The electrostatic discharge inspection method according to claim 7, wherein: The electrostatic discharge inspection unit includes: A first extraction module is configured to extract metal connection relationship information and identify the location and connection relationship of the electrostatic protection unit in the layout file based on the input data information of each component core particle, wherein the metal connection relationship information includes the power routing information and signal routing information between the metal layer of each component core particle, the through-silicon via structure, the conductive bump, the hybrid bonding structure, and the device; The first calculation module is used to calculate the resistance of the first type of discharge path based on the metal connection relationship information and the position and connection relationship of the electrostatic protection unit placed in the identification layout file; the first determination module is used to determine whether it complies with the two-dimensional electrostatic discharge inspection design rules based on the resistance.

9. An electronic device, characterized in that: The electronic device includes: a shell, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the shell, and the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs the program corresponding to the executable program code by reading the executable program code stored in the memory, and is used to execute the electrostatic discharge inspection method of stacked chips described in any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the electrostatic discharge inspection method for stacked chips according to any one of claims 1 to 6.

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