Data writing method based on SPI communication, electronic terminal and storage medium

Abstract

The application discloses a data writing method based on SPI communication, an electronic terminal and a storage medium. The method comprises the following steps: receiving current preset byte data transmitted by a host through an SPI interface; judging whether the write enable of a FIFO memory is valid based on a data receiving flag corresponding to the current preset byte data and a non-empty flag of the FIFO memory; and if the write enable of the FIFO memory is valid, writing the current preset byte data into the FIFO memory. In the foregoing manner, the application can effectively reduce the loss of data that cannot be correctly written during transmission, thereby improving the reliability of the communication system.

Description

Technical Field

[0001] This application relates to the field of master-slave device communication technology, and in particular to a data writing method, electronic terminal and storage medium based on SPI communication. Background Technology

[0002] Serial Peripheral (SPI) is a 4-wire high-speed, high-efficiency serial interface technology with the advantages of being simple and easy to use. Therefore, it has been widely used in the field of communication, and more and more chips have integrated this communication protocol.

[0003] During SPI communication, due to the difference in communication clock frequency and pin transmission delay between the master and slave, data may be lost during transmission because it is not written correctly into the FIFO, thus affecting the communication quality between the master and slave. Summary of the Invention

[0004] The main technical problem addressed in this application is to provide a data writing method, electronic terminal, and storage medium based on SPI communication, which can effectively reduce data loss due to incorrect writing during transmission, thereby improving the reliability of the communication system.

[0005] To address the aforementioned technical problems, the first technical solution adopted in this application is to provide a data writing method based on SPI communication. This method includes: receiving current preset byte data transmitted by the host via the SPI interface; determining whether the write enable of the FIFO memory is valid based on the data receive flag corresponding to the current preset byte data and the non-empty flag of the FIFO memory; and if the write enable of the FIFO memory is valid, writing the current preset byte data into the FIFO memory.

[0006] To solve the aforementioned technical problems, the second technical solution adopted in this application is to provide an electronic terminal. This electronic terminal includes a processor, an SPI interface coupled to the processor, a memory coupled to the processor, and a FIFO memory coupled to the processor. The memory stores a computer program, and the processor executes the computer program to implement the data writing method of the first technical solution.

[0007] To address the aforementioned technical problems, the third technical solution adopted in this application is to provide a computer-readable storage medium. This computer-readable storage medium stores a computer program that can be executed by a processor to implement the data writing method of the first technical solution.

[0008] The beneficial effects of this application are as follows: Unlike the prior art, this application can comprehensively determine whether the write enable of the FIFO memory is valid by setting two conditions: the data receiving flag and the non-empty flag of the FIFO memory. This can improve the accuracy of the write enable judgment of the FIFO memory, reduce the situation of data writing failure due to incorrect write enable judgment, and effectively correspond to more scenarios in the data transmission process by combining the above two conditions. This allows for optimization of the write enable judgment for different scenarios, thereby effectively reducing the loss of data due to incorrect writing during the transmission of data between the master and slave through the SPI interface, and thus improving the reliability and robustness of the communication system. Attached Figure Description

[0009] Figure 1 This is a schematic block diagram of the structure of an embodiment of the communication system of this application;

[0010] Figure 2 This is a flowchart illustrating an embodiment of the data writing method based on SPI communication in this application;

[0011] Figure 3 This is a flowchart illustrating another embodiment of the data writing method based on SPI communication in this application;

[0012] Figure 4 This is a schematic block diagram of the structure of the electronic terminal embodiment of this application;

[0013] Figure 5 This is a schematic block diagram of the structure of an embodiment of a computer-readable storage medium according to this application. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0015] During SPI communication, due to the difference in communication clock frequency and pin transmission delay between the master and slave devices, data is easily lost during transmission because it may not be correctly written to the FIFO (First In First Out) memory. If one or more data items are lost during transmission, the entire transmitted data may be corrupted. Cyclic Redundancy Check (CRC) is a method used to detect and verify potential errors in transmitted or stored data during communication. If data loss leads to corrupted data, redundancy check errors may occur in the data transmitted between the master and slave devices, affecting communication quality. To improve or solve the above technical problems, this application proposes at least the following embodiments.

[0016] like Figure 1 As shown, the communication system 100 described in the real-time example of this application includes a master 101 and a slave 102. The master 101 and slave 102 are connected via an SPI interface. Optionally, the master 101 and slave 102 can be devices or modules, etc. The SPI interface is a 4-wire high-speed, high-efficiency serial interface technology. The four wires connecting the master 101 and slave 102 are the serial clock signal (SCK), the master output / slave input signal (MOSI), the master input / slave output signal (MISO), and the slave select signal (NSS). SCK is generated by the master 101 and then sent to the slave 102. MOSI is used as a master output / slave input pin, used by the master 101 to send data in master mode and receive data in slave mode. MISO is used as a master input / slave output pin, used by the master 101 to send data in slave mode and receive data in master mode. The NSS, controlled by the master 101, acts as a "chip select pin," selecting a specific slave 102 to allow the master 101 to communicate independently with the slave device, avoiding data line conflicts. The SPI interface primarily operates in a master-slave mode, typically consisting of one master 101 and one or more slave 102s. The master 101 selects a slave 102 for synchronous communication, thus completing data exchange. Communication between the master 101 and the slave 102 can be bidirectional or unidirectional.

[0017] like Figure 2 As shown, this embodiment of the data writing method based on SPI communication includes at least the following steps:

[0018] S100: Receives the current preset byte data transmitted by the host via the SPI interface.

[0019] In SPI communication, the master and slave devices can transfer data to each other. For example, the master can unidirectionally transfer data to the slave; specifically, the master can send data to the slave, and the slave can receive data sent by the master. Optionally, the master first sends data to the FIFO memory in the slave, then reads the data from the FIFO memory and transfers it to the main memory. Because the master and slave have two clocks, metastability can easily occur when data signals are transmitted between these two clock domains. Using a FIFO memory allows data to be written in the transmitting clock domain and read out in the receiving clock domain, effectively reducing metastability and enabling data transmission across clock domains. Optionally, the FIFO memory can be synchronous or asynchronous. Each data transmission transfers a preset byte of data to the FIFO memory. The preset byte of data can be 1 byte, 2 bytes, or even more bytes. Of course, the preset byte of data can also be one bit, two bits, or even more bits. Optionally, the current preset byte of data can be received by a memory buffer.

[0020] S200: Determine whether the write enable of the FIFO memory is valid based on the data receive flag corresponding to the current preset byte data and the non-empty flag of the FIFO memory.

[0021] After receiving the current preset byte of data, writing it into the FIFO memory requires the FIFO memory's write enable to be active. Therefore, after data transmission, it's necessary to first check if the FIFO memory's write enable is active. Write enable indicates that writing is possible; a valid write enable for the FIFO memory means data can be written to it. Thus, by checking if the FIFO memory's write enable is active, it's possible to determine if the FIFO memory can be written to the current preset byte of data. Checking the FIFO memory's write enable can include, for example, determining whether the current preset byte of data was successfully received, or checking the FIFO memory's storage status. Specifically, when checking whether the current preset byte of data was successfully received, the result can be mapped to the data reception flag; when checking the FIFO memory's storage space, the result can be mapped to the FIFO memory's non-empty flag. By checking both the data reception flag and the FIFO memory's non-empty flag, it's possible to determine if the FIFO memory's write enable is active.

[0022] S300: If the write enable of the FIFO memory is valid, the current preset byte data is written to the FIFO memory.

[0023] When the write enable of the FIFO memory is determined to be valid, it can be assumed that the current preset byte data can be written into the FIFO memory, and thus a write operation can be performed.

[0024] The write enable of the FIFO memory is determined by setting two conditions: a preset byte data receive flag and a non-empty flag. Only when both conditions are met can the write enable be considered valid, allowing data to be written. This effectively addresses a wider range of data transmission scenarios, increasing the accuracy of the determination and reducing data loss due to incorrect writing during transmission, thereby improving the reliability of the communication system.

[0025] like Figure 3 As shown, the method of determining whether the write enable of the FIFO is valid by judging the data receive flag bit and the non-empty flag bit of the FIFO memory, that is, step S200 may include at least the following steps:

[0026] S210: Determine whether the data reception flag is the first flag.

[0027] The data reception flag indicates the reception status of the current preset byte of data. By checking the data reception flag, it can be determined whether the current preset byte of data has been successfully received. Before making this determination, it should be clear that 1 and 0 of the flag are two relative states, and the specific states corresponding to 1 and 0 can be set to different values ​​depending on the situation. For example, 1 corresponds to successful reception of the current preset byte of data, and 0 corresponds to unsuccessful reception. The first flag is used to indicate that data reception is complete, and can be set to 1, for example. Therefore, by checking whether the data reception flag is 1, it can be determined whether the current preset byte of data has been successfully received.

[0028] The data reception flag is controlled by detecting whether the current preset byte of data has been successfully received. A state machine, for example, can be used for this detection. When the corresponding storage location is detected as having successfully received the current preset byte of data (i.e., the current preset byte of data is stored), for example, when the state machine detects that the current preset byte of data has been successfully received in the memory buffer, the data reception flag is set to 1, indicating that the data has been successfully received without loss. When the corresponding storage location is detected as not having successfully received the current preset byte of data (i.e., the current preset byte of data is not stored), for example, when the state machine detects that the current preset byte of data has not been received in the memory buffer, the data reception flag is set to 0, indicating that the data has not been successfully received, there may have been loss, or the data may not have been transmitted from the host yet. Therefore, when the data reception flag is determined to be 1 (i.e., the data reception flag is the first flag), it can be considered that the current preset byte of data has been successfully received. When the data reception flag is determined to be 0 (i.e., the data reception flag is not the first flag), it can be considered that the current preset byte of data has not been successfully received. By determining whether the data reception flag is the first flag, the actual situation of whether the current preset byte of data has been successfully received can be effectively understood.

[0029] The data reception flag can be used to reflect the reception status of the current preset byte data. The method of controlling the data reception flag can be, for example, signal control. That is, step S210 may include at least the following steps:

[0030] S211: Determine the signal status of the set input signal and the clear input signal.

[0031] The data receive flag is controlled by input signals, such as a set input signal, or a combination of a set input signal and a clear input signal. The set input signal indicates that the data receive flag should be set to 1, and the clear input signal indicates that the data receive flag should be set to 0. The data receive flag can be controlled by adjusting the signal states of the set and clear input signals. Therefore, the data receive flag can be determined by determining the signal states of the set and clear input signals.

[0032] S212: Configure the set input signal as a high-level signal and the clear input signal as a low-level signal in the first clock domain.

[0033] In data transmission, signal states, such as level signals, can be used to represent logic 1 and logic 0. For example, a high-level signal can represent logic 1, and a low-level signal can represent logic 0. The set input signal is configured as a high-level signal by setting it to 1 to indicate that the data receive flag is set to 1. Similarly, the clear input signal is configured as a high-level signal by setting it to 1 to indicate that the data receive flag is set to 0. When the current preset byte of data is successfully received, the data receive flag should be set to 1. After this determination, the set input signal is set to 1 in the first clock domain, which corresponds to configuring the set input signal as a high-level signal in the first clock domain. At this time, the clear input signal is not controlled, so it remains low. Here, the first clock is the interface clock.

[0034] S213: If the set input signal is a high-level signal and the clear input signal is a low-level signal, the data receiving flag is determined to be the first flag.

[0035] When detecting signal status, such as level signal, if the set input signal is detected to be high and the clear input signal is detected to be low, the set input signal is set to 1 and the clear input signal is set to 0. At this time, it can be determined that the data receiving flag is the first flag, that is, the data receiving flag is determined to be 1.

[0036] By setting the set input signal and the clear input signal, the data reception flag can be controlled according to the actual data reception situation, so that users can understand the data reception status in real time and solve problems such as abnormalities that occur during transmission in a timely manner.

[0037] S214: Use the data receive flag bit in the second clock domain to determine whether the data receive flag bit is the first flag bit.

[0038] After determining that the data receive flag is 1, it must be synchronized to the second clock domain for use. The second clock domain differs from the first clock domain; the second clock is the master clock. Within the second clock domain, the success of receiving the current preset byte of data is determined by checking whether the data receive flag is the same as the first flag (i.e., whether the data receive flag is 1). If the data receive flag is 1 within the second clock domain, it can be assumed that the current preset byte of data has been successfully received, meaning the data is ready to be written into the FIFO memory, thus satisfying one of the conditions for valid write enable.

[0039] Another condition for determining whether the write enable of the FIFO memory is valid is to check the non-empty flag bit, that is, step S200 may include at least the following steps:

[0040] S220: Determine whether the non-empty flag is the second flag.

[0041] Checking the non-empty flag can be considered as determining the current storage status of the FIFO memory. The non-empty flag indicates that the FIFO memory is currently in a non-empty state. For example, 1 corresponds to a non-empty state, and 0 corresponds to an empty state. The second flag is used to indicate that the FIFO memory is in a non-empty state. For example, it can be 1. Therefore, by checking whether the non-empty flag is 1, the current storage status of the FIFO memory and whether the previous preset byte of data was successfully received can be determined.

[0042] The non-empty flag is controlled by detecting the presence of data in the FIFO memory. This detection can be achieved, for example, by a state machine. When data is detected in the FIFO memory, the data receive flag is set to 1, indicating that the FIFO memory is not empty. When no data is detected in the FIFO memory, the data receive flag is set to 0, indicating that the FIFO memory is empty. Therefore, when the non-empty flag is determined to be 1 (i.e., the non-empty flag is the second flag), it can be assumed that data exists in the FIFO memory. When the non-empty flag is determined to be 0 (i.e., the data receive flag is not the second flag), it can be assumed that no data exists in the FIFO memory.

[0043] Checking the non-empty flag can also be considered as checking whether the previous preset byte of data was successfully received. When the non-empty flag is 0, meaning the FIFO memory is empty, the FIFO memory may be either write-empty or read-empty. Write-empty indicates that the previously transmitted preset byte of data was not successfully transmitted to the FIFO memory, while read-empty indicates that the currently transmitted preset byte of data has been read out of the FIFO memory. Since it is impossible to pinpoint which specific scenario the FIFO memory is in, it cannot be determined whether the previous preset byte of data was successfully transmitted to the FIFO. Conversely, when the non-empty flag is 1, meaning the data reception flag is the second flag, it can be considered that the previous preset byte of data was successfully received in the FIFO memory. Therefore, the process from receiving the preset byte of data to writing it into the FIFO memory is normal, and the transmission of the current preset byte of data can proceed.

[0044] For data to be written into the FIFO memory, the FIFO memory must not be full. Therefore, the non-empty flag corresponding to the full state of the FIFO memory can be set to 0 to avoid incorrect judgment. Optionally, the status flag indicating the current storage status of the FIFO memory can also be the FIFO's full flag. When the storage space of the FIFO is the same as the amount of data being transmitted, that is, each time a preset number of bytes of data is written, the FIFO will be full, i.e., the FIFO's full flag will be set to 1. Therefore, by checking whether the FIFO's full flag is 1, it can be determined whether the FIFO has successfully transferred data into the FIFO.

[0045] By setting the non-empty flag of the FIFO memory, the current storage status of the FIFO memory can be indicated. If it is the second flag, i.e., 1, it can be assumed that the FIFO memory stores the preset byte data of the previous transmission. Therefore, the transmission process is not a problem, and the current preset byte data can be transmitted. Thus, another condition for determining that the write enable is valid is met.

[0046] S230: If the data receive flag is the first flag and the non-empty flag is the second flag, then the write enable of the FIFO memory is determined to be valid.

[0047] When the data receive flag and the non-empty flag are both true (first and second flags respectively), it can be assumed that the current preset byte data can be written into the FIFO memory. For example, when both the data receive flag and the non-empty flag are 1, it proves that the data previously written to the FIFO memory has been successfully written and is about to be read out, and the transmission process is normal. The current preset byte data has also been received and is ready for transmission. Therefore, it can be determined that the write enable of the FIFO memory is valid, and a write operation can be performed.

[0048] After determining that the write enable is valid, the current preset byte data can be written into the FIFO memory to complete the transmission of the current preset byte data. Step S300 includes at least the following steps:

[0049] S310: After reading the previous preset byte data from the FIFO memory, write the current preset byte data into the FIFO memory.

[0050] Because FIFO memory can transmit data across clock domains, data written to the FIFO memory in the transmitting clock domain can be read out in the receiving clock domain. For example, if the FIFO memory's storage space corresponds to storing a preset byte of data, each time the current preset byte of data is written to the FIFO memory, it is read out of the FIFO memory; that is, the FIFO memory returns to an empty state after each data transmission. When the previous preset byte of data in the FIFO memory is read out and the FIFO memory returns to an empty state, the current preset byte of data is written to the FIFO memory. Of course, the FIFO memory can also store multiple preset bytes of data. Before writing the current preset byte of data to the FIFO memory, the oldest preset byte of data currently stored in the FIFO memory can be read out first, and then the current preset byte of data can be written to the FIFO memory, achieving first-in, first-out (FIFO).

[0051] S320: Triggers write enable on clock edge to write the current preset byte data to FIFO memory.

[0052] All state changes occur at the moment the clock edge arrives. Therefore, to write data into the FIFO memory, the write enable must be valid and the FIFO must not be full when the clock edge arrives. The write enable can be triggered at the clock edge when both conditions are met: the write enable is valid and the FIFO is not full. Optionally, the clock edge that triggers the write enable can be a rising edge, a falling edge, or both.

[0053] S330: Synchronizes the data receive flag to the first clock domain and configures the clear input signal to a high level within the first clock domain.

[0054] After the data receive flag is used up in the second clock domain, i.e., after the write enable is confirmed, the current preset byte data will be written into the FIFO memory when the clock edge arrives. Afterwards, for example, when the memory buffer returns to an empty state, the data receive flag needs to be set to 0, i.e., the data receive flag needs to be synchronized to the first clock domain to configure the clear input signal to a high level. Since the set input signal is not controlled, and the set input signal cannot remain high for an extended period, there may be two scenarios: the set input signal is either high or low. The set input signal and the clear input signal control the data receive flag through flip-flops, such as reset-priority flip-flops and set-priority flip-flops. When the flip-flop is a reset-priority flip-flop, the clear input signal has higher priority than the set input signal. That is, when the clear input signal is high, regardless of whether the set input signal is high or low, the data receive flag is determined not to be the first flag, i.e., the data receive flag is always 0.

[0055] The time difference T3 between configuring the clear input signal to a high level and configuring the set input signal to a high level is set to T3+T4>k*(mT1+nT2), where T1 is the master and slave clock cycle, T2 is the slave bus clock cycle, and T4 is the reception time of the current preset byte data; T3+T4=j*T1, where T3+T4 is the time required to receive the current preset byte data; k, m, n, and j are all positive integers. The slave device's processing time for one frame of data is T1+T2. If the time for each transmission of the preset byte data is less than the time required for the corresponding slave device to process and transmit the preset byte data, the current frame of data may not be fully transmitted before the next frame begins, resulting in data loss. Therefore, ensuring that T3+T4 meets the above condition ensures complete data transmission and reduces the possibility of data loss.

[0056] like Figure 4 As shown in the embodiment of the electronic terminal described in this application, the electronic terminal 110 includes: a processor 111, an SPI interface 112, a memory 113, and a FIFO memory 114. The SPI interface 112, the memory 113, and the FIFO memory 114 are respectively coupled to the processor 111.

[0057] Processor 111 is used to execute computer programs. Processor 111 can also be called a CPU (Central Processing Unit). Processor 111 may be an integrated circuit chip with signal processing capabilities. Processor 111 can also be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. The general-purpose processor can be a microprocessor (MCU), or processor 111 can be any conventional processor.

[0058] The processor 111 is used to execute the computer program stored in the memory 113 to implement the data writing method described in the embodiment of the data writing method based on SPI communication of this application.

[0059] The SPI interface 112 is a 4-wire, high-speed, high-efficiency serial interface technology. The SPI interface 112 primarily operates in a master-slave mode, therefore it typically consists of one master and one or more slave devices. The master selects a slave device for synchronous communication to complete data exchange. Communication between the master and slave devices can be bidirectional or unidirectional. Optionally, the master and slave devices can be devices, modules, etc.

[0060] The memory 113 stores a computer program and may be RAM, ROM, or other types of storage devices. Specifically, the memory may include one or more computer-readable storage media, which may be non-transitory. The memory may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory is used to store at least one line of program code.

[0061] The FIFO memory 114 is a first-in-first-out dual-port buffer, with one input port and one output port. The FIFO memory 114 has two pointers, one for reading and one for writing, enabling data writing and reading, thus facilitating data exchange across clock domains. The first piece of data to enter the FIFO memory 114 is the first piece to be removed.

[0062] In the embodiments provided in this application, it should be understood that the disclosed SPI communication-based data writing method can be implemented in other ways. For example, the various embodiments of the electronic terminal described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0063] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0064] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0065] like Figure 5As shown, if the integrated unit described above is implemented as a software functional unit and sold or used as an independent product, it can be stored in the computer-readable storage medium 200. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions / computer programs to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of various embodiments of the present invention. The aforementioned storage medium includes various media such as USB flash drives, mobile hard drives, read-only memory, random access memory, magnetic disks, or optical disks, as well as electronic terminals such as computers, mobile phones, laptops, tablets, and cameras that have the aforementioned storage media.

[0066] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A data writing method based on SPI communication, characterized in that, include: Receive the current preset byte data transmitted by the host through the SPI interface; The write enable of the FIFO memory is determined based on the data receive flag corresponding to the current preset byte data and the non-empty flag of the FIFO memory. If the write enable of the FIFO memory is valid, then the current preset byte data is written into the FIFO memory; The step of determining whether the write enable of the FIFO memory is valid based on the data receive flag corresponding to the current preset byte data and the non-empty flag of the FIFO memory includes: Determine whether the data reception flag is the first flag; the first flag is used to indicate that data reception has been completed. Determine whether the non-empty flag is the second flag; the second flag is used to indicate that the FIFO memory is in a non-empty state, and the non-empty flag not being the second flag indicates that the FIFO memory does not contain data or the FIFO memory is in a full state; If the data receiving flag is the first flag and the non-empty flag is the second flag, then the write enable of the FIFO memory is determined to be valid.

2. The data writing method according to claim 1, characterized in that, The step of determining whether the data reception flag is the first flag includes: Determine the signal states of the set input signal and the clear input signal; If the set input signal is a high-level signal and the clear input signal is a low-level signal, then the data receiving flag is determined to be the first flag.

3. The data writing method according to claim 2, characterized in that, The step of determining whether the data reception flag is the first flag bit further includes: If the reset input signal is a high-level signal, it is determined that the data receiving flag is not the first flag.

4. The data writing method according to claim 3, characterized in that, After receiving the current preset byte data transmitted by the host via the SPI interface, it includes: Within the first clock domain, the set input signal is configured as a high-level signal, and the clear input signal is configured as a low-level signal.

5. The data writing method according to claim 4, characterized in that, The step of determining whether the data reception flag is the first flag includes: The data receiving flag is used in the second clock domain to determine whether the data receiving flag is the first flag; wherein the second clock domain is different from the first clock domain.

6. The data writing method according to claim 5, characterized in that, After determining whether the data reception flag is the first flag bit in the second clock domain using the data reception flag bit, the process includes: The data receiving flag is synchronized to the first clock domain, and the clear input signal is configured as a high-level signal within the first clock domain.

7. The data writing method according to claim 6, characterized in that, The time difference T3 between configuring the reset input signal to a high level and configuring the set input signal to a high level is set to T3+T4>k*(mT1+nT2), where T1 is the clock cycle of the master and slave, T2 is the bus clock cycle of the slave, T4 is the reception time of the current preset byte data, T3+T4=j*T1 is the time required to receive the current preset byte data, and k, m, n and j are all positive integers.

8. The data writing method according to claim 1, characterized in that, The step of writing the current preset byte data into the FIFO memory includes: After reading the previous preset byte data from the FIFO memory, the current preset byte data is written into the FIFO memory.

9. The data writing method according to claim 1, characterized in that: The step of writing the current preset byte data into the FIFO memory includes: The write enable is triggered at the clock edge to write the current preset byte data into the FIFO memory.

10. An electronic terminal, characterized in that, include: The processor, an SPI interface coupled to the processor, a memory coupled to the processor, and a FIFO memory coupled to the processor, the memory storing a computer program, the processor executing the computer program to implement the data writing method as described in any one of claims 1-9.

11. A computer-readable storage medium, characterized in that, The device contains a computer program that can be executed by a processor to implement the data writing method as described in any one of claims 1-9.

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