A radio frequency pulse generation method and device based on FPGA

Abstract

The present invention provides an FPGA-based radio frequency pulse generation method and device. The method: determines the position of each high-speed data transmission interface for transmitting waveform data in the FPGA according to the distribution of RAM resources in the FPGA, and enables each high-speed data transmission interface for transmitting waveform data to obtain RAM resources of preset capacity based on the principle of proximity; then, with timing priority as the wiring strategy, optimizes the wiring of the high-speed data transmission interface for transmitting waveform data in the FPGA and its corresponding RAM resources, so that the logic timing of the FPGA converges; finally, the waveform data cached in the RAM resources is output through the high-speed data transmission interface, and a radio frequency pulse signal is generated through a digital-to-analog converter and a radio frequency front-end unit. Therefore, the present invention can solve the problem of non-convergence of logic timing when the FPGA outputs waveform data concurrently from multiple large-capacity RAMs.

Description

Technical Field

[0001] The present invention relates to the field of quantum measurement and control technology, and in particular to a method and device for generating radio frequency pulses based on FPGA. Background Art

[0002] The operating principle of a quantum computer is to manipulate the qubits (qubits) fabricated on a quantum chip through a quantum measurement and control system to implement a quantum algorithm. The quantum measurement and control system then reads the qubits' measured output to obtain the computational result. The quantum measurement and control system primarily comprises a low-noise precision voltage unit, a pulse generator, a radio frequency pulse unit, a reflectometry unit, and a high-precision microwave source, forming the measurement and control channels. Each measurement and control channel is used to manipulate and measure a single qubit. To achieve quantum computation with a larger number of qubits, the quantum measurement and control system must have a sufficient number of measurement and control channels to support the manipulation and measurement of more qubits.

[0003] Among them, the principle of the RF pulse unit generating a RF pulse signal is as follows Figure 1 As shown, waveform data is cached in RAM. Then, based on a trigger signal, the cached waveform data in RAM is output to a digital-to-analog converter (DAC). The DAC generates a waveform signal in real time based on the waveform data. Finally, the RF front-end (RF) generates a corresponding RF pulse signal based on the waveform signal output by the DAC. Therefore, supporting the manipulation of more qubits requires a large amount of RAM resources.

[0004] FPGAs, with their rich hardware resources (including RAM hardware resources) and reprogrammable features, are usually used in RF pulse units to provide RAM hardware resources and achieve synchronous output of multiple waveform data. However, when FPGAs output waveform data concurrently from multiple large-capacity RAMs, logical timing may not converge, making it impossible for the synchronization of multiple waveform data outputs to meet the synchronization requirements between measurement and control channels. Although the problem of logical timing non-convergence can be alleviated by reducing the number of FPGA output waveform data channels, more FPGAs must be used to achieve the same number of waveform output channels, which will increase hardware costs. Summary of the Invention

[0005] In view of the above-mentioned deficiencies in the prior art, the purpose of the present invention is to provide an FPGA-based RF pulse generation method that optimizes the layout of RAM resources and high-speed data transmission interfaces within the FPGA, thereby solving the problem of non-convergence of logic timing when the FPGA outputs waveform data concurrently from multiple large-capacity RAM channels.

[0006] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions:

[0007] A method for generating radio frequency pulses based on FPGA, comprising the following steps:

[0008] S1: Determine the position of a high-speed data transmission interface for transmitting waveform data in the FPGA according to the distribution of RAM resources of the FPGA, so that each high-speed data transmission interface for transmitting waveform data obtains RAM resources of a preset capacity based on the principle of proximity;

[0009] S2: Using timing priority as a routing strategy, optimizing the routing of a high-speed data transmission interface for transmitting waveform data in the FPGA and its corresponding RAM resources, and closing the logic timing of the FPGA;

[0010] S3: caching the waveform data of each radio frequency pulse signal into a RAM resource corresponding to a high-speed data transmission interface for transmitting the waveform data of the radio frequency pulse signal;

[0011] S4: According to the trigger control of the trigger signal, each high-speed data transmission interface for transmitting waveform data reads the waveform data cached in its corresponding RAM resource and outputs it to its corresponding digital-to-analog converter; each of the digital-to-analog converters generates a corresponding waveform signal based on the input waveform data and outputs it to its corresponding RF front-end unit to generate a corresponding RF pulse signal.

[0012] According to a specific embodiment, in step S2 of the FPGA-based radio frequency pulse generation method of the present invention, the method of determining whether the logic timing of the FPGA is converged is:

[0013] Obtain the external routing delay of the clock CLK0 used in the timing reference analysis from the input to the FPGA, the first internal routing delay of the clock CLK0 reaching the D terminal of the first REG on the internal timing path of the FPGA, and the second internal routing delay of the clock CLK0 between any two adjacent REGs on the internal timing path of the FPGA;

[0014] If the total delay of the external routing delay and the first internal routing delay is less than the clock period of clock CLK0, and the second internal routing delay is less than the clock period of clock CLK0, the logic timing of the FPGA converges; otherwise, the logic timing of the FPGA does not converge.

[0015] According to a specific embodiment, in the FPGA-based RF pulse generation method of the present invention, if the second internal wiring delay between two adjacent REGs is greater than the clock period of the clock CLK0, one level of REG is added between the two adjacent REGs.

[0016] According to a specific embodiment, in step S2 of the FPGA-based RF pulse generation method of the present invention, when the logic timing of the FPGA converges, the LockRegion method is used to lock the current wiring method of each high-speed data transmission interface for transmitting waveform data in the FPGA and its corresponding RAM resources.

[0017] According to a specific embodiment, in the FPGA-based radio frequency pulse generation method of the present invention, the high-speed data transmission interface is a high-speed serial interface of the JESD204B protocol.

[0018] Another aspect of the present invention further provides a radio frequency pulse generating device based on FPGA, comprising:

[0019] FPGA, N digital-to-analog converters, and N radio frequency front-end units;

[0020] The FPGA is configured to: determine the positions of N high-speed data transmission interfaces for transmitting waveform data in the FPGA based on the distribution of RAM resources in the FPGA, so that each high-speed data transmission interface for transmitting waveform data obtains RAM resources of preset capacity based on the principle of proximity; optimize the wiring of the N high-speed data transmission interfaces for transmitting waveform data in the FPGA and their corresponding RAM resources based on timing priority, so that logic timing converges; and, based on the trigger control of a trigger signal, each high-speed data transmission interface for transmitting waveform data reads the waveform data cached in its corresponding RAM resource and outputs it to its corresponding digital-to-analog converter;

[0021] Each of the digital-to-analog converters generates a corresponding waveform signal based on the input waveform data and outputs it to its corresponding radio frequency front-end unit to generate a corresponding radio frequency pulse signal.

[0022] According to a specific embodiment, in the FPGA-based radio frequency pulse generating device of the present invention, the FPGA is configured such that: if the total delay of the external routing delay and the first internal routing delay is less than the clock period of the clock CLK0 and the second internal routing delay is less than the clock period of the clock CLK0, then the logic timing converges; otherwise, the logic timing does not converge;

[0023] Among them, the external routing delay is the delay of the clock CLK0 used in the timing reference analysis input to the FPGA, the first internal routing delay is the delay of the clock CLK0 reaching the D end of the first REG on the internal timing path of the FPGA, and the second internal routing delay is the delay of the clock CLK0 between any two adjacent REGs on the internal timing path of the FPGA.

[0024] According to a specific embodiment, in the FPGA-based RF pulse generating device of the present invention, the FPGA is configured to: when the second internal wiring delay between two adjacent REGs is greater than the clock period of the clock CLK0, then add one level of REG between the two adjacent REGs.

[0025] According to a specific embodiment, in the FPGA-based radio frequency pulse generation device of the present invention, the FPGA is configured to: when the logic timing converges, use the LockRegion method to lock the current wiring method of each high-speed data transmission interface for transmitting waveform data in the FPGA and its corresponding RAM resources.

[0026] According to a specific embodiment, in the FPGA-based radio frequency pulse generating device of the present invention, the high-speed data transmission interface is a high-speed serial interface of the JESD204B protocol.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] In the FPGA-based radio frequency pulse generation method of the present invention, the number and position of each high-speed data transmission interface for transmitting waveform data in the FPGA are determined according to the number of radio frequency pulse signals that need to be generated and the distribution of RAM resources of the FPGA, and each high-speed data transmission interface for transmitting waveform data obtains RAM resources of preset capacity based on the principle of proximity; then, with timing priority as the wiring strategy, the wiring of each high-speed data transmission interface for transmitting waveform data in the FPGA and the corresponding RAM resources are optimized to converge the logic timing of the FPGA; finally, the waveform data is cached in the RAM resources, and the waveform data is output through the high-speed data transmission interface, and the radio frequency pulse signal is generated through the digital-to-analog converter and the radio frequency front-end unit; therefore, the present invention can solve the problem of non-convergence of logic timing when the FPGA outputs waveform data concurrently from multiple large-capacity RAMs. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of the principle of generating a radio frequency pulse signal for a radio frequency pulse unit;

[0030] Figure 2 Schematic diagram of the flow of a radio frequency pulse generation method based on FPGA in an embodiment of the present invention;

[0031] Figure 3 This is the location distribution diagram of the high-speed data transmission interface of FPGA in general application scenarios;

[0032] Figure 4 This is a location distribution diagram of the high-speed data transmission interface in the FPGA in an embodiment of the present invention;

[0033] Figure 5 This is a timing path analysis diagram of the FPGA in an embodiment of the present invention;

[0034] Figure 6 Schematic diagram of the structure of a radio frequency pulse generating device based on FPGA in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments. However, this should not be construed as limiting the scope of the present invention to the following embodiments, as all technologies implemented based on the present invention fall within the scope of the present invention.

[0036] like Figure 2 As shown, the present invention provides a FPGA-based radio frequency pulse generation method, which includes the following steps:

[0037] S1: Determine the position of a high-speed data transmission interface for transmitting waveform data in the FPGA according to the distribution of RAM resources of the FPGA, so that each high-speed data transmission interface for transmitting waveform data obtains RAM resources of a preset capacity based on the principle of proximity;

[0038] S2: Using timing priority as a routing strategy, optimizing the routing of a high-speed data transmission interface for transmitting waveform data in the FPGA and its corresponding RAM resources, and closing the logic timing of the FPGA;

[0039] S3: caching the waveform data of each radio frequency pulse signal into a RAM resource corresponding to a high-speed data transmission interface for transmitting the waveform data of the radio frequency pulse signal;

[0040] S4: According to the trigger control of the trigger signal, each high-speed data transmission interface for transmitting waveform data reads the waveform data cached in its corresponding RAM resource and outputs it to its corresponding digital-to-analog converter; each of the digital-to-analog converters generates a corresponding waveform signal based on the input waveform data and outputs it to its corresponding RF front-end unit to generate a corresponding RF pulse signal.

[0041] Specifically, the FPGA integrates a high-speed data transmission interface that is convenient for matching with the high-speed DAC. It is usually called a high-speed transceiver or GT. It supports multiple protocols such as PCIE, JESD204B, and SATA. Different FPGA models have different numbers of high-speed transceivers. Therefore, the FPGA's high-speed transceiver resources need to be greater than the number of high-speed DACs. Moreover, since the function of the high-speed data transmission interface is to read the waveform data cached in the FPGA's RAM resources, and the waveform data has high requirements for the capacity of the RAM resources, it is necessary to optimize the location selection of the high-speed data transmission interface so that it can obtain RAM resources of preset capacity based on the principle of proximity. Taking the FPGA model XC7VX690T as an example, it contains 20 high-speed transceiver banks (also called Quads) and needs to generate 8-channel RF pulse signals (i.e., 8 high-speed DACs). Figure 3 As shown in the figure, if the selected 8 high-speed data transmission interfaces are concentrated in one area, when the FPGA internal RAM resources are subsequently opened up for each high-speed data transmission interface, some high-speed data transmission interfaces may have a long path to access the RAM resources. Finally, during the timing analysis, the routing delay is large, resulting in non-convergence of the timing. Since the RAM resources on the FPGA are basically evenly distributed, the high-speed data transmission interfaces are evenly distributed around the FPGA, that is, Figure 4 As shown, it avoids the high-speed data transmission interface from accessing RAM resources through a long path, facilitating the implementation of subsequent logic codes.

[0042] like Figure 5 As shown, in step S2, the method of determining whether the logic timing of the FPGA is converged is:

[0043] Obtain the Input Delay, the external routing delay from the clock CLK0 input to the FPGA, the Internal Delay 1, the first internal routing delay from the clock CLK0 to the D-terminal of REGA on the internal timing path of the FPGA, and the Data Path Delay, the second internal routing delay from the clock CLK0 to any two adjacent REGs on the internal timing path of the FPGA.

[0044] If the total delay of the external routing delay Input Delay and the first internal routing delay Internal Delay 1 is less than the clock period of clock CLK0, and the second internal routing delay Data Path Delay is less than the clock period of clock CLK0, the logic timing of the FPGA converges. Otherwise, the logic timing of the FPGA does not converge.

[0045] During implementation, if the second internal routing delay between two adjacent REGs on the internal timing path of the clock CLK0 of the FPGA is greater than the clock period of the clock CLK0 , one level of REG is added between the two adjacent REGs.

[0046] Since the RAM resources used for the waveform data of multiple RF pulse signals are resources within the FPGA chip, they will occupy a large amount of logic resources and wiring resources. During the layout and wiring stage of the FPGA internal design implementation, if the total delay of the external routing delay InputDelay and the first internal routing delay Internal Delay 1 is greater than the clock period of the clock CLK0 or the second internal routing delay Data Path Delay is greater than the clock period of the clock CLK0, it may cause the timing of some clocks and data to fail to meet the setup and hold time, resulting in timing non-convergence and data errors. At the same time, since the high-speed data transmission interface is a high-speed serial interface of the JESD204B protocol, the FPGA has its own timing constraints and adjustment Internal Delay 2. Therefore, the present invention can solve the problem of non-convergence of logic timing when the FPGA outputs waveform data concurrently from multiple large-capacity RAMs.

[0047] Furthermore, when the FPGA's logic timing converges, the LockRegion method is used to lock the current routing of each high-speed data transmission interface used to transmit waveform data in the FPGA and its corresponding RAM resources. This allows for subsequent modifications to other program functions without the need for re-synthesis and implementation.

[0048] Another aspect of the present invention also provides Figure 6 The FPGA-based radio frequency pulse generating device shown includes:

[0049] FPGA, 8 digital-to-analog converters DAC1 to DAC8, and 8 radio frequency front-end units RF1 to RF8;

[0050] The FPGA is configured to: determine the location of high-speed data transmission interfaces GT1 to GT8 for transmitting waveform data in the FPGA based on the distribution of RAM resources in the FPGA, so that each high-speed data transmission interface for transmitting waveform data obtains RAM resources of preset capacity based on the principle of proximity; optimize the wiring of the eight high-speed data transmission interfaces GT1 to GT8 for transmitting waveform data in the FPGA and their corresponding RAM resources based on timing priority, so that logic timing converges; and, based on the trigger control of a trigger signal, each high-speed data transmission interface for transmitting waveform data reads the waveform data cached in its corresponding RAM resource and outputs it to its corresponding digital-to-analog converter;

[0051] Each of the digital-to-analog converters generates a corresponding waveform signal based on the input waveform data and outputs it to its corresponding radio frequency front-end unit to generate a corresponding radio frequency pulse signal.

[0052] In the FPGA-based radio frequency pulse generating device of the present invention, the FPGA is configured such that: if the total delay of the external routing delay and the first internal routing delay is less than the clock period of the clock CLK0 and the second internal routing delay is less than the clock period of the clock CLK0, the logic timing converges; otherwise, the logic timing does not converge;

[0053] Among them, the external routing delay is the delay of the clock CLK0 used in the timing reference analysis input to the FPGA, the first internal routing delay is the delay of the clock CLK0 reaching the D end of the first REG on the internal timing path of the FPGA, and the second internal routing delay is the delay of the clock CLK0 between any two adjacent REGs on the internal timing path of the FPGA.

[0054] During implementation, the FPGA is configured to add one level of REG between two adjacent REGs when the second internal wiring delay between the two adjacent REGs is greater than the clock cycle of the clock CLK0 .

[0055] In the FPGA-based radio frequency pulse generating device of the present invention, the FPGA is configured to: when the logic timing converges, use the LockRegion method to lock the current wiring method of each high-speed data transmission interface for transmitting waveform data in the FPGA and its corresponding RAM resources.

[0056] In the FPGA-based radio frequency pulse generating device of the present invention, the high-speed data transmission interface is a high-speed serial interface of the JESD204B protocol.

[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for generating radio frequency pulses based on FPGA, comprising the following steps: S1: Determine the position of a high-speed data transmission interface for transmitting waveform data in the FPGA according to the distribution of RAM resources of the FPGA, so that each high-speed data transmission interface for transmitting waveform data obtains RAM resources of a preset capacity based on the principle of proximity; S2: Using timing priority as a routing strategy, optimizing the routing of a high-speed data transmission interface for transmitting waveform data in the FPGA and its corresponding RAM resources, and closing the logic timing of the FPGA; S3: caching the waveform data of each radio frequency pulse signal into a RAM resource corresponding to a high-speed data transmission interface for transmitting the waveform data of the radio frequency pulse signal; S4: According to the trigger control of the trigger signal, each high-speed data transmission interface for transmitting waveform data reads the waveform data cached in its corresponding RAM resource and outputs it to its corresponding digital-to-analog converter; each of the digital-to-analog converters generates a corresponding waveform signal based on the input waveform data and outputs it to its corresponding RF front-end unit to generate a corresponding RF pulse signal.

2. The FPGA-based radio frequency pulse generation method according to claim 1, wherein in step S2, the method for determining whether the logic timing of the FPGA has converged is: Obtain the external routing delay of the clock CLK0 used in the timing reference analysis from the input to the FPGA, the first internal routing delay of the clock CLK0 reaching the D terminal of the first REG on the internal timing path of the FPGA, and the second internal routing delay of the clock CLK0 between any two adjacent REGs on the internal timing path of the FPGA; If the total delay of the external routing delay and the first internal routing delay is less than the clock period of clock CLK0, and the second internal routing delay is less than the clock period of clock CLK0, the logic timing of the FPGA converges; otherwise, the logic timing of the FPGA does not converge.

3. The FPGA-based RF pulse generation method according to claim 2, wherein if the second internal wiring delay between two adjacent REGs is greater than the clock period of the clock CLK0, one level of REG is added between the two adjacent REGs.

4. The FPGA-based RF pulse generation method according to claim 1 , wherein, in step S2, when the logic timing of the FPGA converges, a LockRegion method is used to lock the current wiring mode of each high-speed data transmission interface for transmitting waveform data in the FPGA and its corresponding RAM resources.

5. The FPGA-based radio frequency pulse generation method according to claim 1, wherein the high-speed data transmission interface is a high-speed serial interface of the JESD204B protocol.

6. A radio frequency pulse generating device based on FPGA, characterized in that: include: FPGA, N digital-to-analog converters, and N radio frequency front-end units; The FPGA is configured to: determine the positions of N high-speed data transmission interfaces for transmitting waveform data in the FPGA according to the distribution of RAM resources in the FPGA, so that each high-speed data transmission interface for transmitting waveform data obtains RAM resources of a preset capacity based on the principle of proximity; Using a timing-first routing strategy, N high-speed data transmission interfaces for transmitting waveform data in the FPGA and their corresponding RAM resources are optimized for routing to achieve logic timing convergence; and, based on trigger control of a trigger signal, each high-speed data transmission interface for transmitting waveform data reads the waveform data cached in its corresponding RAM resource and outputs it to its corresponding digital-to-analog converter. Each of the digital-to-analog converters generates a corresponding waveform signal based on the input waveform data and outputs it to its corresponding radio frequency front-end unit to generate a corresponding radio frequency pulse signal.

7. The FPGA-based radio frequency pulse generating device according to claim 6, wherein: The FPGA is configured such that: if the total delay of the external routing delay and the first internal routing delay is less than the clock period of the clock CLK0 and the second internal routing delay is less than the clock period of the clock CLK0, the logic timing converges; otherwise, the logic timing does not converge; Among them, the external routing delay is the delay of the clock CLK0 used in the timing reference analysis input to the FPGA, the first internal routing delay is the delay of the clock CLK0 reaching the D end of the first REG on the internal timing path of the FPGA, and the second internal routing delay is the delay of the clock CLK0 between any two adjacent REGs on the internal timing path of the FPGA.

8. The FPGA-based RF pulse generating device according to claim 7, wherein the FPGA is configured to add one level of REG between two adjacent REGs when the second internal wiring delay between the two adjacent REGs is greater than the clock period of the clock CLK0.

9. The FPGA-based RF pulse generation device according to claim 6, wherein the FPGA is configured to lock the current wiring mode of each high-speed data transmission interface for transmitting waveform data in the FPGA and its corresponding RAM resources using a LockRegion method when logic timing converges.

10. The FPGA-based radio frequency pulse generating device according to claim 6, wherein the high-speed data transmission interface is a high-speed serial interface of the JESD204B protocol.

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