A signal shielding circuit and a semiconductor memory

Abstract

An embodiment of the present application provides a signal shielding circuit and a semiconductor memory. The signal shielding circuit includes a receiving circuit, a delay control circuit, and a logic operation circuit. Among them, the receiving circuit is configured to receive a signal to be processed and a chip select signal, and output an initial processed signal and an initial chip select signal. The delay control circuit is configured to perform delay and logic control operations on the initial chip select signal to obtain a chip select shielding signal, and the pulse width of the chip select shielding signal is greater than or equal to two preset clock cycles. The logic operation circuit is configured to perform invalid shielding processing on the initial processed signal according to the chip select shielding signal to obtain a target signal. In this way, while ensuring that the DRAM does not lose valid information, it is also possible to avoid current waste to the greatest extent, achieving the purpose of saving power consumption.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a signal shielding circuit and a semiconductor memory. Background Art

[0002] With the continuous development of semiconductor technology, when people manufacture and use devices such as computers, higher and higher requirements are put forward for the data transmission speed. In order to obtain a faster data transmission speed, a series of devices such as memories that can transmit data at double data rate (DDR) have emerged.

[0003] In a dynamic random access memory (DRAM), for the DRAM, currently, the chip select (CS) signal can be used to mask the command address signal or the clock signal with an invalid signal, thereby reducing the current consumption. Summary of the Invention

[0004] This application provides a signal shielding circuit and a semiconductor memory, which can maximize the avoidance of current waste while ensuring that the DRAM does not lose valid information, achieving the purpose of saving power consumption.

[0005] In a first aspect, an embodiment of this application provides a signal shielding circuit, which includes a receiving circuit, a delay control circuit, and a logic operation circuit; wherein,

[0006] The receiving circuit is configured to receive a signal to be processed and a chip select signal, and output an initial processed signal and an initial chip select signal;

[0007] The delay control circuit is configured to perform delay and logic control operations on the initial chip select signal to obtain a chip select shielding signal, and the pulse width of the chip select shielding signal is greater than or equal to two preset clock cycles;

[0008] The logic operation circuit is configured to perform invalid shielding processing on the initial processed signal according to the chip select shielding signal to obtain a target signal.

[0009] In some embodiments, the chip select signal is a signal indicating whether the chip is selected, and the chip select signal is a low-level effective pulse signal, and the pulse width of the chip select signal is one preset clock cycle.

[0010] In some embodiments, the logic operation circuit is specifically configured to, when the initial processing signal is a signal corresponding to the target chip, mask the invalid signals in the initial processing signal according to the chip select masking signal; and / or, when the initial processing signal is a signal not corresponding to the target chip, mask all of the initial processing signal according to the chip select masking signal;

[0011] Wherein, the target chip is the chip selected by the chip select signal, and the non-target chip is the chip not selected by the chip select signal.

[0012] In some embodiments, the signal to be processed includes at least one of the following: a command address signal and a clock signal; wherein, the period of the clock signal is equal to the preset clock period.

[0013] In some embodiments, when the signal to be processed is a command address signal, the receiving circuit includes a first receiving module and a second receiving module, and the logic operation circuit includes a first logic operation circuit; wherein,

[0014] The first receiving module is configured to receive the command address signal and output an initial command address signal;

[0015] The second receiving module is configured to receive the chip select signal and output an initial chip select signal;

[0016] The delay control circuit is connected to the output end of the second receiving module and is configured to perform a delay and a logic control operation on the initial chip select signal to obtain the chip select masking signal;

[0017] The first logic operation circuit is connected to the output end of the delay control circuit and the output end of the first receiving module, and is configured to perform a logic operation on the chip select masking signal and the initial command address signal to obtain a target command address signal.

[0018] In some embodiments, when the signal to be processed is a clock signal, the receiving circuit includes a third receiving module and a fourth receiving module, and the logic operation circuit includes a second logic operation circuit; wherein,

[0019] The third receiving module is configured to receive the clock signal and output an initial clock signal;

[0020] The fourth receiving module is configured to receive the chip select signal and output an initial chip select signal;

[0021] The delay control circuit is connected to the output end of the fourth receiving module and is configured to perform a delay and a logic control operation on the initial chip select signal to obtain the chip select masking signal;

[0022] The second logic operation circuit is connected to the output end of the delay control circuit and the output end of the third receiving module, and is used to perform a logic operation on the chip select mask signal and the initial clock signal to obtain a target clock signal.

[0023] In some embodiments, when the signal to be processed is a command address signal and a clock signal, the receiving circuit includes a first receiving module, a second receiving module, and a third receiving module, and the logic operation circuit includes a first logic operation circuit and a second logic operation circuit; wherein,

[0024] The first receiving module is used to receive the command address signal and output an initial command address signal;

[0025] The second receiving module is used to receive the chip select signal and output an initial chip select signal;

[0026] The third receiving module is used to receive the clock signal and output an initial clock signal;

[0027] The delay control circuit is connected to the output end of the second receiving module, and is used to perform a delay and logic control operation on the initial chip select signal to obtain the chip select mask signal;

[0028] The first logic operation circuit is connected to the output end of the delay control circuit and the output end of the first receiving module, and is used to perform an invalid masking process on the initial command address signal according to the chip select mask signal to obtain a target command address signal; and

[0029] The second logic operation circuit is connected to the output end of the delay control circuit and the output end of the third receiving module, and is used to perform a logic operation on the chip select mask signal and the initial clock signal to obtain a target clock signal.

[0030] In some embodiments, the first logic operation circuit includes a first buffer, a first AND gate, and a second buffer; wherein,

[0031] The first buffer is connected to the first receiving module, and is used to perform a drive enhancement and delay process on the initial command address signal to obtain a first command address signal;

[0032] The first AND gate is connected to the output end of the first buffer and the output end of the delay control circuit, and is used to perform an AND operation on the chip select mask signal and the first command address signal to obtain a second command address signal;

[0033] The second buffer is connected to the output end of the first AND gate, and is used to perform a drive enhancement and delay process on the second command address signal to obtain the target command address signal.

[0034] In some embodiments, the second logic operation circuit includes a third buffer, a second AND gate, and a fourth buffer; wherein,

[0035] The third buffer is connected to the third receiving module and is configured to perform drive enhancement and delay processing on the initial clock signal to obtain a first clock signal;

[0036] The second AND gate is connected to the output end of the third buffer and the output end of the delay control circuit, and is configured to perform an AND operation on the chip select mask signal and the first clock signal to obtain a second clock signal;

[0037] The fourth buffer is connected to the output end of the second AND gate and is configured to perform drive enhancement and delay processing on the second clock signal to obtain the target clock signal.

[0038] In some embodiments, the delay control circuit includes a delay module, a pulse width adjustment module, a first inverter, and a first OR gate; wherein,

[0039] The first inverter is configured to perform an inversion process on the initial chip select signal to obtain a first intermediate signal;

[0040] The delay module is configured to perform a delay process on the initial chip select signal to obtain a second intermediate signal;

[0041] The pulse width adjustment module is configured to perform a pulse width expansion process on the second intermediate signal to obtain a third intermediate signal;

[0042] The first OR gate is connected to the output end of the first inverter and the output end of the pulse width adjustment module, and is configured to perform an OR operation on the first intermediate signal and the third intermediate signal to obtain the chip select mask signal.

[0043] In some embodiments, the delay module includes a first delay unit, a second delay unit, and a second inverter, and the second inverter is between the first delay unit and the second delay unit; wherein,

[0044] The first delay unit is configured to perform a first delay process on the initial chip select signal to obtain a first delay signal;

[0045] The second inverter is configured to perform an inversion process on the first delay signal to obtain an inverted delay signal;

[0046] The second delay unit is configured to perform a second delay process on the inverted delay signal to obtain the second intermediate signal.

[0047] In some embodiments, both the first delay unit and the second delay unit are composed of a resistor R and a capacitor C.

[0048] In some embodiments, the pulse width adjustment module includes a fifth buffer and a second OR gate; wherein,

[0049] The fifth buffer, connected to the output end of the delay module, is used for driving enhancement and delay processing of the second intermediate signal to obtain a fourth intermediate signal;

[0050] The second OR gate, connected to the output end of the delay module and the output end of the fifth buffer, is used for performing an OR operation on the second intermediate signal and the fourth intermediate signal to obtain the third intermediate signal.

[0051] In some embodiments, the signal shielding circuit further includes a buffer module, and the buffer module is composed of a plurality of sixth buffers; wherein,

[0052] The buffer module is used for sequentially performing driving enhancement and delay processing on the initial chip select signal according to the plurality of sixth buffers to obtain a target chip select signal.

[0053] In some embodiments, the signal shielding circuit further includes a sampling circuit and a decoding circuit; wherein,

[0054] The sampling circuit is used for receiving the target command address signal, the target clock signal, and the target chip select signal, and sampling the target command address signal and the target chip select signal by using the target clock signal to obtain a sampled command address signal and a sampled chip select signal;

[0055] The decoding circuit, connected to the output end of the sampling circuit, decodes the sampled chip select signal and the sampled command address signal to obtain a target command result.

[0056] In some embodiments, the sampling circuit is composed of a plurality of D flip-flops.

[0057] In some embodiments, the buffer is composed of two inverters.

[0058] In some embodiments, the rising edge time of the chip select shielding signal is earlier than the pulse start time of the first command address signal; the falling edge time of the chip select shielding signal is later than the pulse end time of the first command address signal; wherein, the chip select shielding signal and the first command address signal correspond to the same valid pulse of the chip select signal.

[0059] Second aspect, embodiments of the present application provide a semiconductor memory, which includes the signal shielding circuit described in any one of the first aspect.

[0060] In some embodiments, the semiconductor memory is a dynamic random access memory DRAM chip.

[0061] In some embodiments, the dynamic random access memory DRAM chip complies with the DDR5 memory specification.

[0062] Embodiments of the present application provide a signal shielding circuit and a semiconductor memory. The signal shielding circuit includes a receiving circuit, a delay control circuit, and a logic operation circuit. Among them, the receiving circuit is used to receive a signal to be processed and a chip select signal, and output an initial processed signal and an initial chip select signal. The delay control circuit is used to delay and perform logic control operations on the initial chip select signal to obtain a chip select shielding signal, and the pulse width of the chip select shielding signal is greater than or equal to two preset clock cycles. The logic operation circuit is used to perform invalid shielding processing on the initial processed signal according to the chip select shielding signal to obtain a target signal. In this way, since the command address signal in DDR5 DRAM is based on a signal of two preset clock cycles, and the pulse width of the chip select shielding signal proposed in the present application is greater than or equal to two preset clock cycles, when shielding the initial processed signal, it is possible to ensure that DDR5 DRAM does not lose valid information while maximizing the avoidance of current waste and achieving the purpose of power consumption savings. Description of the Drawings

[0063] Figure 1 It is a schematic diagram of an application scenario of a DRAM;

[0064] Figure 2 It is a schematic diagram of the composition structure of a signal shielding circuit;

[0065] Figure 3 It is a schematic diagram of the signal timing of a signal shielding circuit;

[0066] Figure 4 It is a schematic diagram of the read command timing of a DDR5;

[0067] Figure 5 It is a schematic diagram of the signal timing of a DDR5;

[0068] Figure 6 It is a schematic diagram of the signal timing of another DDR5;

[0069] Figure 7 It is a schematic diagram of the composition structure of a signal shielding circuit provided by an embodiment of the present application Figure 1 ;

[0070] Figure 8A Schematic diagram of the composition structure of a signal shielding circuit provided by an embodiment of the present application Figure 2 ;

[0071] Figure 8B Schematic diagram of the composition structure of a signal shielding circuit provided by an embodiment of the present application Figure 3 ;

[0072] Figure 8C Schematic diagram of the composition structure of a signal shielding circuit provided by an embodiment of the present application Figure 4 ;

[0073] Figure 9A Schematic diagram of the composition structure of a signal shielding circuit provided by an embodiment of the present application Figure 5 ;

[0074] Figure 9B Schematic diagram of the composition structure of a signal shielding circuit provided by an embodiment of the present application Figure 6 ;

[0075] Figure 9C Schematic diagram of the composition structure of a signal shielding circuit provided by an embodiment of the present application Figure 7 ;

[0076] Figure 10 Signal timing diagram of a signal shielding circuit provided by an embodiment of the present application Figure 1 ;

[0077] Figure 11 Schematic diagram eight of the composition structure of a signal shielding circuit provided by an embodiment of the present application;

[0078] Figure 12 Schematic diagram of the specific circuit structure of a signal shielding circuit provided by an embodiment of the present application Figure 1 ;

[0079] Figure 13A Signal timing diagram of a signal shielding circuit provided by an embodiment of the present application Figure 2 ;

[0080] Figure 13B Signal timing diagram of a signal shielding circuit provided by an embodiment of the present application Figure 3 ;

[0081] Figure 14 Schematic diagram of the specific circuit structure of a signal shielding circuit provided by an embodiment of the present application Figure 2 ;

[0082] Figure 15A Signal timing diagram of a signal shielding circuit provided by an embodiment of the present application Figure 4 ;

[0083] Figure 15B Signal timing schematic of a signal shielding circuit provided by an embodiment of the present application Figure 5 ;

[0084] Figure 16 Schematic diagram of the composition structure of a semiconductor memory provided by an embodiment of the present application. Detailed implementation manners

[0085] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only for explaining the relevant application, rather than limiting the application. In addition, it should be noted that, for the sake of description, only the parts related to the relevant application are shown in the drawings.

[0086] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0087] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0088] It should be noted that the terms "first\second\third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0089] Before further elaborating on the embodiments of the present application, the nouns and terms involved in the embodiments of the present application are described first. The nouns and terms involved in the embodiments of the present application are applicable to the following explanations:

[0090] Dynamic Random Access Memory (DRAM)

[0091] Synchronous Dynamic Random Access Memory (SDRAM)

[0092] Double Data Rate (DDR)

[0093] Fourth-generation DDR (4th DDR, DDR4)

[0094] Fifth-generation DDR (5th DDR, DDR5)

[0095] Central Processing Unit (CPU)

[0096] Command / Address Input (CA)

[0097] Clock Input (CLK)

[0098] Chip Select Input (CS)

[0099] Unbuffered Dual In-Line Memory Modules or unregistered Dual In-Line Memory Modules (UDIMM)

[0100] Small Outline Dual In-line Memory Module (SODIMM)

[0101] Valid

[0102] Invalid

[0103] Power Consumption

[0104] Buffer / Repeater (RPT)

[0105] See Figure 1 , which shows a schematic diagram of an application scenario of a DRAM. As Figure 1 shown, taking the application scenario of UDIMM / SODIMM as an example, in a UDIMM / SODIMM system, the DRAMs in a row (Rank) on the memory module are connected to the same CS, and the CA / CLK of all the DRAMs in all Ranks are connected together, and different CS signals are connected to different Ranks. For example, Figure 1 as shown, CS0 is connected to Rank0, CS1 is connected to Rank1, and the CA / CLK of all the DRAMs in Rank0 and Rank1 are connected together.

[0106] In other words, when the CPU sends a valid CS0 command, all DRAMs in all ranks will accept CA and CLK commands, and the only difference lies in the CS. Here, CS can be understood as Rank select in a sense, that is, CS can be regarded as a signal indicating whether the chip is selected.

[0107] Understandably, for DDR4 DRAM, which is based on commands in one clock cycle, there are currently two ways to use CS_n to reduce the consumption current: (1) Mask the command address signal with CS_n; (2) Mask the clock signal with CS_n. Among them, the command address signal can be represented by CMD / ADD or CA; the clock signal can be represented by CLK. It should be noted that CMD / ADD here is a general term for various command address signals of DRAM, which can include command signals such as Row Address Strobe (RAS), Column Address Strobe (CAS), Write (WE), Read (RD), etc., and can also include address signals such as A13 - A0. In addition, in practical applications, the number of address signals included in this command address signal can be specifically determined according to the specifications of the DRAM, and the embodiments of the present application do not make any limitations.

[0108] Specifically, referring to Figure 2 , which shows a schematic diagram of the composition structure of a signal masking circuit. As Figure 2 shown, the signal masking circuit 20 may include a first receiver 201, a second receiver 202, a third receiver 203, a first buffer 204, a second buffer 205, a third buffer 206, a first inverter 207, a first AND gate 208, a fourth buffer 209, a fifth buffer 210, a second AND gate 211, a sixth buffer 212, a seventh buffer 213, a D-type flip-flop (Data Flip-Flop or Delay Flip-Flop, DFF) 214, a second inverter 215, and a third AND gate 216. Among them, the two input signals of the first receiver 201 are the chip select signal (represented by CS_n) and the reference signal (represented by VREFCA), and the output signal is the initial chip select signal (represented by CSB); the two input signals of the second receiver 202 are the command address signal (represented by CMD / ADD) and the reference signal (represented by VREFCA), and the output signal is the initial command address signal (represented by CA); the two input signals of the third receiver 203 are the input clock signal (represented by CK_t) and the complementary input clock signal (represented by CK_c), and the output signal is the initial clock signal (represented by CLK).

[0109] In Figure 2 , the driving capabilities of the first buffer 204, the second buffer 205, and the third buffer 206 increase in sequence, and the CSB signal obtains the target chip select signal (denoted as CSBI) after passing through the first buffer 204, the second buffer 205, and the third buffer 206 in sequence. The driving capabilities of the fourth buffer 209 and the fifth buffer 210 also increase in sequence. The CSB signal and the CA signal are input to the first AND gate 208 after passing through the first inverter 207. The output signal of the first AND gate 208 obtains the target command address signal (denoted as CMD / ADD_RPT) after passing through the fourth buffer 209 and the fifth buffer 210 in sequence. The driving capabilities of the sixth buffer 212 and the seventh buffer 213 also increase in sequence. The CSB signal and the CLK signal are input to the second AND gate 211 after passing through the first inverter 207. The output signal of the second AND gate 211 obtains the target clock signal (denoted as CLK_RPT) after passing through the sixth buffer 212 and the seventh buffer 213 in sequence.

[0110] After obtaining CSBI, CMD / ADD_RPT, and CLK_RPT, decoding processing can also be performed on them. Specifically, using the D flip-flop 214, the input CSBI and CMD / ADD_RPT are sampled by CLK_RPT to obtain the sampled chip select signal (denoted as CSB_INTER) and the sampled command address signal (denoted as CMD / ADD_INTER). Then, after passing through the second inverter 215, CSB_INTER and CMD / ADD_INTER are input to the third AND gate 216, and finally the target command result (denoted as CMD / ADD_OUT) is decoded. It should be noted that the D flip-flop 214 is not a single DFF, but can be many DFFs. Figure 2 In

[0111] According to Figure 2 the circuit structure shown, its corresponding signal timing diagram is as shown in Figure 3 In Figure 3Among them, the valid CSB signal (represented by Valid CSB0) is a pulse signal with active low level, and the pulse width is one clock cycle, which is used to indicate that the Rank connected to this Valid CSB0 signal is selected; while the invalid CSB signal (represented by Invalid CSB1) is a high-level signal, which is used to indicate that the Rank connected to this Invalid CSB1 signal is not selected. In this case, the valid target command address signal (represented by Valid CMD / ADD_RPT0) is also a pulse signal, and the pulse width is one clock cycle, that is, within the time period when Valid CSB0 is at low level, the target command address signal can pass through, and it is at low level in other time periods; the invalid target command address signal (represented by Invalid CMD / ADD_RPT1) is a low-level signal. In addition, the valid target clock signal (represented by Valid CLK_RPT0) is also a pulse signal, and within the time period when Valid CSB0 is at low level, the target clock signal can pass through, and it is at low level in other time periods; the invalid target clock signal (represented by Invalid CLK_RPT1) is a low-level signal. Among them, the high-level signal is represented by H, and the low-level signal is represented by L.

[0112] In short, when using CS_n to mask the command address signal, according to Figure 3 the signal timing shown, adopting the CMD / ADD masking method can save the power consumption of the buffers and DFFs in the Invalid CS Rank, and at the same time ensure the normal operation of the Valid CS Rank, so as to be able to save the current consumption of the Valid Rank during the period when CS_n is at high level.

[0113] When using CS_n to mask the clock signal, according to Figure 3 the signal timing shown, adopting the CLK masking method can save the power consumption of the buffers and DFFs in the Invalid CS Rank, and the current saved is many times that of the CMD / ADD masking (due to the faster frequency of CLK), so as to be able to save the current consumption of the Valid Rank during the period when CS_n is at high level.

[0114] It can also be understood that for DDR5 DRAM, during the read command (READ) or write command (WRITE), DDR5 can support BC8, BL16, BL32 (optional) and BL32 OTF (optional), and MR[1:0] is used to select the burst operation mode (Burst Operation Mode). Among them, Figure 4 shows a timing schematic diagram of a read command. InFigure 4 Among them, a read command includes two clock cycles. For example, <BA, BG> and <CA, BL, AP> correspond to one READ command.

[0115] However, for DDR5 DRAM, since its commands are based on two clock cycles, if the traditional architecture is still sampled, for Valid DRAM, the CA information in the second clock cycle will be lost, resulting in CMD decoding failure (see Figure 5 ). Among them, as Figure 5 shown, CLK represents the initial clock signal, CA represents the initial command address signal, CSB represents the initial chip select signal, CMD / ADD_RPT represents the target command address signal, CSB_Masking represents the chip select masking signal, and CMD represents the decoding result. It can be seen that CA includes CA0 and CA2, but CSB is an active-low pulse signal, and the pulse width is only one clock cycle, resulting in the pulse width of CSB_Masking also being one clock cycle. At this time, when CA passes through CSB_Masking, only CA0 in the first clock cycle passes, and CA2 in the second clock cycle is lost, causing CMD decoding failure.

[0116] In this case, since the falling edge of CS_n is synchronized with CMD / ADD in DDR5, when using CS_n to generate CSB_Masking to reduce power consumption, theoretically, the falling edge of CSB_Masking needs to be earlier than CA. Figure 6 shows another signal timing diagram of DDR5. As Figure 6 shown, a CSB_Masking timing reference for DDR5 is provided here, and Figure 6 is a target case under ideal conditions. Among them, t1 represents that the falling edge moment of CSB_Masking is earlier than CA, and t2 represents that the rising edge moment of CSB_Masking is later than CA. In other words, how to ensure that the CMD decoding of Valid DRAM does not lose information while maximizing power savings is a technical problem that this application urgently needs to solve.

[0117] An embodiment of the present application provides a signal shielding circuit, which includes a receiving circuit, a delay control circuit, and a logic operation circuit. Among them, the receiving circuit is used to receive a signal to be processed and a chip select signal, and output an initial processed signal and an initial chip select signal; the delay control circuit is used to delay and perform logic control operations on the initial chip select signal to obtain a chip select shielding signal, and the pulse width of the chip select shielding signal is greater than or equal to two preset clock cycles; the logic operation circuit is used to perform invalid shielding processing on the initial processed signal according to the chip select shielding signal to obtain a target signal. In this way, since the command address signal in the DDR5 DRAM is based on a signal of two preset clock cycles, and the pulse width of the chip select shielding signal proposed in the present application is greater than or equal to two preset clock cycles, when shielding the initial processed signal, it is possible to ensure that the DDR5 DRAM does not lose valid information while maximizing the avoidance of current waste and achieving the purpose of saving power consumption.

[0118] The following will describe each embodiment of the present application in detail with reference to the drawings.

[0119] In an embodiment of the present application, refer to Figure 7 , which shows a schematic structural diagram of a signal shielding circuit 70 provided by an embodiment of the present application. As Figure 7 shown, the signal shielding circuit 70 may include a receiving circuit 710, a delay control circuit 720, and a logic operation circuit 730. Among them,

[0120] The receiving circuit 710 is used to receive a signal to be processed and a chip select signal, and output an initial processed signal and an initial chip select signal;

[0121] The delay control circuit 720 is used to delay and perform logic control operations on the initial chip select signal to obtain a chip select shielding signal, and the pulse width of the chip select shielding signal is greater than or equal to two preset clock cycles;

[0122] The logic operation circuit 730 is used to perform invalid shielding processing on the initial processed signal according to the chip select shielding signal to obtain a target signal.

[0123] It should be noted that in the embodiment of the present application, the chip select signal is represented by CS_n, and the initial chip select signal is represented by CSB. Among them, the chip select signal may be a signal indicating whether the chip is selected, and the chip select signal is a low-level effective pulse signal, and the pulse width of the chip select signal is one preset clock cycle.

[0124] It should also be noted that in the embodiment of the present application, the signal to be processed may include at least one of the following: a command address signal and a clock signal; among them, the period of the clock signal is equal to the preset clock cycle.

[0125] Accordingly, the initial processing signal obtained after passing through the receiving circuit 710 may include one of the following: an initial command address signal and an initial clock signal.

[0126] Here, the receiving circuit 710 may be a receiver or a buffer. Additionally, the command address signal is represented by CMD / ADD, the initial command address signal is represented by CA; the clock signals are represented by CK_t and CK_c, and the initial clock signal is represented by CLK.

[0127] It should also be noted that in the embodiments of the present application, the chip select masking signal is represented by CS_Masking. Additionally, CS and CSB represent inverted signals, that is, CS_Masking can be regarded as the inverted signal of CSB_Masking.

[0128] In some embodiments, the logic operation circuit 730 is specifically configured to, when the initial processing signal is a signal corresponding to the target chip, mask the invalid signals in the initial processing signal according to the chip select masking signal; and / or, when the initial processing signal is a signal corresponding to a non-target chip, mask all of the initial processing signal according to the chip select masking signal;

[0129] Wherein, the target chip is the chip selected by the chip select signal, and the non-target chip is the chip not selected by the chip select signal.

[0130] It should be noted that for the target chip, that is, the selected chip, at this time the initial processing signal is valid, and it is necessary to pass the valid part through the chip select masking signal while masking the remaining invalid part; for the non-target chip, that is, the unselected chip, at this time the initial processing signal is invalid, and it is necessary to mask it all with the chip select masking signal.

[0131] It should also be noted that since the command address signal is a command based on two preset clock cycles, the pulse width of the chip select masking signal needs to be greater than or equal to two preset clock cycles to avoid losing the command address information in the second clock cycle.

[0132] In a possible implementation manner, when the signal to be processed is a command address signal, at this time, the chip select masking signal can be used to perform invalid masking processing on it. Refer to Figure 8A , in Figure 7 Based on the signal masking circuit 70 shown, the receiving circuit 710 may include a first receiving module 711 and a second receiving module 712, and the logic operation circuit 730 may include a first logic operation circuit 731; wherein,

[0133] The first receiving module 711 is configured to receive the command address signal and output an initial command address signal;

[0134] The second receiving module 712 is configured to receive the chip select signal and output an initial chip select signal;

[0135] The delay control circuit 720 is connected to the output end of the second receiving module 712 and is configured to perform delay and logic control operations on the initial chip select signal to obtain the chip select mask signal;

[0136] The first logic operation circuit 731 is connected to the output end of the delay control circuit 720 and the output end of the first receiving module 711, and is configured to perform a logic operation on the chip select mask signal and the initial command address signal to obtain a target command address signal.

[0137] It should be noted that in the embodiment of the present application, Figure 8A the initial command address signal is shielded by using the chip select mask signal. For the unselected chips, the initial command address signal is an invalid signal at this time, and all of them can be shielded by the first logic operation circuit 731. For the selected chips, the initial command address signal is a valid signal at this time, and the valid part thereof can be passed through by the first logic operation circuit 731, that is, the target command address signal is obtained. Here, the target command address signal can be represented by CMD / ADD_RPT.

[0138] In another possible implementation manner, when the signal to be processed is a clock signal, the chip select mask signal can be used to perform an invalid shielding process on it at this time. Refer to Figure 8B , in Figure 7 On the basis of the signal shielding circuit 70 shown, the receiving circuit 710 may include a third receiving module 713 and a fourth receiving module 714, and the logic operation circuit 730 may include a second logic operation circuit 732; wherein,

[0139] The third receiving module 713 is configured to receive the clock signal and output an initial clock signal;

[0140] The fourth receiving module 714 is configured to receive the chip select signal and output an initial chip select signal;

[0141] The delay control circuit 720 is connected to the output end of the fourth receiving module 714 and is configured to perform delay and logic control operations on the initial chip select signal to obtain the chip select mask signal;

[0142] The second logic operation circuit 732 is connected to the output end of the delay control circuit 720 and the output end of the third receiving module 713, and is configured to perform a logic operation on the chip select mask signal and the initial clock signal to obtain a target clock signal.

[0143] It should be noted that, in the embodiments of the present application, Figure 8B the initial clock signal is shielded by the chip select shielding signal. For the unselected chips, the initial clock signal is an invalid signal at this time, and it can be shielded by the second logic operation circuit 732. For the selected chips, the initial clock signal is a valid signal at this time, and the valid part of it can pass through the second logic operation circuit 732, that is, the target clock signal is obtained. Here, the target clock signal can be represented by PCLK0T_RPT.

[0144] In another possible implementation manner, when the signal to be processed is a command address signal and a clock signal, the chip select shielding signal can be used to perform invalid shielding processing on them respectively. Refer to Figure 8C , in Figure 7 Based on the signal shielding circuit 70 shown in, the receiving circuit 710 may include a first receiving module 711, a second receiving module 712, and a third receiving module 713, and the logic operation circuit 730 may include a first logic operation circuit 731 and a second logic operation circuit 732; wherein,

[0145] The first receiving module 711 is configured to receive the command address signal and output an initial command address signal;

[0146] The second receiving module 712 is configured to receive the chip select signal and output an initial chip select signal;

[0147] The third receiving module 713 is configured to receive the clock signal and output an initial clock signal;

[0148] The delay control circuit 720 is connected to the output end of the second receiving module 712 and is configured to perform delay and logic control operations on the initial chip select signal to obtain the chip select shielding signal;

[0149] The first logic operation circuit 731 is connected to the output end of the delay control circuit 720 and the output end of the first receiving module 711, and is configured to perform invalid shielding processing on the initial command address signal according to the chip select shielding signal to obtain a target command address signal; and

[0150] The second logic operation circuit 732 is connected to the output end of the delay control circuit 720 and the output end of the third receiving module 713, and is configured to perform a logic operation on the chip select shielding signal and the initial clock signal to obtain a target clock signal.

[0151] It should be noted that, in the embodiments of the present application, Figure 8CThe initial command address signal and the initial clock signal are masked by using the chip select masking signal. For the unselected chips, at this time, both the initial command address signal and the initial clock signal are invalid signals, and they can both be masked by the first logic operation circuit 731 and the second logic operation circuit 732. For the selected chips, at this time, both the initial command address signal and the initial clock signal are valid signals. The valid part of the initial command address signal can pass through the first logic operation circuit 731, that is, the target command address signal is obtained; and the valid part of the initial clock signal can pass through the second logic operation circuit 732, that is, the target clock signal is obtained.

[0152] It should also be noted that for the receiving circuit 710, whether it is the first receiving module, the second receiving module or the third receiving module, it can be regarded as a receiver or a buffer. In addition, the chip select masking signal is represented by CS_Masking, the target command address signal can be represented by CMD / ADD_RPT, and the target clock signal can be represented by PCLK0T_RPT.

[0153] Furthermore, in some embodiments, for the first logic operation circuit 731, based on the Figure 8A or Figure 8C signal masking circuit 70 shown, for details, see Figure 9A or Figure 9C , the first logic operation circuit 731 may include a first buffer 7311, a first AND gate 7312, and a second buffer 7313; wherein,

[0154] The first buffer 7311 is connected to the first receiving module 711 and is used to perform drive enhancement and delay processing on the initial command address signal to obtain a first command address signal;

[0155] The first AND gate 7312 is connected to the output end of the first buffer 7311 and the output end of the delay control circuit 720, and is used to perform an AND operation on the chip select masking signal and the first command address signal to obtain a second command address signal;

[0156] The second buffer 7313 is connected to the output end of the first AND gate 7312 and is used to perform drive enhancement and delay processing on the second command address signal to obtain the target command address signal.

[0157] That is to say, after obtaining the first command address signal and the chip select masking signal, a logic operation can be performed on them through the first AND gate 7312, and then through the drive enhancement and delay processing of the second buffer 7313, and the finally obtained target command address signal can be represented by CMD / ADD_RPT.

[0158] Further, in some embodiments, for the second logic operation circuit 732, based on the Figure 8B or Figure 8C signal shielding circuit 70 shown, for details, see Figure 9B or Figure 9C , the second logic operation circuit 732 may include a third buffer 7321, a second AND gate 7322, and a fourth buffer 7323; wherein,

[0159] The third buffer 7321 is connected to the third receiving module 713 and is used to perform driving enhancement and delay processing on the initial clock signal to obtain a first clock signal;

[0160] The second AND gate 7322 is connected to the output end of the third buffer 7321 and the output end of the delay control circuit 720, and is used to perform an AND operation on the chip select shielding signal and the first clock signal to obtain a second clock signal;

[0161] The fourth buffer 7323 is connected to the output end of the second AND gate 7322 and is used to perform driving enhancement and delay processing on the second clock signal to obtain the target clock signal.

[0162] That is to say, after obtaining the first clock signal and the chip select shielding signal, a logic operation can be performed on them through the second AND gate 7322, and then through the driving enhancement and delay processing of the fourth buffer 7323, and finally the obtained target clock signal can be represented by PCLK0T_RPT.

[0163] Further, in some embodiments, for the delay control circuit 720, based on the Figure 8A , Figure 8B or Figure 8C signal shielding circuit 70 shown, for details, see Figure 9A , Figure 9B or Figure 9C , the delay control circuit 720 may include a delay module 721, a pulse width adjustment module 722, a first inverter 723, and a first OR gate 724; wherein,

[0164] The first inverter 723 is used to perform an inversion process on the initial chip select signal to obtain a first intermediate signal;

[0165] The delay module 721 is used to perform a delay process on the initial chip select signal to obtain a second intermediate signal;

[0166] The pulse width adjustment module 722 is used to perform a pulse width expansion process on the second intermediate signal to obtain a third intermediate signal;

[0167] The first OR gate 724 is connected to the output terminal of the first inverter 723 and the output terminal of the pulse width adjustment module 722, and is used to perform an OR operation on the first intermediate signal and the third intermediate signal to obtain the chip select masking signal.

[0168] It should be noted that, in the embodiment of the present application, the first intermediate signal can be represented by CST, the second intermediate signal can be represented by B, and the third intermediate signal can be represented by CST_Shift. In this way, as shown in FIG. 9, after performing a logical operation on CST and CST_Shift through the first OR gate 724, the obtained chip select masking signal is represented by CS_Masking.

[0169] It should also be noted that, in the embodiment of the present application, the rising edge time of the chip select masking signal is earlier than the pulse start time of the first command address signal, and the falling edge time of the chip select masking signal is later than the pulse end time of the first command address signal; wherein, the chip select masking signal and the first command address signal correspond to the same valid pulse of the chip select signal.

[0170] Furthermore, in order to make the rising edge time of the chip select masking signal earlier than the pulse start time of the first command address signal and the falling edge time of the chip select masking signal later than the pulse end time of the first command address signal; in some embodiments, for the delay module 721, the delay module 721 may include a first delay unit 7211, a second delay unit 7212, and a second inverter 7213, and the second inverter 7213 is between the first delay unit 7211 and the second delay unit 7212; wherein,

[0171] The first delay unit 7211 is used to perform a first delay process on the initial chip select signal to obtain a first delay signal;

[0172] The second inverter 7213 is used to perform an inversion process on the first delay signal to obtain an inverted delay signal;

[0173] The second delay unit 7212 is used to perform a second delay process on the inverted delay signal to obtain the second intermediate signal.

[0174] Furthermore, in some embodiments, for the pulse width adjustment module 722, the pulse width adjustment module 722 may include a fifth buffer 7221 and a second OR gate 7222; wherein,

[0175] The fifth buffer 7221 is connected to the output terminal of the delay module 721, and is used to perform drive enhancement and delay processing on the second intermediate signal to obtain a fourth intermediate signal;

[0176] A second OR gate 7222 is connected to the output terminal of the delay module 721 and the output terminal of the fifth buffer 7221, and is configured to perform an OR operation on the second intermediate signal and the fourth intermediate signal to obtain the third intermediate signal.

[0177] It should be noted that, in the embodiment of the present application, both the first delay unit 7211 and the second delay unit 7212 are composed of a resistor R and a capacitor C, that is, two groups of RC delay networks can be adopted in the embodiment of the present application to implement. Exemplarily, the first delay unit 7211 may be composed of a first resistor R1 and a first capacitor C1, the second delay unit 7212 may be composed of a second resistor R2 and a second capacitor C2, and the second inverter 7213 is connected in series between the first resistor R1 and the second resistor R2.

[0178] It should also be noted that, in the embodiment of the present application, the pulse width adjustment module 722 can determine the pulse width expansion width of the third intermediate signal, and the specific expansion size is determined by the design requirements. In addition, the inverted delay signal obtained through the second inverter 7213 can be represented by A, the second intermediate signal obtained through the second delay unit 7212 can be represented by B, the fourth intermediate signal obtained through the fifth buffer 7221 can be represented by C, and the third intermediate signal obtained through the second OR gate 7222 can be represented by CST_Shift.

[0179] In a specific example, Figure 10 shows a signal timing diagram of a signal shielding circuit 70 provided by the embodiment of the present application. As Figure 10 shown, CA is an initial command address signal based on two preset clock cycles, and the valid information it includes is CA0 and CA2; CSB is a pulse signal with a low level being valid, and the pulse width is one preset clock cycle. Then, after the inversion processing by the first inverter 723, the obtained CST signal is a pulse signal with a high level being valid, and the pulse width is still one preset clock cycle; and after the logical operation processing by the delay module 721 and the pulse width adjustment module 722, the obtained CST_Shift signal is a pulse signal with a high level being valid, and the pulse width is much larger than one preset clock cycle; thus, after performing an OR operation on the CST signal and the CST_Shift signal through the first OR gate 724, the obtained CS_Masking signal is a pulse signal with a high level being valid, and the pulse width is already greater than or equal to two preset clock cycles, so that CA0 and CA2 can pass through to obtain the CMD / ADD_RPT signal.

[0180] That is to say, the embodiment of the present application can adopt the RC delay network method and combine it with the logic control method to ensure the sufficiency of t1 / t2. Among them, the delay of the RC network is less than a preset clock cycle (i.e., 1tCK). According to speed and design requirements, two groups of RC networks can be adopted here to ensure the integrity of the CSB signal. Specifically, while ensuring the delay, an inverter (i.e., the second inverter 7213) can be added between the two groups of RC delay networks, effectively protecting the integrity of the CSB information; in addition, the RC network can achieve the required delay with almost no extra current consumption, and using the pulse width adjustment module 722 can ensure that t2 has sufficient margin.

[0181] This embodiment provides a signal shielding circuit, which includes a receiving circuit, a delay control circuit, and a logic operation circuit; wherein, the receiving circuit is used to receive the signal to be processed and the chip select signal, and output an initial processed signal and an initial chip select signal; the delay control circuit is used to delay and perform logic control operations on the initial chip select signal to obtain a chip select shielding signal, and the pulse width of the chip select shielding signal is greater than or equal to two preset clock cycles; the logic operation circuit is used to perform invalid shielding processing on the initial processed signal according to the chip select shielding signal to obtain a target signal. In this way, since the command address signal in the DDR5 DRAM is a signal based on two preset clock cycles, and the pulse width of the chip select shielding signal proposed in the present application is greater than or equal to two preset clock cycles, when shielding the initial processed signal, it is possible to ensure that the DDR5 DRAM does not lose valid information while maximizing the avoidance of current waste and achieving the purpose of power consumption saving.

[0182] In another embodiment of the present application, based on the signal shielding circuit 70 described in the foregoing embodiment, after obtaining the target command address signal and the target clock signal, decoding processing can also be performed on the target command address signal. Taking Figure 8C the signal shielding circuit 70 shown as an example, see Figure 11 , on the basis of the Figure 8C signal shielding circuit 70 shown, the signal shielding circuit 70 may further include a buffer module 740, and the buffer module 740 may be composed of several sixth buffers 741; wherein,

[0183] The buffer module 740 is used to sequentially perform drive enhancement and delay processing on the initial chip select signal according to several sixth buffers 741 to obtain a target chip select signal.

[0184] It should be noted that as Figure 10As shown, the buffer module 740 can be composed of three sixth buffers, and the driving capabilities of these three sixth buffers can be the same or different (such as gradually increasing); the obtained target chip select signal can be represented by CSBI.

[0185] It should also be noted that in the embodiments of the present application, whether it is the first buffer, the second buffer, the third buffer, or the fourth buffer, the fifth buffer, or the sixth buffer, etc., any one buffer can be composed of two inverters, so the buffer can also be called a Repeater, abbreviated as RPT.

[0186] Furthermore, in some embodiments, as Figure 11 shown, the signal shielding circuit 70 can further include a sampling circuit 750 and a decoding circuit 760; wherein,

[0187] The sampling circuit 750 is configured to receive the target command address signal, the target clock signal, and the target chip select signal, and sample the target command address signal and the target chip select signal by using the target clock signal to obtain a sampled command address signal and a sampled chip select signal;

[0188] The decoding circuit 760 is connected to the output end of the sampling circuit 750, and decodes the sampled chip select signal and the sampled command address signal to obtain a target command result.

[0189] It should be noted that in the embodiments of the present application, the sampling circuit 750 can be composed of several D-type flip-flops. In addition, the decoding circuit 760 can include a third inverter and a third AND gate (not shown in the figure); wherein,

[0190] The third inverter is configured to perform an inversion process on the sampled chip select signal to obtain an inverted sampled chip select signal;

[0191] The third AND gate is configured to perform an AND operation on the inverted sampled chip select signal and the sampled command address signal to obtain the target command result.

[0192] It should also be noted that in the embodiments of the present application, the sampled chip select signal can be represented by CS_INTER, the sampled command address signal can be represented by CMD / ADD_INTER, and the target command result can be represented by CMD.

[0193] The signal shielding circuit proposed in the embodiments of the present application can reduce power consumption as much as possible while ensuring performance. The following will be described in detail in combination with two specific circuit structures.

[0194] In a specific example, refer to Figure 12, which shows a schematic diagram of the specific circuit structure of a signal shielding circuit 70 provided by an embodiment of the present application. As Figure 12 shown, the signal shielding circuit 70 may include a first receiver 1201, a second receiver 1202, a third receiver 1203, a first buffer 1204, a first AND gate 1205, a second buffer 1206, a third buffer 1207, a fourth buffer 1208, a fifth buffer 1209, a first inverter 1210, a second inverter 1211, a first resistor R1, a first capacitor C1, a second resistor R2, a second capacitor C2, a sixth buffer 1212, a first OR gate 1213, a second OR gate 1214, a seventh buffer 1215, an eighth buffer 1216, a ninth buffer 1217, a sampling circuit 1218, and a decoding circuit 1219. Among them, the first receiver 1201, the second receiver 1202, and the third receiver 1203 may also be buffers, and the sampling circuit 1218 may be composed of several D-type flip-flops. In addition, the first buffer 1204, the first AND gate 1205, and the second buffer 1206 form a first logic operation circuit, the first resistor R1 and the first capacitor C1 form a first delay unit, the second resistor R2 and the second capacitor C2 form a second delay unit, and the sixth buffer 1212 and the first OR gate 1213 form a pulse width adjustment module.

[0195] According to Figure 12 the signal shielding circuit 70 shown, this circuit uses the chip select shielding signal to shield the command address signal, thereby avoiding current waste and achieving the purpose of saving power consumption.

[0196] Refer to Figure 13A , which shows Figure 12 a signal timing diagram of the signal shielding circuit 70 shown when the command address signal is a valid signal. Among them, the initial command address signal output by the first receiver 1201 is represented by CA, and its valid part includes two preset clock cycles (CA0 and CA2); the initial chip select signal output by the second receiver 1202 is represented by CSB0, which is a low-level effective pulse signal, and the pulse width is one preset clock cycle; the initial clock signal output by the third receiver 1203 is represented by CLK; after the CSB0 signal is inverted by the first inverter 1210, the obtained signal is represented by CST, which is a high-level effective pulse signal at this time; after the CSB0 signal passes through the first delay network composed of the first resistor R1 and the first capacitor C1, the obtained signal is represented by CSB_Delay, and from Figure 13A it can be seen that CSB_Delay has a certain delay with CSB0; after the CSB_Delay signal is inverted by the second inverter 1211, the obtained signal is represented by A, and from Figure 13AIt can be seen that the A signal is a high-level active pulse signal. Since the second inverter 1211 has the effect of enhancing the signal driving ability, the signal integrity of the A signal is greatly improved compared with CSB_Delay at this time; further, after the A signal passes through the second delay network composed of the second resistor R2 and the second capacitor C2, the obtained signal is represented by B; from Figure 13A It can be seen that the B signal is still a high-level active pulse signal, and there is a certain time delay between the B signal and the A signal; further, after the B signal passes through the driving enhancement and time delay processing of the sixth buffer 1212, the obtained signal is represented by C; after the B signal and the C signal pass through the OR operation of the first OR gate 1213, the pulse width of the signal can be broadened. At this time, the obtained signal is represented by CST_Shift. From Figure 13A It can be seen that the pulse width of the CST_Shift signal is broadened to a certain extent, and the rising edge of the pulse is affected by the rising edge of the B signal, and the falling edge of the pulse is affected by the falling edge of the C signal; further, after the CST signal and the CST_Shift signal pass through the OR operation of the second OR gate 1214, the obtained signal is represented by CS_Masking. From Figure 13A It can be seen that the pulse width of the CS_Masking signal has been broadened to be greater than or equal to two preset clock cycles, and the rising edge of the pulse is affected by the rising edge of the CST signal, and the falling edge of the pulse is affected by the falling edge of the CST_Shift signal. In this way, after the CA signal passes through the driving enhancement and time delay processing of the first buffer 1204, the obtained first command address signal is represented by CA1. When the CA1 signal is invalidly masked by using the CS_Masking signal in this way, within the time period when the CS_Masking signal is at a high level, both CA0 and CA2 can pass through. At this time, the obtained signal is the target command address signal, represented by CMD / ADD_RPT.

[0197] See Figure 13B which shows Figure 12 a signal timing diagram of the signal masking circuit 70 shown when the command address signal is an invalid signal. As Figure 13BAs shown, at this time, the initial chip select signal output by the second receiver 1202 is represented by CSB1, which is a high-level signal (represented by H); after the CSB1 signal is inverted by the first inverter 1210, the obtained CST signal is a low-level signal (represented by L); moreover, the CST_Shift signal obtained after the CSB1 signal passes through the first resistor R1, the first capacitor C1, the second inverter 1211, the second resistor R2, the second capacitor C2, the sixth buffer 1212, and the first OR gate 1213 is still a low-level signal, resulting in all command address signals being masked, that is, the obtained target command address signal (CMD / ADD_RPT) is a low-level signal (represented by L).

[0198] It should be noted that Figure 13A represents the situation where the chip is selected, Figure 13B represents the situation where the chip is not selected; therefore, Figure 13A CSB0 in Figure 13B is a low-level effective pulse signal, while

[0199] CSB1 in Figure 14 is a high-level signal, which are respectively used to represent that the chip is selected and the chip is not selected. Figure 14 In another specific example, referring to Figure 12 shows a schematic diagram of the specific circuit structure of another signal masking circuit 70 provided by an embodiment of the present application. As Figure 12 shown, based on the signal masking circuit 70 shown in

[0200] According to Figure 14 the signal masking circuit 70 shown, this circuit can not only mask the command address signal by using the chip select masking signal, but also mask the clock signal by using the chip select masking signal, so as to further avoid current waste and achieve the purpose of saving power consumption.

[0201] Referring to Figure 15A which shows Figure 14A signal timing diagram of the signal shielding circuit 70 shown when the command address signal is a valid signal. Among them, the initial command address signal output by the first receiver 1201 is represented by CA, and its valid part includes two preset clock cycles (CA0 and CA2); the initial chip select signal output by the second receiver 1202 is represented by CSB0, which is a low-level active pulse signal, and the pulse width is one preset clock cycle; the initial clock signal output by the third receiver 1203 is represented by CLK; after the CSB0 signal is inverted by the first inverter 1210, the obtained signal is represented by CST, which is a high-level active pulse signal at this time; after the CSB0 signal passes through the first delay network composed of the first resistor R1 and the first capacitor C1, the obtained signal is represented by CSB_Delay, from Figure 15A it can be seen that there is a certain delay between CSB_Delay and CSB0; after the CSB_Delay signal is inverted by the second inverter 1211, the obtained signal is represented by A, from Figure 15A it can be seen that the A signal is a high-level active pulse signal. Since the second inverter 1211 has the function of enhancing the signal driving ability, the signal integrity of the A signal is greatly improved compared with CSB_Delay at this time; further, after the A signal passes through the second delay network composed of the second resistor R2 and the second capacitor C2, the obtained signal is represented by B; from Figure 15A it can be seen that the B signal is still a high-level active pulse signal, and there is a certain delay between the B signal and the A signal; further, after the B signal passes through the driving enhancement and delay processing of the sixth buffer 1212, the obtained signal is represented by C; after the B signal and the C signal pass through the OR operation of the first OR gate 1213, the pulse width of the signal can be widened, and the obtained signal is represented by CST_Shift at this time, from Figure 15A it can be seen that the pulse width of the CST_Shift signal is widened to a certain extent, and the rising edge of the pulse is affected by the rising edge of the B signal, and the falling edge of the pulse is affected by the falling edge of the C signal; further, after the CST signal and the CST_Shift signal pass through the OR operation of the second OR gate 1214, the obtained signal is represented by CS_Masking, from Figure 15AIt can be seen that the pulse width of the CS_Masking signal has been widened to be greater than or equal to two preset clock cycles, and the rising edge of this pulse is affected by the rising edge of the CST signal, and the falling edge of this pulse is affected by the falling edge of the CST_Shift signal. In this way, after the CA signal is enhanced in driving and delayed by the first buffer 1204, the obtained first command address signal is represented by CA1. When using the CS_Masking signal to perform an invalid masking process on the CA1 signal, within the time period when the CS_Masking signal is at a high level, both CA0 and CA2 can pass through. At this time, the obtained signal is the target command address signal, represented by CMD / ADD_RPT. In addition, the initial clock signal output by the third receiver 1203 is represented by CLK. After the CLK signal is enhanced in driving and delayed by the tenth buffer 1301, the obtained first clock signal is represented by PCLK0T. When using the CS_Masking signal to perform an invalid masking process on the PCLK0T signal, within the time period when the CS_Masking signal is at a high level, the valid part can pass through. At this time, the obtained signal is the target clock signal, represented by PCLK0T_RPT; while in other time periods when the CS_Masking signal is at a low level, the target clock signal is masked.

[0202] See Figure 15B , which shows Figure 14 A signal timing diagram of the signal masking circuit 70 when the command address signal is an invalid signal. As Figure 15B shown, at this time, the initial chip select signal output by the second receiver 1202 is represented by CSB1, which is a high-level signal (represented by H); after the CSB1 signal is inverted by the first inverter 1210, the obtained CST signal is a low-level signal (represented by L); and the CST_Shift signal obtained after the CSB1 signal passes through the first resistor R1, the first capacitor C1, the second inverter 1211, the second resistor R2, the second capacitor C2, the sixth buffer 1212, and the first OR gate 1213 is still a low-level signal, resulting in all command address signals being masked, that is, the obtained target command address signal (CMD / ADD_RPT) is a low-level signal (represented by L), and the target clock signal (PCLK0T_RPT) is also a low-level signal (represented by L).

[0203] It should be noted that Figure 15A represents the situation where the chip is selected, Figure 15B represents the situation where the chip is not selected; therefore, Figure 15A the CSB0 in Figure 15B is a low-level effective pulse signal, while the CSB1 in is a high-level signal, respectively used to characterize that the chip is selected and the chip is not selected.

[0204] That is to say, the chip select signal is a signal indicating whether the chip is selected. Among them, for the unselected chip, at this time, the command address signal / clock signal is an invalid signal, while the chip select signal is always at a high level, making the chip select mask signal always at a low level, so that both the command address signal and the clock signal can be masked. For the selected chip, at this time, the command address signal / clock signal is a valid signal, and the chip select signal is a pulse signal with low-level validity, making the chip select mask signal also a pulse signal, and it is valid at a high level, and the pulse width is greater than or equal to two preset clock cycles; in this way, for the command address signal, within the high-level time period of the chip select mask signal, the valid part in the command address signal can pass through, that is, the target command address signal is obtained. Since the command address signal has only two preset clock cycles, there is no masking situation; for the clock signal, within the high-level time period of the chip select mask signal, the valid part in the clock signal can pass through, that is, the target clock signal is obtained; however, in other time periods of the chip select mask signal, the clock signal is masked.

[0205] This embodiment provides a signal masking circuit. Through this embodiment, the specific implementation of the foregoing embodiment is elaborated in detail. It can be seen that through the technical solution of the foregoing embodiment, since the command address signal in the DDR5 DRAM is a signal based on two preset clock cycles, and the pulse width of the chip select mask signal proposed in this application is greater than or equal to two preset clock cycles, when masking the initial processing signal, it is possible to ensure that the DDR5 DRAM does not lose valid information while maximizing the avoidance of current waste and achieving the purpose of saving power consumption.

[0206] In another embodiment of the present application, refer to Figure 16 , which shows a schematic structural diagram of a semiconductor memory 160 provided by an embodiment of the present application. As Figure 16 shown, the semiconductor memory 160 may include the signal masking circuit 70 described in any one of the foregoing embodiments.

[0207] In the embodiment of the present application, the semiconductor memory 160 may be a DRAM chip.

[0208] Further, in some embodiments, the DRAM chip conforms to the DDR5 memory specification.

[0209] In the embodiments of the present application, the chip select signal is part of the identification of CMD information in DDR5. However, the chip select signal is a low-level active pulse signal with a pulse width of one preset clock cycle, while the command address signal in the DDR5 DRAM is based on a signal of two preset clock cycles. To avoid losing the CA information in the second clock cycle and causing CMD decoding failure, the semiconductor memory 160 proposed in the embodiments of the present application includes a signal shielding circuit 70.

[0210] In this way, by using the signal shielding circuit 70, the pulse width of the chip select shielding signal can be made greater than or equal to two preset clock cycles. Thus, when performing shielding processing on the initial processing signal, while ensuring that the DDR5 DRAM does not lose valid information, it can also maximize the avoidance of current waste and achieve the purpose of power consumption savings.

[0211] The above are only the preferred embodiments of the present application and are not used to limit the protection scope of the present application.

[0212] It should be noted that in the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0213] The serial numbers of the above embodiments of the present application are only for description and do not represent the superiority or inferiority of the embodiments.

[0214] The methods disclosed in several method embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments.

[0215] The features disclosed in several product embodiments provided by the present application can be arbitrarily combined without conflict to obtain new product embodiments.

[0216] The features disclosed in several method or device embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0217] The above are only the specific implementation manners of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A signal shielding circuit, characterized in that, The signal shielding circuit includes a receiving circuit, a delay control circuit, and a logic operation circuit; wherein, The receiving circuit is configured to receive a signal to be processed and a chip select signal, and output an initial processed signal and an initial chip select signal; The delay control circuit is configured to perform delay and logic control operations on the initial chip select signal to obtain a chip select shielding signal, and the pulse width of the chip select shielding signal is greater than or equal to two preset clock cycles; The logic operation circuit is configured to perform invalid shielding processing on the initial processed signal according to the chip select shielding signal to obtain a target signal; The delay control circuit includes a delay module, a pulse width adjustment module, a first inverter, and a first OR gate; wherein, The first inverter is configured to invert the initial chip select signal to obtain a first intermediate signal; The delay module is configured to perform delay processing on the initial chip select signal to obtain a second intermediate signal; The pulse width adjustment module is configured to perform pulse width expansion processing on the second intermediate signal to obtain a third intermediate signal; The first OR gate is connected to the output end of the first inverter and the output end of the pulse width adjustment module, and is configured to perform an OR operation on the first intermediate signal and the third intermediate signal to obtain the chip select shielding signal; The delay module includes a first delay unit, a second delay unit, and a second inverter, and the second inverter is between the first delay unit and the second delay unit; wherein, The first delay unit is configured to perform a first delay processing on the initial chip select signal to obtain a first delayed signal; The second inverter is configured to invert the first delayed signal to obtain an inverted delayed signal; The second delay unit is configured to perform a second delay processing on the inverted delayed signal to obtain the second intermediate signal; Both the first delay unit and the second delay unit are composed of a resistor R and a capacitor C.

2. The signal shielding circuit according to claim 1, wherein The chip select signal is a signal indicating whether a chip is selected, and the chip select signal is a low-level effective pulse signal, and the pulse width of the chip select signal is one preset clock cycle.

3. The signal shielding circuit according to claim 2, wherein The logic operation circuit is specifically configured to, when the initial processed signal is a signal corresponding to a target chip, perform shielding processing on the invalid signals in the initial processed signal according to the chip select shielding signal; and / or, when the initial processed signal is a signal corresponding to a non-target chip, perform shielding processing on all of the initial processed signal according to the chip select shielding signal; Wherein, the target chip is the chip selected by the chip select signal, and the non-target chip is the chip not selected by the chip select signal.

4. The signal shielding circuit according to claim 3, wherein, The signal to be processed includes at least one of the following: a command address signal and a clock signal; wherein, the period of the clock signal is equal to the preset clock cycle.

5. The signal shielding circuit according to claim 4, wherein When the signal to be processed is a command address signal, the receiving circuit includes a first receiving module and a second receiving module, and the logic operation circuit includes a first logic operation circuit; wherein, The first receiving module is configured to receive the command address signal and output an initial command address signal; The second receiving module is configured to receive the chip select signal and output an initial chip select signal; The delay control circuit is connected to the output end of the second receiving module and is configured to perform a delay and logical control operation on the initial chip select signal to obtain the chip select mask signal; The first logic operation circuit is connected to the output end of the delay control circuit and the output end of the first receiving module and is configured to perform a logic operation on the chip select mask signal and the initial command address signal to obtain a target command address signal.

6. The signal shielding circuit according to claim 4, characterized in that, When the signal to be processed is a clock signal, the receiving circuit includes a third receiving module and a fourth receiving module, and the logic operation circuit includes a second logic operation circuit; wherein, The third receiving module is configured to receive the clock signal and output an initial clock signal; The fourth receiving module is configured to receive the chip select signal and output an initial chip select signal; The delay control circuit is connected to the output end of the fourth receiving module and is configured to perform a delay and logical control operation on the initial chip select signal to obtain the chip select mask signal; The second logic operation circuit is connected to the output end of the delay control circuit and the output end of the third receiving module and is configured to perform a logic operation on the chip select mask signal and the initial clock signal to obtain a target clock signal.

7. The signal shielding circuit according to claim 4, characterized in that, When the signal to be processed is a command address signal and a clock signal, the receiving circuit includes a first receiving module, a second receiving module and a third receiving module, and the logic operation circuit includes a first logic operation circuit and a second logic operation circuit; wherein, The first receiving module is configured to receive the command address signal and output an initial command address signal; The second receiving module is configured to receive the chip select signal and output an initial chip select signal; The third receiving module is configured to receive the clock signal and output an initial clock signal; The delay control circuit is connected to the output end of the second receiving module and is configured to perform a delay and logical control operation on the initial chip select signal to obtain the chip select mask signal; The first logic operation circuit is connected to the output end of the delay control circuit and the output end of the first receiving module and is configured to perform an invalid masking process on the initial command address signal according to the chip select mask signal to obtain a target command address signal; and The second logic operation circuit is connected to the output end of the delay control circuit and the output end of the third receiving module and is configured to perform a logic operation on the chip select mask signal and the initial clock signal to obtain a target clock signal.

8. The signal shielding circuit according to claim 5 or 7, characterized in that, The first logic operation circuit includes a first buffer, a first AND gate and a second buffer; wherein, The first buffer is connected to the first receiving module and is configured to perform a drive enhancement and delay process on the initial command address signal to obtain a first command address signal; The first AND gate is connected to the output terminal of the first buffer and the output terminal of the delay control circuit, and is used for performing an AND operation on the chip select mask signal and the first command address signal to obtain a second command address signal; The second buffer is connected to the output terminal of the first AND gate, and is used for driving enhancement and delay processing of the second command address signal to obtain the target command address signal.

9. The signal shielding circuit according to claim 6 or 7, characterized in that The second logic operation circuit includes a third buffer, a second AND gate, and a fourth buffer; wherein, The third buffer is connected to the third receiving module, and is used for driving enhancement and delay processing of the initial clock signal to obtain a first clock signal; The second AND gate is connected to the output terminal of the third buffer and the output terminal of the delay control circuit, and is used for performing an AND operation on the chip select mask signal and the first clock signal to obtain a second clock signal; The fourth buffer is connected to the output terminal of the second AND gate, and is used for driving enhancement and delay processing of the second clock signal to obtain the target clock signal.

10. The signal shielding circuit according to claim 1, characterized in that, The pulse width adjustment module includes a fifth buffer and a second OR gate; wherein, The fifth buffer is connected to the output terminal of the delay module, and is used for driving enhancement and delay processing of the second intermediate signal to obtain a fourth intermediate signal; The second OR gate is connected to the output terminal of the delay module and the output terminal of the fifth buffer, and is used for performing an OR operation on the second intermediate signal and the fourth intermediate signal to obtain the third intermediate signal.

11. The signal shielding circuit according to claim 7, wherein The signal shielding circuit further includes a buffer module, and the buffer module is composed of a plurality of sixth buffers; wherein, The buffer module is used for driving enhancement and delay processing of the initial chip select signal in sequence according to the plurality of sixth buffers to obtain a target chip select signal.

12. The signal shielding circuit according to claim 11, wherein The signal shielding circuit further includes a sampling circuit and a decoding circuit; wherein, The sampling circuit is used for receiving the target command address signal, the target clock signal, and the target chip select signal, and sampling the target command address signal and the target chip select signal by using the target clock signal to obtain a sampled command address signal and a sampled chip select signal; The decoding circuit is connected to the output terminal of the sampling circuit, and decodes the sampled chip select signal and the sampled command address signal to obtain a target command result.

13. The signal shielding circuit according to claim 12, wherein The sampling circuit is composed of a plurality of D flip-flops.

14. The signal shielding circuit according to claim 8, 9, 10 or 11, characterized in that, The buffer is composed of two inverters.

15. The signal shielding circuit according to claim 8, wherein The rising edge time of the chip select mask signal is earlier than the pulse start time of the first command address signal; the falling edge time of the chip select mask signal is later than the pulse end time of the first command address signal; wherein, the chip select mask signal and the first command address signal correspond to the same valid pulse of the chip select signal.

16. A semiconductor memory, characterized in that, It includes the signal shielding circuit according to any one of claims 1 to 15.

17. The semiconductor memory according to claim 16, wherein, The semiconductor memory is a dynamic random access memory DRAM chip.

18. The semiconductor memory according to claim 17, wherein The dynamic random access memory DRAM chip complies with the DDR5 memory specification.

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