Solution to avoid fc package from generating chip layer crack due to stress and structure thereof

Abstract

The application provides a solution method and structure for avoiding FC packaging chip layer cracks caused by stress, which comprises the following steps: according to the assumption of a redistribution layer growth stress optical film stress model, when the thickness of the redistribution layer is greater than or equal to 10 microns, the redistribution layer growth stress is proportional to the thickness of the redistribution layer, and the internal stress of the redistribution layer increases with the increase of the thickness of the redistribution layer; the thickness of the redistribution layer is reduced from 10 microns to 3-8 microns to reduce the stress on the chip circuit layer; the process method is simple, the influence of the internal stress of the redistribution layer film on the product is effectively reduced, the problem of chip metal layer crack abnormality leading to failure is avoided, and the loss caused by the product failure due to the structural damage of the silicon-based chip is effectively avoided.

Description

Technical Field

[0001] This invention relates to the field of FC packaging technology, and specifically to a solution and structure for avoiding chip layer cracks caused by stress in FC packaging. Background Technology

[0002] The growing demand for lighter, thinner, smaller, more reliable, and lower-cost electronic devices, coupled with the inherent low signal inductance and faster transmission speeds of flip chips (FC), has led to the widespread adoption of FC packaging technology in chip packaging. FC packaging offers greater cost-effectiveness compared to traditional surface-mount component packaging.

[0003] However, existing FC packaging has the following technical problems:

[0004] 1) The chip has a high failure rate on the customer's production line. Failure analysis revealed cracks at fixed locations on the chip surface (see attached manual). Figure 1 The abnormal phenomenon shown is mainly caused by the redistribution layer (RDL) having a hooked shape at the corners. Under the high temperature stress of reflow, the chip is heated in the later process, resulting in uneven stress and abnormal cracking of the metal layer, which leads to failure.

[0005] 2) The stress within the redistribution layer (RDL) film has the greatest impact on the chip surface stress. The stress's effect on the product begins during electroplating; excessive stress can damage the fragile silicon-based chip structure, leading to product failure. The redistribution layer (RDL) stress originates from both thermal stress and intrinsic stress. Thermal stress is primarily caused by the difference in thermal expansion coefficients between the RDL film and the substrate. Intrinsic stress is mainly caused by two factors: 1) mismatch between the film structure and the substrate structure at the interface; 2) structural defects formed during the electrocrystallization process. The stress within the redistribution layer (RDL) film has an impact on the product since the electroplating process began. Excessive stress can damage the fragile silicon-based chip structure, leading to product failure. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a solution and structure for preventing chip layer cracks caused by stress in FC packaging. The process is simple, effectively reduces the impact of internal stress in the redistribution layer film on the product, avoids failure caused by abnormal cracks in the chip metal layer, and effectively prevents product failure due to structural damage to silicon-based chips.

[0007] To achieve the above objectives, the technical solution of the present invention is as follows:

[0008] A solution to avoid chip layer cracks caused by stress in FC packaging includes the following steps: based on the assumptions of the optical thin film stress model of redistribution layer growth stress, when the redistribution layer thickness is ≥10μm, the redistribution layer growth stress is proportional to the redistribution layer thickness, and the stress in the redistribution layer increases with the increase of the redistribution layer thickness. The redistribution layer thickness is reduced from 10μm to 3-8μm to reduce the stress on the chip circuit layer.

[0009] This invention provides a solution and structure for avoiding chip layer cracks caused by stress in FC packaging. The process is simple, effectively reduces the impact of internal stress in the redistribution layer film on the product, avoids the problem of failure caused by abnormal cracks in the chip metal layer, and effectively avoids product failure caused by structural damage to silicon-based chips.

[0010] As a preferred technical solution, the connection between the redistribution layer and the oxide layer has no corners.

[0011] As a preferred technical solution, the redistribution layer is a copper thin film electrodeposited on a silicon substrate.

[0012] The present invention also provides a structure to avoid chip layer cracks caused by stress in FC packaging, comprising: a silicon substrate, wherein a redistribution layer is provided on the silicon substrate, and the thickness of the redistribution layer is 3-8 μm.

[0013] As a preferred technical solution, one side of the redistribution layer is connected to one side of the oxide layer, and there is no corner structure at the connection between the redistribution layer and the circuit layer of the oxide layer.

[0014] As a preferred technical solution, the other side of the oxide layer is connected to the silicon substrate.

[0015] As a preferred technical solution, the other side of the redistribution layer is connected to the side of the welding protrusion.

[0016] As a preferred technical solution, the other side of the welding bump is connected to the tin-silver layer.

[0017] As a preferred technical solution, one side of the oxide layer is also connected to multiple top metal parts.

[0018] As a preferred technical solution, the welding protrusion is a copper pillar.

[0019] This invention provides a solution and structure for avoiding chip layer cracks caused by stress in FC packaging. The process is simple, effectively reduces the impact of internal stress in the redistribution layer film on the product, avoids the problem of failure caused by abnormal cracks in the chip metal layer, and effectively avoids product failure caused by structural damage to silicon-based chips. Attached Figure Description

[0020] Figure 1 The background technology chip has a high failure rate on the customer's production line. Failure analysis revealed an abnormal phenomenon: cracks were found at fixed locations on the chip surface.

[0021] Figure 2 This is a schematic diagram illustrating the stress simulation verification of this invention using ANSYS.

[0022] Figure 3 A schematic diagram of a structure to prevent chip layer cracks caused by stress in FC packaging;

[0023] Figure 4 The maximum principal stress cloud map provided for this invention (the thickness of the redistribution layer is 10 μm);

[0024] Figure 5 The maximum principal stress cloud map provided for this invention (the thickness of the redistribution layer is 5 μm);

[0025] Figure 6 The maximum principal stress cloud diagram provided for this invention (no corners at the connection between the redistribution layer and the oxide layer in the circuit layer);

[0026] Figure 7 For low current density (2A / dm) 2 A graph showing the relationship between stress within the redistribution layer and the thickness of the redistribution layer.

[0027] Figure 8 SEM image of the fixed position on the chip surface after the solution provided by the present invention to avoid chip layer cracks caused by stress in FC packaging;

[0028] Among them, 1-redistribution layer; 2-oxide layer; 3-silicon substrate; 4-welding bump; 5-tin-silver layer; 6-top metal part. Detailed Implementation

[0029] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0030] It is understood that the present invention achieves its purpose through some embodiments.

[0031] like Figure 3As shown, this invention provides a structure to avoid chip layer cracks caused by stress in FC packaging, comprising: a redistribution layer 1 with a thickness of 3-8 μm; one side of the redistribution layer 1 is connected to one side of an oxide layer 2, and there are no corners at the connection between the redistribution layer 1 and the circuit layer of the oxide layer 2; the other side of the oxide layer 2 is connected to a silicon substrate 3; the other side of the redistribution layer 1 is connected to one side of a solder bump 4; the other side of the solder bump 4 is connected to a tin-silver layer 5; a plurality of top metal portions 6 are also connected to one side of the oxide layer 2; the solder bump 4 is a copper pillar; its structure is simple, effectively reducing the impact of internal stress in the redistribution layer film on the product, avoiding the problem of failure caused by abnormal cracks in the chip metal layer, and effectively avoiding product failure caused by structural damage to the silicon-based chip.

[0032] like Figure 2 As shown, ANSYS stress simulation confirmed the following: reducing the thickness of redistribution layer 1 from 10µm to 5µm reduces the impact of internal stress in redistribution layer 1 on the product, resulting in a 13.1% reduction in stress on the chip circuit layer; simulation analysis results show that: Figure 4 As shown, when the thickness of redistribution layer 1 is 10 μm, the internal stress of redistribution layer 1 increases with the increase of redistribution layer thickness. An abnormal phenomenon was observed: cracks were found at fixed locations on the chip surface. This abnormality caused structural damage to the fragile silicon-based chip, resulting in product failure. Figure 5 As shown, when the thickness of the redistribution layer 1 in this application is reduced to 5 μm, the stress on the chip circuit layer decreases dramatically. This effectively avoids the problem of failure caused by abnormal cracks in the chip circuit layer, and prevents structural damage to the fragile silicon-based chip, thus avoiding product failure. Figure 6 As shown, when there is no corner at the connection between the redistribution layer 1 and the oxide layer 2, the stress on the chip circuit layer will be reduced sharply. This can effectively avoid the problem of failure caused by abnormal cracks in the chip circuit layer and prevent structural damage to the fragile silicon-based chip, which could lead to product failure.

[0033] like Figure 7 As shown, from a low current density (2A / dm²) 2 In the curve showing the relationship between the internal stress of the redistribution layer and the thickness of the redistribution layer, we can observe that when the thickness of redistribution layer 1 is thin, the internal stress of redistribution layer 1 decreases with the increase of the thickness of redistribution layer 1. When the thickness of redistribution layer 1 is large (≥10μm), the internal stress of redistribution layer 1 increases with the increase of the thickness of redistribution layer 1. Reducing the thickness of redistribution layer 1 from 10μm to 3-8μm, and then reducing the thickness of redistribution layer 1 from 10μm to 5μm, the internal stress of redistribution layer 1 is reduced to the minimum. This reduces the impact of the internal stress of redistribution layer 1 on the product, reduces the stress on the chip circuit layer, and avoids the problem of failure caused by abnormal cracks in the chip circuit layer.

[0034] In the early stage of electrocrystallization, the difference between the lattice of redistribution layer 1 and silicon substrate 3 causes a large interfacial stress, while the growth stress of redistribution layer 1 is relatively small at this time.

[0035] As the thickness of redistribution layer 1 increases, the influence of interface mismatch on the internal stress of redistribution layer 1 will gradually decrease. Therefore, the internal stress of redistribution layer 1 decreases as the film thickness increases.

[0036] When the redistribution layer 1 is deposited to a thickness of ≥10 μm, the growth stress of the redistribution layer 1 becomes the main influencing factor of the internal stress of the redistribution layer 1; according to the growth stress Kl okho of the redistribution layer 1 According to the assumptions of the lm model (optical thin film stress model), the growth stress of redistribution layer 1 is proportional to the thickness of redistribution layer 1. As the thickness of redistribution layer 1 increases, the growth stress of redistribution layer 1 gradually increases. Therefore, when redistribution layer 1 is thicker, the internal stress of redistribution layer 1 increases with the increase of redistribution layer 1 thickness. This application proposes a solution to avoid chip layer cracks caused by stress in FC packaging, including the following steps: According to the assumptions of the optical thin film stress model of redistribution layer 1 growth stress, when the thickness of redistribution layer 1 is ≥10μm, the growth stress of redistribution layer 1 is proportional to the thickness of redistribution layer 1, and the internal stress of redistribution layer 1 increases with the increase of redistribution layer thickness. The redistribution layer 1 is a copper thin film electrodeposited on silicon substrate 3. The thickness of redistribution layer 1 is reduced from 10μm to 3-8μm to reduce the stress on the chip circuit layer. A total of 615,000 products were tested after reducing the thickness of redistribution layer 1. No chip circuit layer cracks leading to failure were found in the defective products.

[0037] This invention also provides a solution to avoid chip layer cracks caused by stress in FC packaging, comprising the following steps: based on the assumptions of the stress model of the growth stress optical thin film of the redistribution layer 1, when the thickness of the redistribution layer 1 is ≥10μm, the growth stress of the redistribution layer 1 is proportional to the thickness of the redistribution layer 1, and the internal stress of the redistribution layer 1 increases with the increase of the redistribution layer thickness. The redistribution layer 1 is a copper thin film electrodeposited on the silicon substrate 3. Reducing the thickness of the redistribution layer 1 from 10μm to 3-8μm can reduce the stress on the chip circuit layer. There are no corners at the connection between the redistribution layer 1 and the oxide layer 2. The process is simple, effectively reduces the impact of the internal stress of the redistribution layer film on the product, avoids the problem of failure caused by abnormal cracks in the chip metal layer, and effectively avoids product failure caused by structural damage to the silicon-based chip.

[0038] like Figure 8 As shown, the SEM images of the fixed positions on the chip surface after the solution provided by this invention avoids chip layer cracks caused by stress in FC packaging, and the SEM images of the redistribution layer 1 with its thickness reduced from 10 μm to 5 μm, demonstrate that the chip circuit layer morphology is intact and good, and no cracks are found. Figure 1The SEM image shows the abnormal morphology of chip circuit layer cracks; this proves that the present invention provides a solution and structure to avoid chip layer cracks caused by stress in FC packaging, which can effectively avoid the problem of failure caused by abnormal cracks in the chip metal layer and avoid product failure due to structural damage to silicon-based chips.

[0039] It is understood that this invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of this invention. Furthermore, under the teachings of this invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of this invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are protected by this invention. Furthermore, under the teachings of this invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of this invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of this invention.

Claims

1. A solution to avoid chip layer cracks caused by stress in FC packaging, characterized in that, Includes the following steps: Based on the assumptions of the optical thin film stress model for redistribution layer growth stress, when the redistribution layer thickness is ≥10μm, the redistribution layer growth stress is proportional to the redistribution layer thickness, and the stress within the redistribution layer increases with the increase of the redistribution layer thickness. Reducing the redistribution layer thickness from 10μm to 3-8μm can reduce the stress on the chip circuit layer; there are no corners at the circuit connection between the redistribution layer and the oxide layer; the redistribution layer is a copper thin film electrodeposited on a silicon substrate.

2. A structure for preventing chip layer cracks caused by stress in FC packaging, characterized in that, The solution for avoiding chip layer cracks caused by stress in FC packaging according to claim 1 includes: a silicon substrate, wherein a redistribution layer is provided on the silicon substrate, and the thickness of the redistribution layer is 3-8 μm.

3. The structure for avoiding chip layer cracks caused by stress in FC packaging according to claim 2, characterized in that, One side of the redistribution layer is connected to the other side of the oxide layer, and there is no corner structure at the connection between the redistribution layer and the circuit layer of the oxide layer.

4. The structure for avoiding chip layer cracks caused by stress in FC packaging according to claim 3, characterized in that, The other side of the oxide layer is connected to the silicon substrate.

5. The structure for avoiding chip layer cracks caused by stress in FC packaging according to claim 3, characterized in that, The other side of the redistribution layer is connected to the side of the welding protrusion.

6. The structure for avoiding chip layer cracks caused by stress in FC packaging according to claim 5, characterized in that, The other side of the welding bump is connected to the tin-silver layer.

7. The structure for avoiding chip layer cracks caused by stress in FC packaging according to claim 3, characterized in that, The oxide layer also has multiple top metal parts connected to one side.

8. The structure for avoiding chip layer cracks caused by stress in FC packaging according to claim 5, characterized in that, The welding protrusions are copper pillars.

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