Semiconductor device and method of manufacturing the same

Abstract

The application relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a buried layer formed in the substrate, a first well region arranged on the upper surface layer of the buried layer, a second well region arranged on the upper surface layer of the buried layer and partially in contact with the substrate, the second well region being located at the periphery of the first well region, a base lead-out region and a plurality of emitter lead-out regions arranged in the upper surface layer of the first well region at intervals, a gate structure arranged on the upper surface layer of the substrate and comprising a gate, the orthographic projection of the gate on the first well region being staggered with the emitter lead-out regions, and the gate being electrically connected with the base lead-out region, and a collector lead-out region formed in the upper surface layer of the second well region. The plurality of emitter lead-out regions are connected in parallel to lead out the emitter. The current gain of the semiconductor device can be improved, and the current gain of the semiconductor device is not affected by the excessively high doping concentration of the emitter lead-out region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to semiconductor devices and their manufacturing methods. Background Technology

[0002] In related technologies, the semiconductor structure includes a P-type substrate and an N-type buried layer disposed within the substrate. An NPN transistor is formed in the P-well, while the N-type buried layer is used for isolation. The emitter is led out from the P-well, and the collector is led out from the N-well. The breakdown voltage of the semiconductor structure is improved by forming a PN junction between the P-well and the N-well.

[0003] However, the emitter region of a traditional semiconductor structure is usually heavily doped, which affects the current gain of the semiconductor structure. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor device and its manufacturing method to address the problem that the emitter region of traditional semiconductor structures is usually heavily doped, which affects the current gain of the semiconductor structure.

[0005] According to one aspect of this application, a semiconductor device is provided, comprising:

[0006] The substrate has a first type of conductivity;

[0007] A buried layer is formed within the substrate and has a second conductivity type, the first conductivity type being the opposite of the second conductivity type;

[0008] A first well region is located on the upper surface of the buried layer and has the first conductivity type;

[0009] The second well region is located on the upper surface of the buried layer and partially contacts the substrate. The second well region is located outside the first well region and has the second conductivity type.

[0010] A base lead-out region and multiple emitter lead-out regions are spaced apart within the upper surface layer of the first well region; the base lead-out region is located around the emitter lead-out region; the base lead-out region has the first conductivity type, and the emitter lead-out region has the second conductivity type;

[0011] A gate structure is disposed on the upper surface layer of the substrate and includes a gate, wherein the orthographic projection of the gate onto the first well region is staggered with the emitter lead-out region; and the gate is electrically connected to the base lead-out region; and

[0012] The collector lead-out region is formed within the upper surface layer of the second well region and has the second conductivity type;

[0013] The multiple emitter lead-out regions are connected in parallel to lead out the emitter.

[0014] In one embodiment, the first conductivity type is P-type, and the second conductivity type is N-type;

[0015] When the emitter input voltage is applied, the emitter lead-out region, the base lead-out region, and the first well region together with the collector lead-out region constitute an NPN transistor.

[0016] In one embodiment, the semiconductor device further includes a resistor structure, which is connected in series with the base lead-out region and then connected in parallel with the gate of the gate structure.

[0017] In one embodiment, the resistor structure is an adjustable resistor.

[0018] In one embodiment, the substrate further includes a plurality of isolation structures formed on the upper surface of the substrate, the plurality of isolation structures including a first isolation structure for electrically isolating the emitter lead-out region and the base lead-out region from each other, and a second isolation structure for electrically isolating the base lead-out region and the collector lead-out region from each other.

[0019] In one embodiment, the gate structure further includes a gate dielectric layer disposed on the upper surface of the substrate, and the gate is disposed on the upper surface of the gate dielectric layer;

[0020] The gate includes a parallel structure, which comprises a plurality of conductive structures connected in parallel.

[0021] In one embodiment, the gate includes two parallel structures, wherein the conductive structure of one parallel structure extends along a first direction and the conductive structure of the other parallel structure extends along a second direction, wherein one conductive structure of one parallel structure intersects with a plurality of conductive structures of the other parallel structure.

[0022] The first direction and the second direction intersect each other.

[0023] According to another aspect of this application, a method for manufacturing a semiconductor device is provided, comprising:

[0024] A substrate is provided; the substrate has a first conductivity type;

[0025] A buried layer is formed within the substrate; the buried layer has a second conductivity type, the first conductivity type being the opposite of the second conductivity type;

[0026] A first well region is formed on the upper surface of the buried layer, and the first well region has the first conductivity type;

[0027] A second well region is formed on the upper surface of the buried layer, located around the first well region. A portion of the second well region is in contact with the substrate and has the second conductivity type.

[0028] A gate structure is formed on the upper surface layer of the substrate;

[0029] A base lead-out region and a plurality of emitter lead-out regions are formed at intervals in the upper surface layer of the first well region; wherein, the base lead-out region is located around the emitter lead-out region; the gate structure includes a gate, the orthographic projection of the gate on the first well region is staggered with the emitter lead-out region; and the gate is electrically connected to the base lead-out region; the base lead-out region has the first conductivity type, and the emitter lead-out region has the second conductivity type;

[0030] A collector lead-out region having the second conductivity type is formed in the upper surface layer of the second well region;

[0031] The multiple emitter lead-out regions are connected in parallel to lead out the emitter, and the doping concentration of the emitter lead-out regions is a preset value.

[0032] In one embodiment, the gate structure includes a gate dielectric layer; prior to forming the gate structure on the upper surface of the substrate, the method of manufacturing the semiconductor device further includes forming a plurality of isolation structures on the upper surface of the substrate;

[0033] The formation of the gate structure on the upper surface layer of the substrate specifically includes:

[0034] A gate dielectric layer is formed on the upper surface of the substrate between two adjacent isolation structures;

[0035] The gate is formed on the region above the first well region on the gate dielectric layer.

[0036] In one embodiment, forming spaced-apart base lead-out regions and multiple emitter lead-out regions within the upper surface layer of the first well region specifically includes:

[0037] Ions of a first conductivity type are injected into the first well region to form the base lead-out region;

[0038] Ions of a second conductivity type are injected into the first well region to form a plurality of emitter extraction regions.

[0039] The semiconductor device and its manufacturing method described above, when a certain voltage is applied to the base lead-out region, will cause an inversion layer to be generated in the first well region below the gate due to the gate being electrically connected to the base lead-out region. This inversion layer has the same conductivity type as the emitter lead-out region, thereby connecting multiple emitter lead-out regions with the intermediate inversion layer to form an emitter assembly. That is, by controlling the gate voltage, the area of ​​the emitter and the effective doping concentration of the entire emitter region can be effectively controlled, thus eliminating the need for heavy doping during the formation of the emitter lead-out region. Furthermore, since multiple emitter lead-out regions are connected in parallel to lead out the emitter, it is beneficial to improve the electrical conductivity of the emitter during use, ensuring the overall area of ​​all emitter regions while also improving the current gain of the semiconductor device, and avoiding the impact of excessively high doping concentration in the emitter lead-out region on the current gain of the semiconductor device. Attached Figure Description

[0040] Figure 1 A schematic diagram of the structure of a semiconductor device according to an embodiment of this application is shown;

[0041] Figure 2 A schematic diagram of the structure of a semiconductor device according to another embodiment of this application is shown;

[0042] Figure 3 A schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application is shown;

[0043] Figures 4(a)-4(f) A schematic diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of this application is shown;

[0044] Figure 5 A schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application is shown.

[0045] In the figure: 110, substrate; 111, sacrificial layer; 112, oxide layer; 113, silicon nitride layer; 120, buried layer; 130, first well region; 140, second well region; 150, emitter lead-out region; 160, base lead-out region; 170, collector lead-out region; 180, gate structure; 181, gate; 1811, conductive structure; 182, gate dielectric layer; 190, resistive structure; 210, first isolation structure; 220, second isolation structure; 230, third isolation structure; 300, passivation layer; 410, first conductive plug; 420, second conductive plug; 430, third conductive plug. Detailed Implementation

[0046] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0048] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0049] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0051] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0052] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0053] Figure 1 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application.

[0054] Please see Figure 1 The semiconductor device provided in one embodiment of this application includes a substrate 110, a buried layer 120, a first well region 130, a second well region 140, a plurality of emitter lead-out regions 150, a base lead-out region 160, a collector lead-out region 170, and a gate structure 180.

[0055] The substrate 110 has a first conductivity type, the buried layer 120 is formed in the substrate 110, and the buried layer 120 has a second conductivity type, the first conductivity type being the opposite of the second conductivity type.

[0056] In this embodiment, one of the first conductivity type and the second conductivity type is P-type, and the other is N-type. For example, the first conductivity type is P-type, and the second conductivity type is N-type; or, the first conductivity type is N-type, and the second conductivity type is P-type. For instance, in this embodiment, the first conductivity type is P-type, the second conductivity type is N-type, the substrate 110 has a P-type conductivity type, and the buried layer 120 has an N-type conductivity type.

[0057] A first well region 130 is disposed on the upper surface of the buried layer 120 and has a first conductivity type. A second well region 140 is disposed on the upper surface of the buried layer 120, and a portion of the second well region 140 is in contact with the substrate 110. The second well region 140 is located around the first well region 130 and has a second conductivity type. The first well region 130 and the second well region 140 have opposite conductivity types, and a PN junction can be formed between the first well region 130 and the second well region 140.

[0058] A base lead-out region 160 and multiple emitter lead-out regions 150 are spaced apart within the upper surface layer of the first well region 130. The base lead-out region 160 is located around the emitter lead-out region 150. The base lead-out region 160 has a first conductivity type, and the emitter lead-out region 150 has a second conductivity type. A gate structure 180 is disposed on the upper surface layer of the substrate 110 and includes a gate 181. The orthographic projection of the gate 181 onto the first well region 130 is staggered with that of the emitter lead-out region 150, and the gate 181 is electrically connected to the base lead-out region 160. A collector lead-out region 170 is formed within the upper surface layer of the second well region 140, and the collector lead-out region 170 has a second conductivity type.

[0059] Thus, since the overall structure formed by the base lead-out region 160 and the first well region 130 has the opposite conductivity type to the emitter lead-out region 150, and the overall structure formed by the base lead-out region 160 and the first well region 130 has the opposite conductivity type to the overall structure formed by the collector lead-out region 170 and the second well region 140, the overall structure formed by the emitter lead-out region 150, the base lead-out region 160 and the first well region 130 together with the overall structure formed by the collector lead-out region 170 and the second well region 140 constitutes a transistor.

[0060] When a certain voltage is applied to the base lead-out region 160, the gate 181, which is electrically connected to the base lead-out region 160, will cause an inversion layer to be generated in the first well region 130 below the gate 181. This inversion layer has the same conductivity type as the emitter lead-out region 150, thereby connecting multiple emitter lead-out regions 150 with the intermediate inversion layer to form an emitter assembly. That is, by controlling the voltage of the gate 181, the area of ​​the emitter and the effective doping concentration of the entire emitter region can be effectively controlled, thus eliminating the need for heavy doping when forming the emitter lead-out region 150. Furthermore, since multiple emitter lead-out regions 150 are connected in parallel to lead out the emitter, it is beneficial to improve the electrical conductivity of the emitter during use. While ensuring the overall area of ​​all emitter regions, it can also improve the current gain of the semiconductor device, avoiding the impact of excessively high doping concentration of the emitter lead-out region 150 on the current gain of the semiconductor device.

[0061] In some embodiments, the doping concentration of the emitter lead-out region 150 is a preset value, which is 4 × 10⁻⁶. 19 cm -3 ~8×10 19 cm -3 That is, the doping concentration of emitter take-off region 150 can be 4×10⁻⁶. 19 cm -3 ~8×10 19 cm -3 Compared to traditional heavily doped regions, the emitter lead-out region 150 has a lower doping concentration, which is beneficial for improving the current gain of semiconductor devices.

[0062] In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type. When the emitter input voltage is applied, the emitter lead-out region 150, the base lead-out region 160, and the first well region 130 together with the collector lead-out region 170 constitute an NPN transistor.

[0063] The collector lead-out region 170 is led out as the collector. When a positive voltage is input to the emitter, the emitter serves as the emitter of the NPN transistor, and the collector serves as the collector of the NPN transistor. The base lead-out region 160 and the first well region 130 together serve as the base region of the NPN transistor.

[0064] In some embodiments, the semiconductor device further includes a resistor structure 190, which is connected in series with the base lead-out region 160 and then connected in parallel with the gate 181 of the gate structure 180.

[0065] The following explanation uses P-type as the first conductivity type and N-type as the second conductivity type as an example. The resistive structure 190 creates a voltage difference between the gate 181 and the first well region 130, forming an electric field that repels holes and attracts electrons. Therefore, holes in the region of the first well region 130 below the gate 181 are repelled, while minority carriers (electrons) in the P-type first well region 130 are attracted to the region below the gate 181. When the voltage at the gate 181 reaches a certain value, such as a base voltage of 0.4V-0.7V, these electrons can form an inversion layer in the region of the first well region 130 below the gate 181. Since the orthogonal projection of the gate 181 onto the first well region 130 coincides with the emitter lead-out region 15... The staggered arrangement of the 0s indicates that the inversion layer formed is located between two adjacent emitter lead-out regions 150, electrically connecting the two adjacent emitter lead-out regions 150. This is equivalent to forming an inversion layer with a low doping concentration and the same conductivity type as the emitter lead-out region 150 between the two adjacent emitter lead-out regions 150. In this way, the effective doping concentration of the emitter lead-out region 150 can be effectively increased, thereby increasing the effective area of ​​the emitter lead-out region 150. It is also beneficial to increase the gain current of the semiconductor device. Thus, the gain current of the semiconductor device and the effective doping concentration of the emitter lead-out region 150 can be controlled by controlling the input voltage of the gate 181.

[0066] When the voltage of the gate 181 reaches a certain value, such as when the base voltage is greater than 0.7V, a strong inversion layer can be formed in the region below the gate 181 on the first well region 130, which is more conducive to improving the gain current of the semiconductor device.

[0067] In some embodiments, the gate 181 is located above the region between two adjacent emitter lead-out regions 150.

[0068] In some embodiments, the resistor structure 190 is an adjustable resistor, such as a variable resistor, a resistor box, or a potentiometer, to obtain a suitable voltage drop.

[0069] In some embodiments, the resistor structure 190 is a high-resistance resistor. The resistance value of the resistor structure 190 can be changed by changing the material of the resistor structure 190, or by adjusting the doping concentration of the resistor structure 190. For example, if the material of the resistor structure 190 is polycrystalline silicon, the resistance value of the resistor structure 190 can be increased by reducing the doping concentration of the resistor structure 190.

[0070] In some embodiments, the resistance value of the resistor structure 190 is 2000Ω-10000Ω.

[0071] In some embodiments, the semiconductor device further includes a plurality of isolation structures formed on the upper surface of the substrate 110, the plurality of isolation structures including a first isolation structure 210 for electrically isolating the emitter lead-out region 150 and the base lead-out region 160 from each other, and a second isolation structure 220 for electrically isolating the base lead-out region 160 and the collector lead-out region 170 from each other.

[0072] The first isolation structure 210 also extends to the upper surface of the first well region 130. The first isolation structure 210 can be a ring structure to better electrically isolate the emitter lead-out region 150 and the base lead-out region 160.

[0073] A portion of the second isolation structure 220 extends to the upper surface of the first well region 130, and another portion of the second isolation structure 220 extends to the upper surface of the second well region 140. The second isolation structure 220 can be a ring structure to better electrically isolate the base lead-out region 160 and the collector lead-out region 170.

[0074] Of course, this application is not limited to this. Alternatively, multiple collector lead-out regions 170 may be provided, and the upper surface of the first well region 130 may have multiple base lead-out regions 160 corresponding one-to-one with the collector lead-out regions 170. The upper surface of the first well region 130 may also have multiple second isolation structures 220 extending to the upper surface of the second well region 140 and corresponding one-to-one with the collector lead-out regions 170. Each second isolation structure 220 is disposed between the corresponding base lead-out region 160 and the corresponding collector lead-out region 170 to electrically isolate them. Furthermore, the multiple collector lead-out regions 170 are connected in parallel to serve as collectors, which helps improve the electrical conductivity of the collector during use, thereby improving the voltage withstand capability and reliability of the semiconductor device.

[0075] The multiple isolation structures also include a third isolation structure 230 disposed on the upper surface of the second well region 140 and located on the periphery of the collector lead-out region 170. The third isolation structure 230 is located on the periphery of the collector lead-out region 170 and is used to isolate the semiconductor device from other devices, thereby further improving the isolation performance of the semiconductor device.

[0076] The third isolation structure 230 can be a ring structure to better electrically isolate the semiconductor device from other devices.

[0077] In other embodiments, the first isolation structure 210, the second isolation structure 220 and the third isolation structure 230 may be shallow trench isolation structures.

[0078] In some embodiments, please refer to Figure 2The gate structure 180 also includes a gate dielectric layer 182 disposed on the upper surface of the substrate 110, and a gate 181 disposed on the upper surface of the gate dielectric layer 182. The gate 181 includes a parallel structure, which includes a plurality of parallel conductive structures 1811 (such as polysilicon). The conductive structures 1811 and the emitter lead-out region 150 are arranged alternately.

[0079] Multiple conductive structures 1811 are connected in parallel, which means that each conductive structure 1811 can constitute the gate resistance of the gate 181, making the gate resistance distribution of the gate 181 more uniform. This is beneficial to improving the current sharing characteristics of the gate 181 and reducing the gate resistance, so as to realize the fast switching of the "series connection" between two adjacent emitter lead-out regions 150 below the gate 181.

[0080] In some embodiments, the gate 181 includes two parallel structures. In one parallel structure, the conductive structure 1811 extends along a first direction F1, and the conductive structure 1811 of the other parallel structure extends along a second direction F2. The conductive structure 1811 of the one parallel structure intersects with a plurality of conductive structures 1811 of the other parallel structure. The first direction F1 and the second direction F2 intersect each other.

[0081] Understandably, the two parallel structures can be connected to form a mesh structure. Thus, the gate 181 is equivalent to multiple conductive branch structures connected in parallel, which helps to reduce the gate resistance and facilitates fast switching of the "series connection" between the two adjacent emitter lead-out regions 150 below the gate 181.

[0082] In some embodiments, a plurality of emitter lead-out regions 150 are arranged in an array along a first direction F1 and a second direction F2, that is, the plurality of emitter lead-out regions 150 are arranged to form a plurality of emitter lead-out region assemblies spaced apart along the first direction F1, and each emitter lead-out region assembly includes a plurality of emitter lead-out regions 150 spaced apart along the second direction F2. In one parallel structure, a plurality of conductive structures 1811 (extending along the first direction F1) and a plurality of emitter lead-out regions 150 of the same emitter lead-out region assembly are staggered along the second direction F2; in another parallel structure, a plurality of conductive structures 1811 (extending along the second direction F2) and a plurality of emitter lead-out region assemblies are staggered along the first direction F1. This achieves fast switching of a "series connection" between two adjacent emitter lead-out regions 150 below the gate 181, while also facilitating the control of the gain current of the semiconductor device and the effective doping concentration of the emitter lead-out regions 150 by controlling the input voltage of the gate 181.

[0083] This application provides a method for manufacturing a semiconductor device, which can be used to manufacture the semiconductor device of any of the foregoing embodiments.

[0084] Figure 3 A schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application is shown.

[0085] Please see Figure 3 A method for manufacturing a semiconductor device according to an embodiment of this application includes the following steps:

[0086] S210, a substrate 110 is provided, the substrate 110 having a first conductivity type.

[0087] S220, Referring to Figure 4(a), a buried layer 120 is formed within the substrate 110. The buried layer 120 has a second conductivity type, which is the opposite of the first conductivity type. A sacrificial layer 111 can be deposited on the substrate 110, and then the buried layer 120 is formed by high-temperature push-well after ion implantation. The junction depth after push-well must reach a certain depth to ensure the depletion of the semiconductor device and the conduction path of the current. The sacrificial layer 111 can be made of silicon dioxide.

[0088] S230, Referring to Figure 4(b), a first well region 130 is formed on the upper surface of the buried layer 120. The first well region 130 has a first conductivity type. The first well region 130 can be formed by high-temperature push-well formation after ion implantation.

[0089] S240, Referring to Figure 4(b), a second well region 140 is formed on the upper surface of the buried layer 120, located around the first well region 130. A portion of the second well region 140 is in contact with the substrate 110, and the second well region 140 has a second conductivity type. The second well region 140 can be formed by high-temperature push-well formation after ion implantation.

[0090] S250, Referring to Figure 4(e), a gate structure 180 is formed on the upper surface layer of the substrate 110.

[0091] S260, Referring to Figure 4(f), a base lead-out region 160 and a plurality of emitter lead-out regions 150 are formed at intervals in the upper surface layer of the first well region 130. The base lead-out region 160 is located around the emitter lead-out region 150. The gate structure 180 includes a gate 181. The orthographic projection of the gate 181 onto the first well region 130 is staggered with that of the emitter lead-out region 150, and the gate 181 is electrically connected to the base lead-out region 160. The base lead-out region 160 has a first conductivity type, and the emitter lead-out region 150 has a second conductivity type.

[0092] S270, Please refer to Figure 4(f), a collector lead-out region 170 with a second conductivity type is formed in the upper surface layer of the second well region 140.

[0093] Multiple emitter lead-out regions 150 are connected in parallel to lead out the emitter, and the doping concentration of the emitter lead-out regions 150 is a preset value. This helps to improve the electrical conductivity of the emitter during use, ensures the overall area of ​​all emitter regions, and also improves the current gain of the semiconductor device, avoiding the impact of excessively high doping concentration of the emitter lead-out regions 150 on the current gain of the semiconductor device.

[0094] In some embodiments, before step S250 of forming the gate structure 180 on the upper surface layer of the substrate 110, the semiconductor device manufacturing method further includes: forming a plurality of isolation structures on the upper surface layer of the substrate 110. Specifically, the sacrificial layer 111 can be removed, the upper surface of the substrate 110 can be cleaned, and a sacrificial oxidation process can be performed on the upper surface of the substrate 110 to form an oxide layer 112. As shown in Figures 4(c) and 4(d), a silicon nitride layer 113 can be deposited on the oxide layer 112. Through processes such as photolithography and development, a pattern corresponding to the plurality of isolation structures can be formed on the silicon nitride layer 113. High-temperature thermal oxidation is then performed on the substrate 110 at the pattern corresponding to the isolation structures to form a plurality of isolation structures.

[0095] Multiple isolation structures can be formed using a field oxidation process. Due to the high temperature and prolonged advancement of the isolation structures, on the one hand, the isolation structures themselves are advanced. Parts of the multiple isolation structures, such as the first isolation structure 210, extend to the upper surface of the first well region 130; another part of the multiple isolation structures, such as a part of the second isolation structure 220, extends to the upper surface of the first well region 130, and another part of the second isolation structure 220 extends to the upper surface of the second well region 140; yet another part of the multiple isolation structures, such as the third isolation structure 230, extends to the upper surface of the second well region 140. On the other hand, the first well region 130 and the second well region 140 are also advanced, and the junction profiles of both the first well region 130 and the second well region 140 are optimized. After the push-in of the first well region 130 and the second well region 140, the junction depth can reach a certain depth to ensure the depletion of the semiconductor device and the conduction path of the current.

[0096] Step S250 of forming the gate structure 180 on the upper surface layer of the substrate 110 specifically includes:

[0097] S251, As shown in Figure 4(d), remove the oxide layer 112 and the silicon nitride layer 113, and form a gate dielectric layer 182 between two adjacent isolation structures on the upper surface of the substrate 110.

[0098] S252, As shown in FIG4(e), a gate 181 is formed on the region of the gate dielectric layer 182 above the first well region 130.

[0099] In some embodiments, step S260, which involves forming spaced-apart base lead-out regions 160 and multiple emitter lead-out regions 150 within the upper surface layer of the first well region 130, specifically includes:

[0100] Please refer to Figure 4(f). Ions of a first type of conductivity are implanted into the first well region 130 using photoresist as a masking film to form the base lead-out region 160. Ions of a second type of conductivity are implanted into the first well region 130 using photoresist as a masking film to form multiple emitter lead-out regions 150.

[0101] In some embodiments, step S270 of forming a collector lead-out region 170 having a second conductivity type in the upper surface layer of the second well region 140 specifically includes:

[0102] Please refer to Figure 4(f). Using photoresist as a masking film, ions of the second conductivity type are implanted into the second well region 140 to form the second electrode lead-out region 170.

[0103] In some embodiments, please refer to Figure 4(f) and in conjunction with the relevant references. Figure 5 The manufacturing methods for semiconductor devices also include:

[0104] S281. A passivation layer 300 covering the gate structure 180 and multiple isolation structures is formed on the upper surface of the substrate 110.

[0105] S282. Planarize the side of the passivation layer 300 that is away from the gate structure 180.

[0106] S283. A first conductive plug 410, a second conductive plug 420 and a third conductive plug 430 are formed within the passivation layer 300, penetrating the passivation layer 300.

[0107] S284. An emitter, a collector, and a base are formed on the passivation layer 300.

[0108] The emitter is electrically connected to the emitter lead-out region 150 via a first conductive plug 410, the collector is electrically connected to the collector lead-out region 170 via a second conductive plug 420, and the base is electrically connected to the base lead-out region 160 via a third conductive plug 430. This allows the emitter, collector, and base of the NPN transistor to be properly connected.

[0109] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the above flowcharts may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps. It should be noted that the different embodiments described above can be combined with each other.

[0110] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0111] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: The substrate has a first type of conductivity; A buried layer is formed within the substrate and has a second conductivity type, the first conductivity type being the opposite of the second conductivity type; A first well region is located on the upper surface of the buried layer and has the first conductivity type; The second well region is located on the upper surface of the buried layer and partially contacts the substrate. The second well region is located outside the first well region and has the second conductivity type. A base lead-out region and multiple emitter lead-out regions are spaced apart within the upper surface layer of the first well region; the base lead-out region is located around the emitter lead-out region; The base lead-out region has the first conductivity type, and the emitter lead-out region has the second conductivity type; A gate structure is disposed on the upper surface layer of the substrate and includes a gate, wherein the orthographic projection of the gate on the first well region is staggered with the emitter lead-out region; and the gate is electrically connected to the base lead-out region. as well as The collector lead-out region is formed within the upper surface layer of the second well region and has the second conductivity type; The multiple emitter lead-out regions are connected in parallel to lead out the emitter.

2. The semiconductor device according to claim 1, characterized in that, The first conductivity type is P-type, and the second conductivity type is N-type; When the emitter input voltage is applied, the emitter lead-out region, the base lead-out region, and the first well region together with the collector lead-out region constitute an NPN transistor.

3. The semiconductor device according to claim 1 or 2, characterized in that, The semiconductor device further includes a resistor structure, which is connected in series with the base lead-out region and then connected in parallel with the gate of the gate structure.

4. The semiconductor device according to claim 3, characterized in that, The resistor structure is an adjustable resistor.

5. The semiconductor device according to claim 1 or 2, characterized in that, It also includes a plurality of isolation structures formed on the upper surface of the substrate, the plurality of isolation structures including a first isolation structure for electrically isolating the emitter lead-out region and the base lead-out region from each other, and a second isolation structure for electrically isolating the base lead-out region and the collector lead-out region from each other.

6. The semiconductor device according to claim 1 or 2, characterized in that, The gate structure further includes a gate dielectric layer disposed on the upper surface of the substrate, and the gate is disposed on the upper surface of the gate dielectric layer; The gate includes a parallel structure, which comprises a plurality of conductive structures connected in parallel.

7. The semiconductor device according to claim 6, characterized in that, The gate includes two parallel structures. In the two parallel structures, the conductive structure of one parallel structure extends along a first direction, and the conductive structure of the other parallel structure extends along a second direction. One of the conductive structures of the one parallel structure intersects with multiple conductive structures of the other parallel structure. The first direction and the second direction intersect each other.

8. A method for manufacturing a semiconductor device, characterized in that, include: Provide substrate; The substrate has a first conductivity type; A buried layer is formed within the substrate; The buried layer has a second conductivity type, and the first conductivity type is the opposite of the second conductivity type; A first well region is formed on the upper surface of the buried layer, and the first well region has the first conductivity type; A second well region is formed on the upper surface of the buried layer, located around the first well region. A portion of the second well region is in contact with the substrate and has the second conductivity type. A gate structure is formed on the upper surface layer of the substrate; A base lead-out region and a plurality of emitter lead-out regions are formed at intervals in the upper surface layer of the first well region; wherein, the base lead-out region is located around the emitter lead-out region; the gate structure includes a gate, the orthographic projection of the gate on the first well region is staggered with the emitter lead-out region; and the gate is electrically connected to the base lead-out region; the base lead-out region has the first conductivity type, and the emitter lead-out region has the second conductivity type; A collector lead-out region having the second conductivity type is formed in the upper surface layer of the second well region; The multiple emitter lead-out regions are connected in parallel to lead out the emitter, and the doping concentration of the emitter lead-out regions is a preset value.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The gate structure further includes a gate dielectric layer; prior to forming the gate structure on the upper surface layer of the substrate, the method for manufacturing the semiconductor device further includes forming a plurality of isolation structures on the upper surface layer of the substrate; The formation of the gate structure on the upper surface layer of the substrate specifically includes: A gate dielectric layer is formed on the upper surface of the substrate between two adjacent isolation structures; The gate is formed on the region above the first well region on the gate dielectric layer.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The formation of spaced base lead-out regions and multiple emitter lead-out regions within the upper surface layer of the first well region specifically includes: Ions of a first conductivity type are injected into the first well region to form the base lead-out region; Ions of a second conductivity type are injected into the first well region to form a plurality of emitter extraction regions.

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