Semiconductor device and method of manufacturing the same

Abstract

The application belongs to the technical field of semiconductor, and particularly relates to a semiconductor device and a preparation method thereof. The semiconductor device designed by the application comprises a substrate, an NMOS region and a PMOS region above the substrate; wherein the NMOS region comprises a first NMOS region and a second NMOS region, the first NMOS region comprises a first nanosheet array, and the second NMOS region comprises a second nanosheet array; the PMOS region comprises a first PMOS region and a second PMOS region, the first PMOS region comprises a third nanosheet array, and the second PMOS region comprises a fourth nanosheet array; and the outer side of each nanosheet channel in the first nanosheet array, the second nanosheet array, the third nanosheet array and the fourth nanosheet array is respectively surrounded by a gate dielectric layer, the gate dielectric layer comprises an interface layer, and the gate dielectric layer further comprises a first high-k dielectric layer, a second high-k dielectric layer and a third high-k dielectric layer covering the interface layer in sequence; or the gate dielectric layer further comprises a third high-k dielectric layer, a second high-k dielectric layer and a first high-k dielectric layer covering the interface layer in sequence; wherein the polarity of the first high-k dielectric layer and the third high-k dielectric layer is different, the electric dipole electric field formed by the first high-k dielectric layer and the second high-k dielectric layer is different from the electric dipole electric field formed by the third high-k dielectric layer and the second high-k dielectric layer, and the Si-O polarity intensity in IL is changed after annealing, so as to realize threshold control at different positions of the device.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] With the continuous miniaturization of transistor feature size, the traditional MOSFET device has undergone a transition from a planar structure to a three-dimensional structure, improving device performance while reducing the impact of short channel effects. The mainstream three-dimensional structure transistor is FinFET. However, FinFET faces great challenges below 5nm technology generation, and in the latest International Roadmap for Devices and Systems (IRDS), nanosheet GAAFET is a key device that can effectively replace FinFET after 3nm node, and can significantly suppress short channel effects and improve the current driving performance of the device.

[0003] GAA stacked nanosheet FET is a new type of device with a ring gate structure and horizontal nanosheet (NS) as a conductive channel, which is developed on the basis of FinFET and Nanowire FET. In terms of gate control, the ring gate structure has better gate control ability than the FinFET device structure, which can effectively suppress the short channel effect of the device; in terms of current driving, Nanosheet GAAFET has effective gate adjustment and vertical and horizontal stacking design, which can significantly enhance the current driving performance of the device.

[0004] The GAAFET in the prior art realizes multi-threshold control of the device by changing the thickness of the work function metal layer (WFL) or other metal gate film layers in the HKMG structure. However, for Nanosheet GAAFET, due to the space limitation between the stacked nanosheets, if the threshold control is realized by adjusting the thickness of the metal gate film layer, the work function layer will be difficult to fill or will not be uniformly filled, resulting in difficulty in accurately controlling the threshold of the CMOS device.

[0005] CN114551357A (published on May 27, 2022) discloses a stacked nanosheet ring gate CMOS device and a preparation method thereof. The CMOS device includes: a substrate, a first NMOS and a second NMOS formed above an NMOS region of the substrate, each nanosheet channel in a nanosheet array of the first NMOS is surrounded by a first high-k dielectric layer, an NMOS work function layer and a conductive metal layer from inside to outside, each nanosheet channel in a nanosheet array of the second NMOS is surrounded by a second high-k dielectric layer, an NMOS work function layer and a conductive metal layer from inside to outside; a first PMOS and a second PMOS formed above a PMOS region of the substrate, each nanosheet channel in a nanosheet array of the first PMOS is surrounded by a second high-k dielectric layer, a PMOS work function layer and a conductive metal layer from inside to outside, each nanosheet channel in a nanosheet array of the second PMOS is surrounded by a first high-k dielectric layer, a PMOS work function layer and a conductive metal layer from inside to outside. The CMOS device uses different high-k dielectric layers to realize the regulation of the threshold value of the CMOS device, but the regulation result cannot reach the ideal precision. SUMMARY

[0006] The technical purpose of the present application is to at least solve the problem in the prior art that for a Nanosheet GAAFET, due to the space limitation between stacked nanosheets, if the threshold value is regulated by adjusting the thickness change of the metal gate film layer, the work function layer is difficult to fill or is not uniformly filled, resulting in the difficulty in accurately regulating the threshold value of the CMOS device.

[0007] The purpose is achieved by the following technical solutions:

[0008] In a first aspect, a gate dielectric layer for a semiconductor device, the gate dielectric layer comprises an interface layer, the gate dielectric layer further comprises a first high-k dielectric layer, a second high-k dielectric layer and a third high-k dielectric layer covering the interface layer in sequence;

[0009] or the gate dielectric layer further comprises a third high-k dielectric layer, a second high-k dielectric layer and a first high-k dielectric layer covering the interface layer in sequence;

[0010] Wherein, the material of the first high-k dielectric layer and the material of the third high-k dielectric layer have different polarities. The electric dipole field formed by the first high-k dielectric layer and the second high-k dielectric layer is different from the electric dipole field formed by the third high-k dielectric layer and the second high-k dielectric layer, which changes the Si-O polarity intensity in the IL after annealing, so as to realize the threshold value regulation of different positions of the device.

[0011] In some embodiments of the present application, the material of the second high-k dielectric layer is Hf-based high-k material, preferably Hf oxide.

[0012] In some embodiments of the present application, the material of the first high-k dielectric layer is oxide of one or two or more of La, Mg, Sc, Y, and Nd, and the material of the third high-k dielectric layer is oxide of one or two or more of Al, Mn, Zr, Ti, and Mo. Among the oxides possessed by the first high-k dielectric layer, the metal E fm The radius of the metal E is smaller than that of the metal F, and the radius of the metal F is relatively larger than that of the metal G.

[0013] In a second aspect, an HKMG structure for a semiconductor device, the HKMG structure comprising the gate dielectric layer of the first aspect, further comprising a metal gate.

[0014] In a third aspect, a semiconductor device, the semiconductor device comprising:

[0015] a substrate;

[0016] an NMOS region and a PMOS region above the substrate;

[0017] wherein the NMOS region comprises a first NMOS region and a second NMOS region, the first NMOS region comprising a first nanosheet array, and the second NMOS region comprising a second nanosheet array;

[0018] the PMOS region comprises a first PMOS region and a second PMOS region, the first PMOS region comprising a third nanosheet array, and the second PMOS region comprising a fourth nanosheet array;

[0019] each nanosheet channel in the first nanosheet array, the second nanosheet array, the third nanosheet array, and the fourth nanosheet array is surrounded by the gate dielectric layer of the first aspect or the HKMG structure of the second aspect on the outside; this arrangement ensures effective regulation of multi-thresholds in the semiconductor device without increasing the overall thickness of the multi-layer HKMG.

[0020] a source region and a drain region.

[0021] In some embodiments of the present application, the gate dielectric layer on the outside of each nanosheet channel of any two or more of the first nanosheet array, the second nanosheet array, the third nanosheet array, and the fourth nanosheet array is different in distribution.

[0022] In some embodiments of the present invention, each nanosheet channel in the first nanosheet array and the second nanosheet array is surrounded from the inside out by an interface layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer, and a metal gate.

[0023] In the third nanosheet array and the fourth nanosheet array, each nanosheet channel is surrounded from the inside out by an interface layer, a third high-k dielectric layer, a second high-k dielectric layer, a first high-k dielectric layer, and a metal gate.

[0024] In some embodiments of the present invention, each nanosheet channel in the first nanosheet array and the third nanosheet array is surrounded from the inside out by an interface layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer, and a metal gate.

[0025] In the second nanosheet array and the fourth nanosheet array, each nanosheet channel is surrounded from the inside out by an interface layer, a third high-k dielectric layer, a second high-k dielectric layer, a first high-k dielectric layer, and a metal gate.

[0026] In some embodiments of the present invention, each nanosheet channel in the first nanosheet array and the fourth nanosheet array is surrounded from the inside out by an interface layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer, and a metal gate.

[0027] In the second and third nanosheet arrays, each nanosheet channel is surrounded from the inside out by an interface layer, a third high-k dielectric layer, a second high-k dielectric layer, a first high-k dielectric layer, and a metal gate.

[0028] In some embodiments of the present invention, the thicknesses of any two dielectric layers in each of the first high-k dielectric layers are not equal, and the thicknesses of any two dielectric layers in each of the third high-k dielectric layers are not equal.

[0029] In some embodiments of the present invention, the thickness T of any two dielectric layers in each of the first high-k dielectric layers is... HK1 They are respectively Preferred Preferred

[0030] In some embodiments of the present invention, the thickness T of any two dielectric layers in each of the third high-k dielectric layers is... HK2 They are respectively Preferred Preferred

[0031] Fourthly, a method for fabricating the semiconductor device described in the third aspect includes the following steps:

[0032] Provide substrate;

[0033] forming NMOS region and PMOS region over the substrate respectively; wherein first high-k dielectric or third high-k dielectric is deposited firstly over the interface layer of each nanosheet channel of each nanosheet array, then second high-k dielectric is deposited, and finally third high-k dielectric or first high-k dielectric is deposited, for forming gate dielectric layer;

[0034] forming source region and drain region.

[0035] In some embodiments of the present application, the annealing process is performed after the deposition, and the annealing process temperature is 200-1000℃, preferably 250-950℃.

[0036] In some embodiments of the present application, the deposition is physical vapor deposition and / or chemical vapor deposition.

[0037] In the fifth aspect, a GAA FET transistor is provided, which comprises the gate dielectric layer of the first aspect or the HKMG structure of the second aspect.

[0038] In the sixth aspect, a chip is provided, which comprises the GAA FET transistor of the fifth aspect.

[0039] The beneficial effects of the technical solutions of the present application mainly include the following:

[0040] 1. By adjusting the material and thickness of the high-k dielectric covering each nanosheet channel in different regions, the threshold voltage of different regions can be precisely adjusted.

[0041] 2. The adjustment method designed in the present application can precisely adjust the threshold voltage of different regions without changing the thickness of the HKMG. BRIEF DESCRIPTION OF DRAWINGS

[0042] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of the preferred embodiments and are not intended to limit the scope of the present application. Moreover, like reference numerals designate like parts throughout the several views in the drawings. In the drawings:

[0043] Figure 1 a structure schematic diagram of a GAA FET transistor according to an embodiment of the present application is schematically shown;

[0044] Figure 2 a cross-sectional view of A-A of Figure 1 is schematically shown;

[0045] Figure 3 a cross-sectional view of A-A of Figure 1A-A sectional view of FIG. 1 ;

[0046] Figure 4 A-A sectional view of FIG. 1 ; Figure 3 A-A sectional view of FIG. 1 ;

[0047] The reference numbers in the drawings represent the following:

[0048] 100, substrate;

[0049] 110-1, first NMOS fin structure;

[0050] 110-11, first nanosheet array;

[0051] 110-2, second NMOS fin structure;

[0052] 110-21, second nanosheet array;

[0053] 120-1, first PMOS fin structure;

[0054] 120-11, third nanosheet array;

[0055] 120-2, second PMOS fin structure;

[0056] 120-21, fourth nanosheet array;

[0057] 130, dummy gate;

[0058] 140, interface layer;

[0059] 150, first high-k dielectric layer;

[0060] 160, second high-k dielectric layer;

[0061] 170, third high-k dielectric layer;

[0062] 180, metal gate. DETAILED DESCRIPTION

[0063] The term "high-k" is used throughout this application to mean a dielectric material having a dielectric constant greater than SiO2as measured in vacuum.

[0064] The term "HKMG structure" is used throughout this application to mean a structure that utilizes an HK dielectric material in place of SiON and a metal gate in place of a poly-silicon gate.

[0065] The term "NMOS region" is used throughout this application to mean an N-type metal-oxide-semiconductor region.

[0066] The term "PMOS region" is used throughout this application to mean a P-type metal-oxide-semiconductor region.

[0067] In the prior art, for the Nanosheet GAA FET, due to the space limitation between the stacked nanosheets, if the threshold value is regulated by adjusting the thickness change of the metal gate film layer, the work function layer is difficult to fill or is not filled uniformly, resulting in that the threshold value of the CMOS device is difficult to accurately regulate. Even if different high-k dielectric layers are used to regulate the threshold value of the device, the regulation result cannot be as accurate as ideal.

[0068] To solve the above technical problems, the present application provides a semiconductor device and a preparation method thereof. The semiconductor device changes the Si-O polarity intensity in the IL by covering the dipole-doped high-k dielectric with different polarities at different positions, ensures the effective and accurate regulation of the multi-threshold value of the device without increasing the overall thickness of the multi-layer HKMG.

[0069] The first aspect of the present application to achieve the above technical effects is to provide a gate dielectric layer for a semiconductor device, the gate dielectric layer comprising an interface layer, the gate dielectric layer further comprising a first high-k dielectric layer, a second high-k dielectric layer and a third high-k dielectric layer successively covering the interface layer;

[0070] Or the gate dielectric layer further comprises a third high-k dielectric layer, a second high-k dielectric layer and a first high-k dielectric layer successively covering the interface layer;

[0071] Wherein, the material of the first high-k dielectric layer and the material of the third high-k dielectric layer have different polarities. The electric dipole electric field formed by the first high-k dielectric layer and the second high-k dielectric layer is different from the electric dipole electric field formed by the third high-k dielectric layer and the second high-k dielectric layer. After annealing, the Si-O polarity intensity in the IL is changed to regulate the threshold value of the device at different positions.

[0072] In some embodiments, the material of the second high-k dielectric layer is a Hf-based high-k material, preferably an oxide of Hf, such as HfO2, HfSiO x , HfON, HfSiON, HfAlO x , etc.

[0073] In some embodiments, the material of the first high-k dielectric layer is an oxide of one or two or more of La, Mg, Sc, Y, Nd, and the material of the third high-k dielectric layer is an oxide of one or two or more of Al, Mn, Zr, Ti, Mo. Among them, the metal E fm of the oxide possessed by the first high-k dielectric layer is smaller than that of the oxide possessed by the third high-k dielectric layer, and the radius of the oxide possessed by the first high-k dielectric layer is relatively larger than that of the oxide possessed by the third high-k dielectric layer.

[0074] For example, the material of the first high-k dielectric layer is LaOx MgO x ScO x YO x NdO x , the material of the third high-k dielectric layer is AlO x MnO x ZrO x TiO x MoO x , wherein x in each chemical formula is any natural number other than zero; and the polarity of the material of the first high-k dielectric layer is different from the polarity of the material of the third high-k dielectric layer, and the doping of the oxide of Hf by the different-polarity dielectric is conducive to changing the Si-O polarity intensity in the IL.

[0075] In some embodiments, the material of the interface layer contains Si elements, which can be Si-containing oxides, Si-containing salts, etc.

[0076] A second aspect of the present application for achieving the above technical effects is to provide an HKMG structure for a semiconductor device, the HKMG structure comprising the gate dielectric layer of the first aspect, and further comprising a metal gate.

[0077] In some embodiments, the metal gate comprises a work function metal layer (WFL).

[0078] A third aspect of the present application for achieving the above technical effects is to provide a semiconductor device, the semiconductor device comprising:

[0079] a substrate;

[0080] an NMOS region and a PMOS region above the substrate;

[0081] wherein the NMOS region comprises a first NMOS region and a second NMOS region, the first NMOS region comprises a first nanosheet array, and the second NMOS region comprises a second nanosheet array;

[0082] the PMOS region comprises a first PMOS region and a second PMOS region, the first PMOS region comprises a third nanosheet array, and the second PMOS region comprises a fourth nanosheet array;

[0083] each nanosheet channel in the first nanosheet array, the second nanosheet array, the third nanosheet array, and the fourth nanosheet array is respectively surrounded by the gate dielectric layer of the first aspect or the HKMG structure of the second aspect;

[0084] a source region and a drain region.

[0085] In some embodiments, the gate dielectric layer distribution outside each nanosheet channel of any two or more of the first nanosheet array, the second nanosheet array, the third nanosheet array, and the fourth nanosheet array is different.

[0086] In some embodiments, the gate dielectric layer distribution outside each nanosheet channel of any three of the first nanosheet array, the second nanosheet array, the third nanosheet array, and the fourth nanosheet array is different.

[0087] In some embodiments, the gate dielectric layer distribution outside each nanosheet channel of the four of the first nanosheet array, the second nanosheet array, the third nanosheet array, and the fourth nanosheet array is different.

[0088] In some embodiments, each nanosheet channel in the first nanosheet array and the second nanosheet array is sequentially surrounded by, from inside to outside, an interface layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer, and a metal gate; that is, the gate dielectric layer distribution outside each nanosheet channel of the first NMOS region and the second NMOS region in the NMOS region is the same, and the thickness of each layer in each of the gate dielectric layers can be the same or different, preferably different.

[0089] Each nanosheet channel in the third nanosheet array and the fourth nanosheet array is sequentially surrounded by, from inside to outside, an interface layer, a third high-k dielectric layer, a second high-k dielectric layer, a first high-k dielectric layer, and a metal gate; that is, the gate dielectric layer distribution outside each nanosheet channel of the first PMOS region and the second PMOS region in the PMOS region is the same, and the thickness of each layer in each of the gate dielectric layers can be the same or different, preferably different.

[0090] In some embodiments, each nanosheet channel in the first nanosheet array and the third nanosheet array is sequentially surrounded by, from inside to outside, an interface layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer, and a metal gate; that is, the gate dielectric layer distribution outside each nanosheet channel of the first NMOS region in the NMOS region and the first PMOS region in the PMOS region is the same, and the thickness of each layer in each of the gate dielectric layers can be the same or different, preferably different.

[0091] Each nanosheet channel in the second nanosheet array and the fourth nanosheet array is sequentially surrounded by, from inside to outside, an interface layer, a third high-k dielectric layer, a second high-k dielectric layer, a first high-k dielectric layer, and a metal gate; that is, the gate dielectric layer distribution outside each nanosheet channel of the second NMOS region in the NMOS region and the second PMOS region in the PMOS region is the same, and the thickness of each layer in each of the gate dielectric layers can be the same or different, preferably different.

[0092] In some embodiments, each nanosheet channel in the first nanosheet array and the fourth nanosheet array is sequentially surrounded by, from inside to outside, an interface layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer, and a metal gate; that is, the gate dielectric layer distribution outside each nanosheet channel of the first NMOS region in the NMOS region and the second PMOS region in the PMOS region remains the same, and the thickness of each layer in each of the gate dielectric layers can be the same or different, preferably different.

[0093] In some embodiments, each nanosheet channel in the first nanosheet array and the fourth nanosheet array is sequentially surrounded by, from inside to outside, an interface layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer, and a metal gate; that is, the gate dielectric layer distribution outside each nanosheet channel of the first NMOS region in the NMOS region and the second PMOS region in the PMOS region remains the same, and the thickness of each layer in each of the gate dielectric layers can be the same or different, preferably different.

[0094] In some embodiments, the thickness of any two dielectric layers in each of the first high-k dielectric layers is not equal, and the thickness of any two dielectric layers in each of the third high-k dielectric layers is not equal.

[0095] In some embodiments, the thickness of any two dielectric layers in each of the first high-k dielectric layers is Preferably Preferably

[0096] For example, the thickness of any two dielectric layers in each of the first high-k dielectric layers is T HK1 For example

[0097] For example

[0098] In some embodiments, the thickness of each of the third high-k dielectric layers is T HK2 For example Preferably Preferably

[0099] For example, the thickness of any two dielectric layers in each of the third high-k dielectric layers is

[0100] For example

[0101] In some embodiments, the thickness of any one of the first high-k dielectric layers is equal to the thickness of any one of the third high-k dielectric layers.

[0102] A fourth aspect of the present application to achieve the above technical effects is to provide a preparation method of the semiconductor device of the third aspect, comprising the following steps:

[0103] providing a substrate;

[0104] forming an NMOS region and a PMOS region above the substrate; wherein a first high-k dielectric or a third high-k dielectric is first deposited above the interface layer of each nanosheet channel of each nanosheet array, followed by deposition of a second high-k dielectric, and finally deposition of a third high-k dielectric or a first high-k dielectric to form a gate dielectric layer;

[0105] forming a source region and a drain region.

[0106] In some embodiments, the annealing process is performed after the deposition, and the annealing process temperature is 200-1000℃, preferably 250-950℃, further preferably 300-800℃, and most preferably 450-600℃.

[0107] For example, the annealing process temperature is 200℃, 250℃, 300℃, 350℃, 400℃, 450℃, 500℃, 550℃, 600℃, 650℃, 700℃, 750℃, 800℃, 850℃, 900℃, 950℃, or 1000℃.

[0108] In some embodiments, the deposition is physical vapor deposition or chemical deposition.

[0109] A fifth aspect of the present application to achieve the above technical effects is to provide a GAA-FET transistor, which comprises the gate dielectric layer of the first aspect or the HKMG structure of the second aspect.

[0110] A sixth aspect of the present application to achieve the above technical effects is to provide a chip, which comprises the GAA-FET transistor of the fifth aspect.

[0111] In some embodiments, the preparation process of the GAA FET transistor, except for the gate dielectric layer, is as described in Chinese Patent Application (Application Publication No. CN115295416A, Application Publication Date: 2022-11-04), of course, other structures are also provided, but other GAA FET transistors with the gate dielectric layer of the features of the present application are also within the protection scope of the present application.

[0112] Exemplary embodiments of the present disclosure will be described below in greater detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure can be embodied in various forms without being limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0113] Embodiment 1

[0114] A method for fabricating a GAA FET transistor is provided, as shown in Figure 1 、 Figure 2 comprising the steps of:

[0115] S1, providing a substrate 100, the substrate 1 comprising an NMOS region and a PMOS region, the NMOS region being provided with a first NMOS fin structure 110-1 and a second NMOS fin structure 110-2, the PMOS region being provided with a first PMOS fin structure 120-1 and a second PMOS fin structure 120-2, each of the fin structures comprising a support portion formed on the substrate and alternately stacked sacrificial layers and channel layers on the support portion, and each of the fin structures forming a dummy gate 130;

[0116] S2, forming a source region and a drain region on both sides of each of the dummy gates, respectively;

[0117] S3, removing the dummy gates by a selective etching or etching process;

[0118] S4, continuing to selectively etch the sacrificial layers in each of the fin structures for releasing the channel of the nanosheet, wherein the channel layer of the first NMOS fin structure 110-1 is released to form a first nanosheet array 110-11, and by analogy, the channel layer of the second NMOS fin structure 110-2 is released to form a second nanosheet array 110-21, the channel layer of the first PMOS fin structure 120-1 is released to form a third nanosheet array 120-11, and the channel layer of the second PMOS fin structure 120-2 is released to form a fourth nanosheet array 120-21;

[0119] S5, each nanosheet channel in the first nanosheet array 110-11 and the second nanosheet array 110-21 is sequentially surrounded by, from inside to outside, an interface layer 140, a first high-k dielectric layer 150, a second high-k dielectric layer 160, and a third high-k dielectric layer 170; wherein the second high-k dielectric layer is made of a Hf-based high-k material, preferably an oxide of Hf such as HfO2; the first high-k dielectric layer is made of an oxide of any one of La, Mg, Sc, Y, and Nd, preferably an oxide of Sc such as Sc2O3; and the thickness of the first high-k dielectric layer in the first nanosheet array and the second nanosheet array is 0.5-5 nm. Preferably For example For example Preferably For example Meanwhile, the third high-k dielectric layer is made of an oxide of any one of Al, Mn, Zr, Ti, and Mo, preferably an oxide of Zr such as ZrO2; and the thickness of the third high-k dielectric layer in the first nanosheet array and the second nanosheet array is 0.5-5 nm. Preferably For example For example Preferably For example

[0120] In addition, each nanosheet channel in the third nanosheet array 120-11 and the fourth nanosheet array 120-21 is sequentially surrounded by, from inside to outside, an interface layer 140, a third high-k dielectric layer 170, a second high-k dielectric layer 160, and a first high-k dielectric layer 150. The second high-k dielectric layer is made of a Hf-based high-k material, preferably an oxide of Hf such as HfO2; the third high-k dielectric layer is made of an oxide of any one of Al, Mn, Zr, Ti, and Mo, preferably an oxide of Zr such as ZrO2; and the thickness of the third high-k dielectric layer in the first nanosheet array and the second nanosheet array is 0.5-5 nm. Preferably For example For example Preferably For example The first high-k dielectric layer is made of an oxide of any one of La, Mg, Sc, Y, and Nd, preferably an oxide of Sc such as Sc2O3; and the thickness of the first high-k dielectric layer in the first nanosheet array and the second nanosheet array is 0.5-5 nm. Preferably For example For example Preferably For example

[0121] S6, annealing or non-annealing process is performed to form a gate dielectric layer; wherein the annealing process temperature is 200-1000 DEG C, preferably 250-950 DEG C, such as 600 DEG C.

[0122] S7, forming a metal gate layer;

[0123] S6, continuing to deposit an ILD medium on top of the metal gate layer, and leading out a contact electrode.

[0124] Embodiment 2

[0125] A preparation method of a GAA FET transistor is provided, different in that in step S5, each nanosheet channel in the first nanosheet array and the third nanosheet array is sequentially surrounded by an interface layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer, and a metal gate from inside to outside.

[0126] Each nanosheet channel in the second nanosheet array and the fourth nanosheet array is sequentially surrounded by an interface layer, a third high-k dielectric layer, a second high-k dielectric layer, a first high-k dielectric layer, and a metal gate from inside to outside.

[0127] Embodiment 3

[0128] A preparation method of a GAA FET transistor is provided, different in that in step S5, each nanosheet channel in the first nanosheet array and the fourth nanosheet array is sequentially surrounded by an interface layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer, and a metal gate from inside to outside.

[0129] Each nanosheet channel in the second nanosheet array and the third nanosheet array is sequentially surrounded by an interface layer, a third high-k dielectric layer, a second high-k dielectric layer, a first high-k dielectric layer, and a metal gate from inside to outside.

[0130] Other embodiments are also included, in which the material and thickness of the first high-k dielectric layer, the second high-k dielectric layer, and the third high-k dielectric layer are changed respectively or simultaneously within the above-mentioned categories or numerical ranges, which are not described in detail in this embodiment, but are within the protection scope of the present application.

[0131] By adjusting the material and thickness of the high-k dielectric covering each nanosheet channel in the first nanosheet array, the second nanosheet array, the third nanosheet array, and the fourth nanosheet array, the threshold voltage of different regions can be precisely adjusted.

[0132] It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", "including" and "has" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order in which they are described unless specifically identified as an order dependent step. It is also to be understood that additional or alternative steps can be employed.

[0133] Although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can be only used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as "first", "second", and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.

[0134] Spatially relative terms, such as "inner", "outer", "inward", "outward", "lower", "bottom", "top", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the example term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0135] The above description is only specific example embodiments of the present application, but the scope of the present application is not limited thereto. Any person skilled in the art can easily make changes or substitutions within the technical scope disclosed in the present application, and such changes or substitutions should be encompassed within the scope of the present application. Therefore, the scope of the present application should be defined by the scope of claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: Substrate; The NMOS and PMOS regions are located above the substrate; The NMOS region includes a first NMOS region and a second NMOS region, wherein the first NMOS region includes a first nanosheet array and the second NMOS region includes a second nanosheet array; The PMOS region includes a first PMOS region and a second PMOS region, the first PMOS region includes a third nanosheet array, and the second PMOS region includes a fourth nanosheet array. Each nanosheet channel in the first nanosheet array, the second nanosheet array, the third nanosheet array, and the fourth nanosheet array is surrounded by an HKMG structure. The HKMG structure includes a gate dielectric layer and a metal gate. The gate dielectric layer includes an interface layer and also includes a first high-k dielectric layer, a second high-k dielectric layer, and a third high-k dielectric layer that sequentially cover the interface layer. Alternatively, the gate dielectric layer may further include a third high-k dielectric layer, a second high-k dielectric layer, and a first high-k dielectric layer that sequentially cover the interface layer; An electric dipole is formed between the first high-k dielectric layer and the second high-k dielectric layer, and an electric dipole is formed between the third high-k dielectric layer and the second high-k dielectric layer; The materials of the first high-k dielectric layer and the third high-k dielectric layer have different polarities. Source region and drain region.

2. The semiconductor device according to claim 1, characterized in that, The second high-k dielectric layer is made of Hf-based high-k material.

3. The semiconductor device according to claim 2, characterized in that, The second high-k dielectric layer is made of Hf oxide.

4. The semiconductor device according to claim 1, characterized in that, The first high-k dielectric layer is made of one or more oxides of La, Mg, Sc, Y, and Nd, and the third high-k dielectric layer is made of one or more oxides of Al, Mn, Zr, Ti, and Mo.

5. The semiconductor device according to claim 1, characterized in that, The distribution of the gate dielectric layer on the outer side of each nanosheet channel in any two or more of the first nanosheet array, the second nanosheet array, the third nanosheet array, and the fourth nanosheet array is different but the same at the same time.

6. The semiconductor device according to claim 5, characterized in that, In the first nanosheet array and the second nanosheet array, each nanosheet channel is surrounded from the inside out by an interface layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer, and a metal gate. In the third nanosheet array and the fourth nanosheet array, each nanosheet channel is surrounded from the inside out by an interface layer, a third high-k dielectric layer, a second high-k dielectric layer, a first high-k dielectric layer, and a metal gate. Alternatively, each nanosheet channel in the first nanosheet array and the third nanosheet array is surrounded from the inside out by an interface layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer, and a metal gate. In the second nanosheet array and the fourth nanosheet array, each nanosheet channel is surrounded from the inside out by an interface layer, a third high-k dielectric layer, a second high-k dielectric layer, a first high-k dielectric layer, and a metal gate. Alternatively, each nanosheet channel in the first nanosheet array and the fourth nanosheet array is surrounded from the inside out by an interface layer, a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer, and a metal gate. In the second and third nanosheet arrays, each nanosheet channel is surrounded from the inside out by an interface layer, a third high-k dielectric layer, a second high-k dielectric layer, a first high-k dielectric layer, and a metal gate.

7. The semiconductor device according to claim 6, characterized in that, The thicknesses of any two dielectric layers in each of the first high-k dielectric layers are not equal, and the thicknesses of any two dielectric layers in each of the third high-k dielectric layers are not equal.

8. The semiconductor device according to claim 7, characterized in that, The thickness T of any two dielectric layers in each of the first high-k dielectric layers HK1 The ranges are 1~5 Å and 5~10 Å, respectively.

9. The semiconductor device according to claim 8, characterized in that, The thickness T of any two dielectric layers in each of the first high-k dielectric layers HK1 The ranges are 1.5–4.5 Å and 5.5–9.5 Å, respectively.

10. The semiconductor device according to claim 7, characterized in that, The thickness T of any two dielectric layers in each of the third high-k dielectric layers HK2 The ranges are 1~5 Å and 5~10 Å, respectively.

11. The semiconductor device according to claim 10, characterized in that, The thickness T of any two dielectric layers in each of the third high-k dielectric layers HK2 The ranges are 1.5–4.5 Å and 5.5–9.5 Å, respectively.

12. A method for fabricating a semiconductor device according to any one of claims 1 to 11, characterized in that, The steps include the following: Provide substrate; NMOS and PMOS regions are formed above the substrate, respectively; wherein, a first high-k dielectric or a third high-k dielectric is first deposited above the interface layer of each nanosheet channel of each nanosheet array, followed by a second high-k dielectric, and finally a third high-k dielectric or a first high-k dielectric is deposited to form a gate dielectric layer. This forms the source and drain regions.

13. The preparation method according to claim 12, characterized in that, The deposition is followed by an annealing or non-annealing process, and the annealing process temperature is 200~1000℃.

14. The preparation method according to claim 13, characterized in that, The annealing process temperature is 250~950℃.

15. The preparation method according to claim 12, characterized in that, The deposition is physical vapor deposition and / or chemical vapor deposition.

16. A GAA FET transistor, characterized in that, The transistor includes: The HKMG structure includes a gate dielectric layer and a metal gate. The gate dielectric layer includes an interface layer and further includes a first high-k dielectric layer, a second high-k dielectric layer and a third high-k dielectric layer that sequentially cover the interface layer. Alternatively, the gate dielectric layer may further include a third high-k dielectric layer, a second high-k dielectric layer, and a first high-k dielectric layer that sequentially cover the interface layer; An electric dipole is formed between the first high-k dielectric layer and the second high-k dielectric layer, and an electric dipole is formed between the third high-k dielectric layer and the second high-k dielectric layer; The materials of the first high-k dielectric layer and the third high-k dielectric layer have different polarities.

17. A chip, characterized in that, The chip includes the GAA FET transistor of claim 16.

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