Semiconductor devices and electronic devices

Abstract

This application provides a semiconductor device and an electronic device. The semiconductor device includes an insulating substrate and a thin-film transistor layer on the insulating substrate. The thin-film transistor layer includes an active layer and a first metal layer on the active layer. The active layer includes an active segment and a conductor layer stacked together. The conductor layer includes a first conductor segment and a second conductor segment spaced apart on the active segment. The first metal layer includes a first electrode connected to the first conductor segment and a second electrode connected to the second conductor segment. By providing a groove between the first and second electrodes in the active segment, the depth of the groove being greater than the thickness of the conductor layer and less than the thickness of the active layer, and by further providing a compensation portion disposed in the groove, the compensation portion includes a conductive portion connected to one of the first and second electrodes and insulated from the other of the first and second electrodes, thereby reducing the channel length and increasing the on-state current of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a semiconductor device and an electronic device. Background Technology

[0002] Currently, please refer to Figure 1 This is a schematic diagram of the structure of an existing display panel. The existing display panel 1 includes an insulating substrate 10, a light-shielding layer 70, a buffer layer 80, a thin film transistor layer 20, a planarization layer 91, a common electrode 62A, a passivation layer 92, and a pixel electrode 61A stacked on the insulating substrate 10. The thin film transistor layer 20 includes an active layer 23, a gate insulating layer 22, a gate 21, an interlayer insulating layer 25, a source electrode 24A1, and a drain electrode 24B1 stacked sequentially on the insulating substrate 10.

[0003] It is understood that in the prior art, the thin film transistor layer includes multiple thin film transistors 20A (TFTs) arranged in a matrix. The thin film transistors 20A use gate voltage to control the current between the source 24A1 and the drain 24B1, thereby serving as switching elements of the display panel. As the performance of display devices improves, the channel in the thin film transistor 20A is required to have a larger aspect ratio. The aspect ratio of the channel determines the functional characteristics of the thin film transistor 20A. Under the condition that the width of the channel is constant, shortening the length of the channel can enable the thin film transistor to have a larger aspect ratio, thereby having a larger on-state current.

[0004] However, in the traditional thin-film transistor manufacturing process, the length of the channel is directly limited by the photolithography process, making it difficult to achieve a short channel. At the same time, in the existing technology, when the source and drain are formed on the active layer by etching process, the metal material is affected by the side etching of the etching solution, which leads to an increase in channel length and thus reduces the on-state current of the thin-film transistor. Summary of the Invention

[0005] This application provides a semiconductor device and an electronic device to alleviate the shortcomings of related technologies.

[0006] To achieve the above functions, the technical solutions provided in this application are as follows:

[0007] 1. This application provides a semiconductor device, including:

[0008] Insulating substrate:

[0009] A thin-film transistor layer is disposed on the insulating substrate, the thin-film transistor layer comprising:

[0010] An active layer is disposed on the insulating substrate. The active layer includes an active segment and a conductor layer stacked together. The conductor layer includes a first conductor segment and a second conductor segment spaced apart on the active segment.

[0011] A first metal layer is disposed on the side of the active layer away from the insulating substrate, and the first metal layer includes a first electrode connected to the first conductor segment and a second electrode connected to the second conductor segment;

[0012] The active layer includes a groove located between the first electrode and the second electrode, wherein the depth of the groove is less than the thickness of the active layer and greater than the thickness of the conductor layer;

[0013] The semiconductor device further includes a compensation portion disposed in the groove, the compensation portion including at least a conductive portion, the conductive portion being connected to one of the first electrode and the second electrode, and the conductive portion being insulated from the other of the first electrode and the second electrode.

[0014] In the semiconductor device provided in the embodiments of this application, the compensation portion includes a first compensation sub-portion and a second compensation sub-portion located between the conductive portion and the active segment. The sum of the thickness of the first compensation sub-portion and the thickness of the second compensation sub-portion is less than or equal to the depth of the groove. The conductive portion extends from the second compensation sub-portion in a direction away from the groove.

[0015] In the semiconductor device provided in the embodiments of this application, the orthographic projection of the conductive portion on the insulating substrate overlaps with the orthographic projection of the second compensator portion on the insulating substrate, and the orthographic projection of the second compensator portion on the insulating substrate overlaps with the orthographic projection of the first compensator portion on the insulating substrate.

[0016] In the semiconductor device provided in the embodiments of this application, the material of the first compensation sub-section is the same as the material of the active section, the material of the second compensation sub-section is the same as the material of the conductor layer, and the material of the conductive section is the same as the material of the first metal layer.

[0017] In the semiconductor device provided in the embodiments of this application, the compensation portion includes a first compensation sub-portion and a second compensation sub-portion located between the conductive portion and the active segment. The sum of the thickness of the first compensation sub-portion and the thickness of the second compensation sub-portion is equal to the depth of the groove. The second compensation sub-portion is located between the first compensation sub-portion and the conductive portion.

[0018] Wherein, the side of the first compensation sub-part away from the insulating substrate is flush with the side of the active segment away from the insulating substrate, the side of the second compensation sub-part away from the insulating substrate is flush with the side of the conductor layer away from the insulating substrate, and the side of the conductive part away from the insulating substrate is flush with the side of the first metal layer away from the insulating substrate.

[0019] In the semiconductor device provided in the embodiments of this application, the semiconductor device further includes a first insulating layer located on the side of the first metal layer away from the active layer, the first insulating layer extending from the side of the first metal layer away from the active layer into the groove;

[0020] Wherein, at least a portion of the first insulating layer is located between the conductive portion and the first electrode, or at least a portion of the first insulating layer is located between the conductive portion and the second electrode.

[0021] In the semiconductor device provided in the embodiments of this application, the conductive portion is connected to the first electrode;

[0022] The first insulating layer includes a first insulator portion and a second insulator portion that are connected to each other. The orthographic projection of the first insulator portion on the substrate covers the orthographic projection of the second electrode on the substrate. The second insulator portion is located in the groove and is disposed between the compensation portion and the second electrode.

[0023] In the semiconductor device provided in the embodiments of this application, the conductive portion is connected to the second electrode;

[0024] The first insulating layer includes a first insulator portion and a second insulator portion that are connected to each other. The orthographic projection of the first insulator portion on the substrate covers the orthographic projection of the first electrode on the substrate. The second insulator portion is located in the groove and is disposed between the compensation portion and the first electrode.

[0025] In the semiconductor device provided in the embodiments of this application, the thin-film transistor layer includes a gate, a gate insulating layer, the active layer, the first electrode, and the second electrode stacked sequentially.

[0026] Wherein, the first electrode covers the first conductor segment, the second electrode covers the second conductor segment, and the orthogonal projection of the gate on the insulating substrate covers the orthogonal projection of the active layer on the insulating substrate.

[0027] This application provides an electronic device, which includes any of the semiconductor devices described above.

[0028] The beneficial effects of this application embodiment are as follows: This application embodiment provides an active layer including a groove located between the first electrode and the second electrode. The depth of the groove is greater than the thickness of the conductor layer and less than the thickness of the active layer. The semiconductor device further includes a compensation portion disposed in the groove. The compensation portion includes at least a conductive portion. The conductive portion is connected to one of the first electrode and the second electrode, and the conductive portion is insulated from the other of the first electrode and the second electrode. This reduces the channel length, increases the on-state current, and reduces the power consumption of the semiconductor device. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the structure of an existing display panel;

[0031] Figure 2 This is a first top cross-sectional view of the semiconductor device provided in the embodiments of this application;

[0032] Figure 3 for Figure 2 A schematic diagram of the cross-sectional structure along the AA′ direction;

[0033] Figure 4 This is a second top cross-sectional view of the semiconductor device provided in the embodiments of this application;

[0034] Figure 5 for Figure 4 A schematic diagram of the cross-sectional structure along the BB′ direction;

[0035] Figure 6 A flowchart illustrating the method for fabricating the semiconductor device provided in the embodiments of this application;

[0036] Figures 7A to 7G for Figure 6 A flowchart illustrating the fabrication process of semiconductor devices. Detailed Implementation

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0038] This application provides a semiconductor device and an electronic device. These will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0039] Please see Figures 2 to 7G This application provides a semiconductor device and an electronic device, wherein the semiconductor device 2 includes:

[0040] Insulating substrate 10:

[0041] Thin-film transistor layer 20 is disposed on the insulating substrate 10, and the thin-film transistor layer 20 includes:

[0042] An active layer 23 is disposed on the insulating substrate 10. The active layer 23 includes an active segment 23A and a conductor layer 231 stacked together. The conductor layer 231 includes a first conductor segment 23B and a second conductor segment 23C spaced apart on the active segment 23A.

[0043] A first metal layer 24 is disposed on the side of the active layer 23 away from the insulating substrate 10. The first metal layer 24 includes a first electrode 24A connected to the first conductor segment 23B and a second electrode 24B connected to the second conductor segment 23C.

[0044] The active layer 23 includes a groove 230 located between the first electrode 24A and the second electrode 24B. The depth of the groove 230 is less than the thickness of the active layer 23 and greater than the thickness of the conductor layer 231.

[0045] The semiconductor device 2 further includes a compensation portion 30 disposed in the groove 230. The compensation portion 30 includes at least a conductive portion 33. The conductive portion 33 is connected to one of the first electrode 24A and the second electrode 24B, and the conductive portion 33 is insulated from the other of the first electrode 24A and the second electrode 24B.

[0046] It is understood that, in this embodiment of the application, the active layer 23 includes a groove 230 located between the first electrode 24A and the second electrode 24B. The depth of the groove 230 is less than the thickness of the active layer 23 and greater than the thickness of the conductor layer 231. The semiconductor device 2 also includes a compensation portion 30 disposed in the groove 230. The compensation portion 30 includes at least a conductive portion 33. The conductive portion 33 is connected to one of the first electrode 24A and the second electrode 24B, and is insulated from the other of the first electrode 24A and the second electrode 24B. This reduces the channel length, increases the on-state current, and reduces the power consumption of the semiconductor device 2.

[0047] The technical solution of this application will now be described in conjunction with specific embodiments.

[0048] In one embodiment, please refer to Figure 2 and Figure 3 ;in, Figure 2 This is a first top cross-sectional view of the semiconductor device provided in the embodiments of this application; Figure 3 for Figure 2 A schematic diagram of the cross-sectional structure along the AA′ direction.

[0049] In this embodiment, the semiconductor device 2 includes an insulating substrate 10 and a thin-film transistor layer 20 disposed on the insulating substrate 10. The insulating substrate 10 may include a rigid substrate or a flexible substrate. This embodiment does not impose specific limitations on the material of the insulating substrate 10.

[0050] The thin-film transistor layer 20 includes a gate 21, a gate insulating layer 22, an active layer 23, and a first metal layer 24 sequentially stacked on the insulating substrate 10. The active layer 23 includes an active segment 23A and a conductor layer 231 stacked on top of each other. The conductor layer 231 includes a first conductor segment 23B and a second conductor segment 23C spaced apart on the active segment 23A. The first metal layer 24 includes a first electrode 24A connected to the first conductor segment 23B and a second electrode 24B connected to the second conductor segment 23C. The first electrode 24A includes, but is not limited to, a source electrode, and the second electrode 24B includes, but is not limited to, a drain electrode. The first conductor segment 23B and the second conductor segment 23C have the same projection pattern, while the first electrode 24A and the second electrode 24B have different projection patterns.

[0051] The thin-film transistor layer 20 includes a plurality of thin-film transistors 20A arranged in a matrix, with each thin-film transistor 20A located in a sub-pixel region. Each thin-film transistor 20A includes a gate 21, a gate insulating layer 22, an active layer 23, a first electrode 24A, and a second electrode 24B stacked together.

[0052] The active layer 23 is made of materials including but not limited to amorphous silicon, polycrystalline silicon, or oxide semiconductor materials; preferably, the first conductor segment 23B and the second conductor segment 23C are both made of polycrystalline silicon with a high concentration of n-type impurities doped by silicides, the shape of the first conductor segment 23B is the same as the shape of the second conductor segment 23C, the orthographic projection of the active segment 23A on the insulating substrate 10 covers the orthographic projection of the first conductor segment 23B on the insulating substrate 10, and the orthographic projection of the active segment 23A on the insulating substrate 10 covers the orthographic projection of the second conductor segment 23C on the insulating substrate 10.

[0053] The gate 21 is made of a metallic material, including but not limited to one or more alloys of molybdenum (Mo), titanium (Ti), and nickel (Ni); the orthogonal projection of the gate 21 onto the insulating substrate 10 covers the orthogonal projection of the active layer 23 onto the insulating substrate 10; it can be understood that, combined with Figure 1 In the prior art, a light-shielding layer is usually disposed between the insulating substrate 10 and the active layer 23. The light-shielding layer can block the light incident on the active layer 23, thereby reducing the increase in leakage current caused by photogenerated carriers generated by light irradiating the active layer 23, and thus maintaining the stability of the active layer 23 during operation. Compared with the prior art, this embodiment sets the orthogonal projection of the gate 21 on the insulating substrate 10 to cover the orthogonal projection of the active layer 23 on the insulating substrate 10, so that the gate 21 can play the role of the light-shielding layer in the prior art, saving engineering processes and reducing the manufacturing cost of the semiconductor device 2.

[0054] The material of the first metal layer 24 includes, but is not limited to, one or more alloys of molybdenum (Mo), titanium (Ti), and nickel (Ni). The first electrode 24A covers the first conductor segment 23B, and the second electrode 24B covers the second conductor segment 23C. Specifically, the orthographic projection of the first electrode 24A on the insulating substrate 10 covers the orthographic projection of the first conductor segment 23B on the insulating substrate 10, and the orthographic projection of the second electrode 24B on the insulating substrate 10 covers the orthographic projection of the second conductor segment 23C on the insulating substrate 10. It can be understood that, in combination with... Figure 1Compared with existing thin-film transistor layer fabrication processes, this embodiment does not require etching to create contact vias, allowing the first electrode 24A and the second electrode 24B to be connected to the active layer 23 through contact vias, further saving fabrication costs.

[0055] In this embodiment, the active layer 23 includes a groove 230 located between the first electrode 24A and the second electrode 24B. The depth of the groove 230 is less than the thickness of the active layer 23 and greater than the thickness of the conductor layer 231. Further, the width of the groove 230 is equal to the distance between the first electrode 24A and the second electrode 24B. The semiconductor device 2 also includes a compensation portion 30 disposed in the groove 230. The compensation portion 30 includes at least a conductive portion 33. The conductive portion 33 is connected to one of the first electrode 24A and the second electrode 24B, and is insulated from the other of the first electrode 24A and the second electrode 24B.

[0056] Specifically, in this embodiment, the conductive portion 33 is connected to the second electrode 24B, and the conductive portion 33 is insulated from the first electrode 24A. It can be understood that in this embodiment, the active segment 23A includes a groove 230 located between the first electrode 24A and the second electrode 24B. The depth of the groove 230 is less than the thickness of the active layer 23 and greater than the thickness of the conductor layer 231. The width of the groove 230 is equal to the distance between the first electrode 24A and the second electrode 24B. The semiconductor device 2 also includes components disposed in... The compensation portion 30 within the groove 230 includes at least a conductive portion 33, which is connected to the second electrode 24B. This increases the width of the second electrode 24B, thereby reducing the channel length of the thin-film transistor 20A, increasing the on-state current, and reducing the power consumption of the semiconductor device 2. Furthermore, by setting the conductive portion 33 to be insulated from the first electrode 24A, the second electrode 24B is prevented from conducting with the first electrode 24A, thus avoiding any impact on the electrical characteristics of the thin-film transistor 20A.

[0057] In this embodiment, the compensation portion 30 includes a first compensation sub-portion 31 and a second compensation sub-portion 32 located between the conductive portion 33 and the active segment 23A. The sum of the thickness of the first compensation sub-portion 31 and the thickness of the second compensation sub-portion 32 is less than or equal to the depth of the groove 230. The conductive portion 33 extends from the second compensation sub-portion 32 in a direction away from the groove 230.

[0058] Preferably, the sum of the thickness of the first compensation sub-part 31 and the thickness of the second compensation sub-part 32 is equal to the depth of the groove 230. The second compensation sub-part 32 is located between the first compensation sub-part 31 and the conductive part 33. The side of the first compensation sub-part 31 away from the insulating substrate 10 is flush with the side of the active segment 23A away from the insulating substrate 10. The side of the second compensation sub-part 32 away from the insulating substrate 10 is flush with the side of the conductor layer 231 away from the insulating substrate 10. The side of the conductive part 33 away from the insulating substrate 10 is flush with the side of the first metal layer 24 away from the active layer 23.

[0059] Furthermore, the orthographic projection of the conductive portion 33 on the insulating substrate 10 overlaps with the orthographic projection of the second compensating portion 32 on the insulating substrate 10, and the orthographic projection of the second compensating portion 32 on the insulating substrate 10 overlaps with the orthographic projection of the first compensating portion 31 on the insulating substrate 10, thereby maintaining the flatness of the thin-film transistor 20A and the flatness of the semiconductor device 2; furthermore, the material of the first compensating portion 31 is the same as the material of the active segment 23A, the material of the second compensating portion 32 is the same as the material of the conductor layer 231, and the material of the conductive portion 33 is the same as the material of the first metal layer 24, thereby maintaining the electrical characteristics of the thin-film transistor 20A.

[0060] Furthermore, in this embodiment, the semiconductor device 2 further includes a first insulating layer 40 located on the side of the first metal layer 24 away from the active layer 23, the first insulating layer 40 extending from the side of the first metal layer 24 away from the active layer 23 into the groove 230; wherein at least a portion of the first insulating layer 40 is located between the conductive portion 33 and the first electrode 24A.

[0061] Specifically, in this embodiment, the first insulating layer 40 includes a first insulator portion 41 and a second insulator portion 42 connected to each other. The orthographic projection of the first insulator portion 41 on the substrate covers the orthographic projection of the first electrode 24A on the substrate, thereby blocking water and oxygen and providing insulation for the first electrode 24A. The second insulator portion 42 is located in the groove 230 and is disposed between the compensation portion 30 and the first electrode 24A, thereby insulating the conductive portion 33 from the first electrode 24A and preventing the second electrode 24B from conducting with the first electrode 24A, thus affecting the electrical characteristics of the thin film transistor 20A.

[0062] It is understood that in this embodiment, the channel of the thin-film transistor 20A (not marked in the figure) is located between the first conductor segment 23B and the second conductor segment 23C, that is, the active segment 23A. The length of the channel is equal to the width of the second insulator portion 42. Therefore, the length of the channel can be determined by the width of the second insulator portion 42. Thus, under the condition that the width of the channel is constant, this embodiment can shorten the length of the channel by reducing the width of the second insulator portion 42, thereby enabling the thin-film transistor 20A to have a larger aspect ratio, thereby having a larger on-state current and reducing the power consumption of the thin-film transistor 20A.

[0063] Specifically, in this embodiment, the semiconductor device 2 further includes a third electrode 61 located between the second electrode 24B and the gate insulating layer 22, a second insulating layer 50 located on the side of the first insulating layer 40 away from the first metal layer 24, and a fourth electrode 62 located on the side of the second insulating layer 50 away from the first insulating layer 40; wherein, the third electrode 61 is connected to the second electrode 24B, the orthographic projection of the third electrode 61 on the insulating substrate 10 coincides at least partially with the orthographic projection of the second electrode 24B on the insulating substrate 10, the orthographic projection of the third electrode 61 on the insulating substrate 10 does not overlap with the first electrode 24A on the insulating substrate 10, and the orthographic projection of the third electrode 61 on the insulating substrate 10 does not overlap with the gate 21 on the insulating substrate 10; wherein, the third electrode 61 is one of a pixel electrode and a common electrode, and the fourth electrode 62 is the other of a pixel electrode and a common electrode.

[0064] Understandably, in combination Figure 1 Compared with the existing thin-film transistor layer 20 fabrication process, this embodiment does not require etching to create contact vias, so that the second electrode 24B can be connected to the third electrode 61 through the contact vias, further saving fabrication costs; and by setting the third electrode 61, the second electrode 24B and the fourth electrode 62 to be stacked sequentially on the insulating substrate, the thickness of the semiconductor device 2 is reduced.

[0065] Please combine Figure 4 and Figure 5 ;in, Figure 4 This is a second top cross-sectional view of the semiconductor device provided in the embodiments of this application; Figure 5 for Figure 4 A schematic diagram of the cross-sectional structure along the BB′ direction.

[0066] In this embodiment, the structure of the display panel is similar to / identical to the first structure of the semiconductor device provided in the above embodiments. Please refer to the description of the semiconductor device in the above embodiments for details, which will not be repeated here. The only difference between the two is:

[0067] In this embodiment, the conductive portion 33 is connected to the first electrode 24A, and the conductive portion 33 is insulated from the second electrode 24B. It can be understood that this embodiment includes a groove 230 between the first electrode 24A and the second electrode 24B in the active segment 23A. The depth of the groove 230 is less than the thickness of the active layer 23 and greater than the thickness of the conductor layer 231. The width of the groove 230 is equal to the distance between the first electrode 24A and the second electrode 24B. The semiconductor device 2 also includes components disposed in the groove... The compensation portion 30 within the groove 230 includes at least a conductive portion 33 connected to the first electrode 24A, thereby increasing the width of the first electrode 24A, which in turn reduces the channel length of the thin-film transistor 20A, increases the on-state current, and reduces the power consumption of the semiconductor device 2. Furthermore, by setting the conductive portion 33 to be insulated from the second electrode 24B, the first electrode 24A and the second electrode 24B are prevented from conducting, thus avoiding any impact on the electrical characteristics of the thin-film transistor 20A.

[0068] Furthermore, the first insulating layer 40 extends from the side of the first metal layer 24 away from the active layer 23 into the groove 230; wherein at least a portion of the first insulating layer 40 is located between the conductive portion 33 and the second electrode 24B.

[0069] Specifically, in this embodiment, the first insulating layer 40 includes a first insulator portion 41 and a second insulator portion 42 connected to each other. The orthographic projection of the first insulator portion 41 on the substrate covers the orthographic projection of the second electrode 24B on the substrate, thereby blocking water and oxygen and providing insulation for the second electrode 24B. The second insulator portion 42 is located in the groove 230 and is disposed between the compensation portion 30 and the second electrode 24B, thereby insulating the conductive portion 33 from the second electrode 24B and preventing the first electrode 24A from conducting with the second electrode 24B, thus affecting the electrical characteristics of the thin film transistor 20A.

[0070] This application also provides a method for fabricating a semiconductor device. Please refer to the embodiments thereof. Figure 2 , Figure 3 , Figure 6 Figures 7A to 7G ;in, Figure 6A flowchart illustrating the method for fabricating the semiconductor device provided in the embodiments of this application; Figures 7A to 7G for Figure 6 A flowchart illustrating the fabrication process of semiconductor devices.

[0071] In this embodiment, the method for fabricating the semiconductor device includes the following steps:

[0072] Step S100: Provide an insulating substrate 10.

[0073] When the insulating substrate 10 is a rigid substrate, the material can be metal or glass. When the insulating substrate 10 is a flexible substrate, the material can include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane-based resin, cellulose resin, siloxane resin, polyimide-based resin, and polyamide-based resin.

[0074] Step S200: A thin-film transistor layer 20 is formed on the insulating substrate 10. The thin-film transistor layer 20 includes an active layer 23 and a first metal layer 24 located on the active layer 23. The active layer 23 includes an active segment 23A and a conductor layer 231 stacked together. The conductor layer 231 includes a first conductor segment 23B and a second conductor segment 23C spaced apart on the active segment 23A. The first metal layer 24 includes a first electrode 24A connected to the first conductor segment 23B and a second electrode 24B connected to the second conductor segment 23C. The active layer 23 includes a groove 230 located between the first electrode 24A and the second electrode 24B. The depth of the groove 230 is less than the thickness of the active layer 23 and greater than the thickness of the conductor layer 231.

[0075] The method for manufacturing the semiconductor device further includes the following steps:

[0076] Step S300: A compensation portion 30 is formed on the side of the thin film transistor layer 20 away from the insulating substrate 10. The compensation portion 30 is disposed in the groove 230. The compensation portion 30 includes at least a conductive portion 33. The conductive portion 33 is connected to one of the first electrode 24A and the second electrode 24B, and the conductive portion 33 is insulated from the other of the first electrode 24A and the second electrode 24B.

[0077] Specifically, in this embodiment, in step S200, the method for manufacturing the semiconductor device further includes the following steps:

[0078] Step S201: Form a gate 21 on the insulating substrate 10, such as Figure 7AAs shown; wherein the material of the gate 21 includes, but is not limited to, one or more alloys of molybdenum (Mo), titanium (Ti), and nickel (Ni).

[0079] Step S202: A gate insulating layer 22 is formed on the side of the gate 21 away from the insulating substrate 10. The gate insulating layer 22 covers the gate 21, thereby blocking water and oxygen and providing insulation for the gate 21. Figure 7B As shown; wherein, the material of the gate insulating layer 22 includes, but is not limited to, monolayer silicon nitride (Si3N4), monolayer silicon dioxide (SiO2), and monolayer silicon oxynitride (SiON). x ), or a double-layer structure of the above membrane layers.

[0080] Step S203: An active layer 23 is formed on the side of the gate insulating layer 22 away from the gate 21, and the orthogonal projection of the gate 21 on the insulating substrate 10 covers the orthogonal projection of the active layer 23 on the insulating substrate 10.

[0081] Specifically, step S203 includes the following steps:

[0082] Step S2031: Deposit a first amorphous silicon (a-Si) layer on the gate insulating layer 22, and perform crystallization treatment on the first amorphous silicon layer to form a first polycrystalline silicon thin film.

[0083] Step S2032: Pattern the first polycrystalline silicon thin film to form the active segment 23A.

[0084] Step S2033: Deposit a second amorphous silicon (a-Si) layer on the active segment 23A, and perform crystallization treatment on the second amorphous silicon layer to form a second polycrystalline silicon thin film.

[0085] Step S2034: The second polycrystalline silicon thin film is patterned to form a second polycrystalline silicon pattern, and ion implantation is performed on the second polycrystalline silicon pattern to form a conductor layer 231. The active layer 23 includes the active segment 23A and the conductor layer 231 stacked together, such as... Figure 7C As shown; preferably, the conductor layer 231 is made of polycrystalline silicon with a high concentration of n-type impurities doped with silicide.

[0086] Step S204: A third electrode 61 is formed on the side of the gate insulating layer 22 away from the gate 21. The orthographic projection of the third electrode 61 on the insulating substrate 10 does not overlap with the orthographic projection of the active layer 23 on the insulating substrate 10, and the orthographic projection of the third electrode 61 on the insulating substrate 10 does not overlap with the gate 21 on the insulating substrate 10. Figure 7D As shown.

[0087] Step S205: A first metal layer 24 is formed on the side of the active layer 23 away from the gate insulating layer 22. The first metal layer 24 and the active layer 23 are patterned to form a slot 2300 passing through the first metal layer 24, the conductor layer 231, and a portion of the active segment 23A. The slot 2300 includes a first opening (not marked in the figure) passing through the first metal layer 24 and a groove 230 passing through the conductor layer 231 and a portion of the active segment 23A. The first opening and the groove 230 are interconnected. The first metal layer 24 forms a first electrode 24A and a second electrode 24B spaced apart. The conductor layer 231 forms a first conductor segment 23B and a second conductor segment 23C spaced apart. The first electrode 24A is connected to the first conductor segment 23B, and the second electrode 24B is connected to the second conductor segment 23C. The groove 230 is located between the first electrode 24A and the second electrode 24B. Figure 7E As shown.

[0088] Specifically, the orthographic projection of the first electrode 24A on the insulating substrate 10 covers the orthographic projection of the first conductor segment 23B on the insulating substrate 10, and the orthographic projection of the second electrode 24B on the insulating substrate 10 covers the orthographic projection of the second conductor segment 23C on the insulating substrate 10.

[0089] Furthermore, the second electrode 24B is connected to the third electrode 61, and the orthographic projection of the third electrode 61 on the insulating substrate 10 at least coincides with the orthographic projection of a portion of the second electrode 24B on the insulating substrate 10.

[0090] Step S206: A first insulating layer 40 is formed on the side of the first electrode 24A away from the active layer 23. The first insulating layer 40 extends from the side of the first electrode 24A away from the active layer 23 into the groove 230, as shown below. Figure 7F As shown; wherein, the material of the first insulating layer 40 includes, but is not limited to, monolayer silicon nitride (Si3N4), monolayer silicon dioxide (SiO2), and monolayer silicon oxynitride (SiON). x ), or a double-layer structure of the above membrane layers.

[0091] Furthermore, in this embodiment, in step S300, the method for manufacturing the semiconductor device further includes the following steps:

[0092] Step S301: A compensation portion 30 is formed on the side of the thin-film transistor layer 20 away from the insulating substrate 10. The compensation portion 30 is disposed within the groove 230. The compensation portion 30 includes a first compensation sub-part 31, a second compensation sub-part 32, and a conductive portion 33 stacked on the active segment 23A. The conductive portion 33 is connected to the second electrode 24B and is insulated from the first electrode 24A. Figure 7G As shown.

[0093] Specifically, the thickness of the compensation portion 30 is equal to the depth of the slot 2300. The side of the first compensation sub-part 31 away from the insulating substrate 10 is flush with the side of the active segment 23A away from the insulating substrate 10. The side of the second compensation sub-part 32 away from the insulating substrate 10 is flush with the side of the conductor layer 231 away from the insulating substrate 10. The side of the conductive portion 33 away from the insulating substrate 10 is flush with the side of the first metal layer 24 away from the insulating substrate 10. The orthographic projection of the conductive portion 33 on the insulating substrate 10 overlaps with the orthographic projection of the second compensation sub-part 32 on the insulating substrate 10. The orthographic projection of the second compensation sub-part 32 on the insulating substrate 10 overlaps with the orthographic projection of the first compensation sub-part 31 on the insulating substrate 10, thereby maintaining the flatness of the thin film transistor 20A.

[0094] Furthermore, the material of the first compensation sub-section 31 is the same as the material of the active section 23A, the material of the second compensation sub-section 32 is the same as the material of the conductor layer 231, and the material of the conductive section 33 is the same as the material of the first metal layer 24, thereby maintaining the electrical characteristics of the thin film transistor 20A.

[0095] Furthermore, the second insulator portion 42 is disposed between the compensation portion 30 and the first electrode 24A, thereby insulating the conductive portion 33 from the first electrode 24A and preventing the second electrode 24B from conducting with the first electrode 24A, thus affecting the electrical characteristics of the thin-film transistor 20A.

[0096] Specifically, in this embodiment, the method for manufacturing the semiconductor device further includes the following steps:

[0097] Step S400: A second insulating layer 50 and a fourth electrode 62 are sequentially formed on the side of the first insulating layer 40 away from the first electrode 24A. The second insulating layer 50 covers the interlayer insulating layer, the first insulating layer 40, the compensation portion 30, the second electrode 24B, and the third electrode 61, thereby providing water and oxygen barrier and insulation for the aforementioned film layer. The fourth electrode 62 is positioned corresponding to the third electrode 61. Figure 3As shown.

[0098] It is understood that in this embodiment, the thin-film transistor layer 20 includes a plurality of thin-film transistors 20A arranged in a matrix, with each thin-film transistor 20A corresponding to a sub-pixel region. The thin-film transistor 20A includes a gate 21, a gate insulating layer 22, an active layer 23, a first electrode 24A, and a second electrode 24B stacked together. The channel of the thin-film transistor 20A is located between the first conductor segment 23B and the second conductor segment 23C, that is, the length of the channel is equal to the width of the second insulator portion 42. Therefore, the length of the channel can be determined by the width of the second insulator portion 42. Thus, under the condition that the width of the channel is constant, this embodiment can shorten the length of the channel by reducing the width of the second insulator portion 42, thereby enabling the thin-film transistor 20A to have a larger aspect ratio, thereby having a larger on-state current and reducing the power consumption of the thin-film transistor 20A.

[0099] This embodiment provides an electronic device, which includes the semiconductor device described in any of the above embodiments.

[0100] It is understood that the semiconductor device has been described in detail in the above embodiments, and will not be repeated here.

[0101] In specific applications, the electronic device can be a display screen for devices such as smartphones, tablets, laptops, smart bracelets, smartwatches, smart glasses, smart helmets, desktop computers, smart TVs, or digital cameras, and can even be applied to electronic devices with flexible displays.

[0102] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0103] The above provides a detailed description of a semiconductor device and an electronic device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, include: Insulating substrate: A thin-film transistor layer is disposed on the insulating substrate, the thin-film transistor layer comprising: An active layer is disposed on the insulating substrate. The active layer includes an active segment and a conductor layer stacked together. The conductor layer includes a first conductor segment and a second conductor segment spaced apart on the active segment. A first metal layer is disposed on the side of the active layer away from the insulating substrate, and the first metal layer includes a first electrode connected to the first conductor segment and a second electrode connected to the second conductor segment; The active layer includes a groove located between the first electrode and the second electrode, wherein the depth of the groove is less than the thickness of the active layer and greater than the thickness of the conductor layer; The semiconductor device further includes a compensation portion disposed within the groove. The compensation portion includes a conductive portion and a first compensation sub-part and a second compensation sub-part located between the conductive portion and the active segment. The sum of the thickness of the first compensation sub-part and the thickness of the second compensation sub-part is equal to the depth of the groove. The second compensation sub-part is located between the first compensation sub-part and the conductive portion. The conductive portion is connected to one of the first electrode and the second electrode, and the conductive portion is insulated from the other of the first electrode and the second electrode.

2. The semiconductor device according to claim 1, characterized in that, The compensation section includes a first compensation sub-section and a second compensation sub-section located between the conductive section and the active section. The sum of the thickness of the first compensation sub-section and the thickness of the second compensation sub-section is less than or equal to the depth of the groove. The conductive section extends from the second compensation sub-section in a direction away from the groove.

3. The semiconductor device according to claim 2, characterized in that, The orthographic projection of the conductive part on the insulating substrate overlaps with the orthographic projection of the second compensator on the insulating substrate, and the orthographic projection of the second compensator on the insulating substrate overlaps with the orthographic projection of the first compensator on the insulating substrate.

4. The semiconductor device according to claim 2, characterized in that, The material of the first compensation sub-section is the same as the material of the active section, the material of the second compensation sub-section is the same as the material of the conductor layer, and the material of the conductive section is the same as the material of the first metal layer.

5. The semiconductor device according to claim 1, characterized in that, The side of the first compensation sub-part away from the insulating substrate is flush with the side of the active segment away from the insulating substrate, the side of the second compensation sub-part away from the insulating substrate is flush with the side of the conductor layer away from the insulating substrate, and the side of the conductive portion away from the insulating substrate is flush with the side of the first metal layer away from the insulating substrate.

6. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a first insulating layer located on the side of the first metal layer away from the active layer, the first insulating layer extending from the side of the first metal layer away from the active layer into the groove; Wherein, at least a portion of the first insulating layer is located between the conductive portion and the first electrode, or at least a portion of the first insulating layer is located between the conductive portion and the second electrode.

7. The semiconductor device according to claim 6, characterized in that, The conductive part is connected to the first electrode; The first insulating layer includes a first insulator portion and a second insulator portion that are connected to each other. The orthographic projection of the first insulator portion on the substrate covers the orthographic projection of the second electrode on the substrate. The second insulator portion is located in the groove and is disposed between the compensation portion and the second electrode.

8. The semiconductor device according to claim 6, characterized in that, The conductive part is connected to the second electrode; The first insulating layer includes a first insulator portion and a second insulator portion that are connected to each other. The orthographic projection of the first insulator portion on the substrate covers the orthographic projection of the first electrode on the substrate. The second insulator portion is located in the groove and is disposed between the compensation portion and the first electrode.

9. The semiconductor device according to claim 1, characterized in that, The thin-film transistor layer includes a gate, a gate insulating layer, the active layer, the first electrode, and the second electrode, which are stacked sequentially. Wherein, the first electrode covers the first conductor segment, the second electrode covers the second conductor segment, and the orthogonal projection of the gate on the insulating substrate covers the orthogonal projection of the active layer on the insulating substrate.

10. An electronic device, characterized in that, The electronic device includes the semiconductor device according to any one of claims 1-9.

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