A graphene transistor and a method of manufacturing the same
By incorporating lateral protrusions and plug-slot structures into graphene transistors, the problem of low carrier mobility is solved, thereby improving carrier mobility and enhancing transistor stability and heat dissipation performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHONGQING GRAPHENE RES INST CO LTD
- Filing Date
- 2022-12-16
- Publication Date
- 2026-05-29
AI Technical Summary
The carrier mobility in graphene transistors is greatly affected by substrate roughness and impurities, leading to performance degradation.
Multiple horizontally parallel protrusions are arranged between the graphene channel layer and the gate structure to reduce direct contact between the graphene and the substrate. Plugs and slots are provided on the source and drain to improve the contact area and stability. Meanwhile, grooves are provided on the shielding layer to enhance heat dissipation.
This improved the carrier mobility of graphene, enhanced the stability and heat dissipation performance of transistors, and reduced the impact of impurity scattering.
Smart Images
Figure CN115799313B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of transistors, and more specifically to a graphene transistor and its manufacturing method. Background Technology
[0002] Graphene field-effect transistors (GFETs) are transistors made using the semiconductor properties of graphene. Graphene is used to form the channel of a GFET. Since the theoretical carrier mobility of graphene is about 10 times that of silicon, theoretically, electrons (or holes) in graphene can form the largest current under the same electric field strength. Therefore, applying graphene to transistors can improve transistor performance.
[0003] like Figure 1 The diagram illustrates a graphene transistor in the prior art, comprising a substrate 1, a gate structure 2 and a conductive layer 9 on the substrate 1, and a graphene channel layer 10 on the gate structure 2. The graphene channel layer 10 has source and drain terminals at both ends. The source includes a first source 5 and a second source 4, and the drain includes a first drain 7 and a second drain 8. Both the first source 5 and the second source 4 are disposed on the substrate 1 and are electrically connected through the substrate 1. Both the first drain 7 and the second drain 8 are disposed on the conductive layer 9 and are electrically connected through the conductive layer 9. The first source 5 and the first drain 7 are opposite to each other, while the second source 4 and the second drain 8 are far apart, thus connecting the first source 5 and the first drain 7 to the ends of the graphene channel layer 10.
[0004] In the graphene transistor described above, the graphene channel layer 10 is attached to the substrate 1. However, the roughness of the substrate 1 itself and the impurities attached to the surface of the substrate 1 will destroy the periodicity of the graphene lattice through long-range Coulomb scattering and short-range non-Coulomb scattering. This greatly reduces the superior carrier mobility performance of graphene and reduces the performance of the graphene transistor. Summary of the Invention
[0005] The present invention aims to provide a graphene transistor and a method for manufacturing the same, in order to solve the problem of low carrier mobility in graphene transistors.
[0006] To achieve the above objectives, the present invention adopts the following technical solution: a graphene transistor, comprising a substrate, a conductive layer and a gate structure disposed on the substrate, a first drain and a second drain disposed on the conductive layer, the first drain and the second drain being electrically connected through the conductive layer; a first source and a second source disposed on the substrate, the first source and the second source being electrically connected through the substrate, the first source and the first drain being opposite to each other, the gate structure being located between the first drain and the first source, a graphene channel layer being disposed between the first drain and the first source, a plurality of protrusions being disposed on the top of the gate structure, the plurality of protrusions being arranged in parallel laterally, with gaps between adjacent protrusions; the graphene channel layer being located on the protrusions on the top of the gate structure.
[0007] The principle and advantages of this scheme are as follows: The graphene channel layer in this scheme is located on the convex strip. Since there is a gap between adjacent convex strips, the graphene channel layer and the upper surface of the gate structure will not be in full contact, which reduces the influence of the substrate on the graphene and thus improves the graphene carrier mobility.
[0008] In this design, the top protrusion of the gate structure is a horizontal strip structure. Thus, the gap between two adjacent protrusions is also a horizontal and continuous strip. Compared to other gap shapes, such as discontinuous grooves, the total area of the gap at the top of the gate structure is larger, which can minimize the contact area between the graphene channel layer and the top of the gate structure, resulting in a better improvement in the graphene carrier mobility.
[0009] Preferably, as an improvement, the cross-sectional shape of the protrusion is semi-circular, and the graphene channel layer is located on the arc-shaped surface of the protrusion. In this scheme, the cross-sectional shape of the protrusion is semi-circular. Compared with creating grooves in the gate structure, the contact area between the protrusion and the graphene channel layer is theoretically a line at the microscopic level (rather than a surface contact), and the contact area between the protrusion and the graphene channel layer is smaller. At the same time, the top of the protrusion is arc-shaped, and impurities at the top of the protrusion can slide down along the arc surface of the protrusion and accumulate at the bottom of the gap. Impurities are less likely to accumulate at the top of the protrusion, thereby reducing the possibility of impurities contacting the graphene channel layer. This reduces the disruption of the periodicity of the graphene lattice by impurities through long-range Coulomb scattering and short-range non-Coulomb scattering, and improves the graphene carrier mobility. In addition, the top of the protrusion is thin and the bottom is thick, and there are multiple protrusions, so that multiple protrusions can provide stable support for the graphene channel layer.
[0010] Preferably, as an improvement, multiple first slots are provided at both ends of the graphene channel layer, and the multiple first slots are arranged along the width direction of the graphene channel layer; multiple first plugs are integrally formed on both the first source and the first drain, and the first plugs are inserted into the first slots; a second slot is formed between adjacent first plugs, and a second plug is formed between two adjacent first slots at the end of the graphene channel layer, and the second plug is located in the second slot; there is a distance between the end of the first plug and the bottom of the first slot, and between the end of the second plug and the bottom of the second slot.
[0011] Because the contact area between the graphene channel layer and the top of the gate structure is reduced, the adhesion between the graphene channel layer and the gate structure is weakened. To address this issue, this solution uses a first plug and a second plug that are interlocked, thereby increasing the contact area between the first source and the graphene channel layer, as well as the contact connection area between the first drain and the graphene channel layer. This makes it less likely for the graphene channel layer to detach from the first source and the first drain. Simultaneously, the increased contact connection area ensures better electrical contact between the ends of the graphene channel layer and the first source and the first drain, respectively, and also improves the electron flow rate between the first source, the first drain, and the graphene channel layer.
[0012] In addition, in this design, there is a distance between the end of the first plug and the bottom of the first slot, and between the end of the second plug and the bottom of the second slot. This ensures that the end of the first plug and the bottom of the first slot do not abut against each other, and the end of the second plug and the bottom of the second slot do not abut against each other. When the transistor is in use, since the first source and the first drain are made of metal, they are prone to thermal expansion due to heat generation. This design provides space for the expansion of the first source and the first drain, preventing the expansion of the first source and the first drain from pushing and deforming the graphene channel layer and causing it to detach from the gate structure, thus ensuring the stability of the transistor.
[0013] Preferably, as an improvement, the distance is 100-1000nm.
[0014] A method for manufacturing graphene transistors, characterized by comprising the following steps:
[0015] S1. A silicon oxide layer is formed on the substrate; a gate structure precursor and a conductivity layer are formed below the silicon oxide layer on the substrate.
[0016] S2. Part of the silicon oxide layer on the substrate is removed to expose the gate structure precursor, and a first silicon oxide layer is formed on the conductive layer and a second silicon oxide layer is formed on the substrate.
[0017] S3. Multiple horizontally parallel protrusions are etched on the top of the gate structure precursor, with gaps between adjacent protrusions. Then, a dielectric is covered on the top of the gate structure precursor to form a gate structure.
[0018] S4. A graphene channel layer is formed on the gate structure, and the graphene channel layer is located on the protrusion.
[0019] S5. A first drain and a second drain are respectively provided on both sides of the first silicon oxide layer, and a first source and a second source are respectively provided on both sides of the second silicon oxide layer. The first source and the first drain are opposite to each other, and the two ends of the graphene channel layer are respectively connected to the first source and the first drain.
[0020] This manufacturing method can produce graphene transistors with structures such as raised stripes. The graphene channel layer and the upper surface of the gate structure in the prepared graphene transistor will not be in full contact, which reduces the influence of the substrate on the graphene and thus improves the graphene carrier mobility.
[0021] Preferably, as an improvement, in step S4, multiple first slots are fabricated at both ends of the graphene channel layer;
[0022] In step S5, both the first source and the first drain are formed by metal deposition. During metal deposition, the first source and the first drain are deposited and embedded in the first slot, and the ends of the first source and the first drain deposited and embedded in the first slot are both separated from the bottom of the first slot. Then, the first source and the first drain are patterned by photolithography and etched to remove the parts of the first source and the first drain located above the graphene channel layer and to ensure that the first source and the first drain are separated from the ends of the first plug.
[0023] Therefore, by adopting this scheme, a structure in which the first plug and the second plug are interlocked can be fabricated. It is not necessary to first fabricate the first plug at the end of the graphene channel layer, then fabricate the second plug on the first source and the first drain, and finally interlock the first plug and the second plug. Therefore, the fabrication method of this scheme allows the first plug and the second plug to be automatically interlocked. The fabrication method is simple and does not require measures to insert the first plug into the first slot and the second plug into the second slot.
[0024] Preferably, as an improvement, it also includes
[0025] S6. A shielding layer is bonded between the first silicon oxide layer and the second silicon oxide layer. The shielding layer has a groove on its side away from the substrate, and then a graphene thermal conductive layer is disposed in the groove.
[0026] The shielding layer is used to protect the graphene channel layer; however, its presence can affect heat dissipation. Therefore, this design incorporates grooves in the shielding layer, with a graphene thermally conductive layer placed within these grooves. This leverages graphene's excellent thermal conductivity to improve the shielding layer's heat dissipation performance, allowing heat generated during transistor operation to be dissipated more effectively. The grooves are chosen because they reduce the thickness of the shielding layer beneath the graphene thermally conductive layer, minimizing the path of heat transfer and resulting in better heat conduction and dissipation.
[0027] Preferably, as an improvement, the graphene channel layer is a graphene film.
[0028] Preferably, as an improvement, the graphene film is formed by chemical vapor deposition.
[0029] Preferably, as an improvement, the deposited metal is at least one of Ti, Pt, Cr, Au, Al, Ni, Cu, and Ag. Attached Figure Description
[0030] Figure 1 This is a schematic diagram of the structure of a graphene transistor in the prior art.
[0031] Figure 2 This is a top-view diagram showing the connection between the first source, the graphene channel layer, and the first drain.
[0032] Figure 3 This is a schematic diagram of the gate structure.
[0033] Figure 4 This is a 3D view of the gate structure.
[0034] Figure 5 This is a cross-sectional view of the shielding layer. Detailed Implementation
[0035] The following detailed description illustrates the specific implementation method:
[0036] The reference numerals in the accompanying drawings include: substrate 1, gate structure 2, gap 3, second drain 8, first drain 7, shielding layer 6, first source 5, second source 4, conductive layer 9, graphene channel layer 10, first connector 11, first slot 12, protrusion 13, second slot 14, second connector 15, graphene thermal conductive layer 16, first silicon oxide layer 18, and second silicon oxide layer 17.
[0037] Example 1
[0038] The basics are as follows: Figure 1 , Figure 3 and Figure 4 As shown.
[0039] A graphene transistor, combined with Figure 1 As shown, the system includes a substrate 1, on which a conductive layer 9 made of metal and a gate structure 2 are disposed. A first drain 7 and a second drain 8 are disposed on the conductive layer 9, with the first drain 7 located to the right of the second drain 8. The first drain 7 and the second drain 8 are electrically connected through the conductive layer 9. A first source 5 and a second source 4 are disposed on the substrate 1, with the first source 5 located to the left of the second source 4. The first source 5 and the second source 4 are electrically connected through the substrate 1, with the first source 5 and the first drain 7 facing each other. The gate structure 2 is located between the first drain 7 and the first source 5. A graphene channel layer 10 is disposed between the first drain 7 and the first source 5. The two ends of the graphene channel layer 10 are in contact with the first source 5 and the first drain 7, respectively. The graphene channel layer 10 is a graphene thin film formed by chemical vapor deposition.
[0040] In this embodiment, the first source 5, the second source 4, the first drain 7, and the second drain 8 are all made of metal, such as at least one of Ti, Pt, Cr, Au, Al, Ni, Cu, and Ag.
[0041] The difference between this embodiment and the prior art is that: Figure 1 The top of gate structure 2 is flat, while in this embodiment, combined with Figure 3 and Figure 4 As shown, the top of the gate structure 2 is provided with multiple protrusions 13, which are arranged horizontally in parallel, with gaps 3 between adjacent protrusions 13; the graphene channel layer 10 is located on the protrusions 13 at the top of the gate structure. In this embodiment, the cross-sectional shape of the protrusions 13 is semi-circular, and the graphene channel layer 10 is located on the arc-shaped surface of the protrusions 13. In this embodiment, the diameter of the protrusions 13 is 500 nm, and the center-to-center distance between two adjacent protrusions 13 is 600 nm.
[0042] In this embodiment, substrate 1 is a silicon substrate. Substrate 1 can be a doped semiconductor substrate, which can be an n-type doped semiconductor substrate or a p-type doped semiconductor substrate.
[0043] The gate structure 2 in this embodiment includes a known gate electrode layer and a gate dielectric layer. The gate electrode layer is disposed on the substrate 1, and the gate dielectric layer is disposed on the gate electrode layer. That is, the main structure of the gate structure 2 is the gate electrode layer, and a gate dielectric layer is disposed on top of the gate electrode layer.
[0044] In this embodiment, the gate electrode layer is formed of a metallic material (e.g., at least one of Ti, Pt, Cr, Au, Al, Ni, Cu, and Ag). A silicon dioxide insulating layer is formed between the gate electrode layer and the substrate 1. The gate dielectric layer is at least one of HfO2, ZrO2, and Al2O3.
[0045] This embodiment also discloses a method for manufacturing graphene transistors, including the following steps:
[0046] S1. A silicon oxide layer is formed on the substrate 1, for example, a silicon dioxide layer is grown; a gate structure precursor and a conductive layer 9 are formed below the silicon oxide layer on the substrate 1. The gate structure precursor and conductive layer 9 are formed by: photolithographically patterning the substrate 1 with the silicon oxide layer to expose the area where the gate structure precursor and conductive layer 9 are to be formed; and locally performing n-type heavy doping on the p-type doped silicon substrate 1 to form the gate structure precursor and conductive layer 9.
[0047] S2. Part of the silicon oxide layer on the substrate 1 is removed to expose the gate structure precursor. A first silicon oxide layer 18 is formed on the conductive layer 9 and a second silicon oxide layer 17 is formed on the substrate 1. That is, the first silicon oxide layer 18 and the second silicon oxide layer 17 are the remaining products of the silicon oxide layer. The method for removing part of the silicon oxide layer is to perform photolithographic patterning on the silicon oxide layer to expose the area of the silicon oxide layer to be removed, and then etch the exposed area.
[0048] S3. Etch multiple horizontally parallel protrusions 13 on the top of the gate structure precursor (the specific etching method is: form a photoresist layer on the gate structure precursor, perform photolithography patterning on the photoresist layer to expose the area to be etched, and then perform plasma dry etching) with gaps 3 between adjacent protrusions 13. Then, form a dielectric (i.e., gate dielectric layer) on the top of the gate structure precursor using atomic layer evaporation deposition process, thereby forming the gate structure 2 (the gate structure 2 includes the gate dielectric layer and the gate electrode layer).
[0049] S4. A graphene channel layer 10 is formed on the gate structure 2, and the graphene channel layer 10 is located on the protrusion 13; the graphene channel layer 10 is a thin film prepared by CVD chemical vapor deposition.
[0050] S5. A first drain 7 and a second drain 8 are respectively disposed on both sides of the first silicon oxide layer 18, and a first source 5 and a second source 4 are respectively disposed on both sides of the second silicon oxide layer 17. The first source 5 and the first drain 7 are opposite to each other, and the two ends of the graphene channel layer 10 are respectively connected to the first source 5 and the first drain 7. In this embodiment, the first source 5, the first drain 7, the second source 4, and the second drain 8 are all formed by metal deposition.
[0051] Through this embodiment, compared to Figure 1 In the graphene transistor structure, the graphene channel layer 10 is located on the protrusion 13. Since there is a gap 3 between adjacent protrusions 13, the graphene channel layer 10 and the upper surface of the gate structure 2 will not be in full contact, which reduces the influence of the substrate 1 on the graphene and thus improves the graphene carrier mobility.
[0052] Example 2
[0053] Combination Figure 2As shown, in this embodiment, multiple first slots 12 are provided at both ends of the graphene channel layer 10, and the multiple first slots 12 are arranged along the width direction of the graphene channel layer 10. Multiple first plugs 11 are integrally formed on both the first source electrode 5 and the first drain electrode 7, and the first plugs 11 are inserted into the first slots 12. A second slot 14 is formed between adjacent first plugs 11, and a second plug 15 is formed between two adjacent first slots 12 at the end of the graphene channel layer 10. The second plug 15 is located in the second slot 14. There is a distance between the end of the first plug 11 and the bottom of the first slot 12, and between the end of the second plug 15 and the bottom of the second slot 14. In this embodiment, the distance is 100-1000 nm, preferably 300 μm.
[0054] Meanwhile, this embodiment differs from Embodiment 1 in its method of manufacturing the graphene transistor. Specifically, in step S4, multiple first slots 12 are fabricated at both ends of the graphene channel layer 10. The fabrication method involves first performing photolithography patterning on the ends of the graphene channel layer 10, and then etching the exposed areas to form multiple first slots 12 arranged along the width direction of the graphene channel layer 10. The portion of the graphene channel layer 10 located between two adjacent first slots 12 forms the second connector 15.
[0055] In step S5, both the first source electrode 5 and the first drain electrode 7 are formed by metal deposition. During metal deposition, the first source electrode 5 and the first drain electrode 7 are first deposited and embedded into the first slot 12 respectively, and there is a distance between the first source electrode 5 and the first drain electrode 7 and the bottom of the first slot 12, that is, the first source electrode 5 and the first drain electrode 7 will not fill the bottom of the first slot 12. Then, the first source electrode 5 and the first drain electrode 7 are photolithographically patterned and etched to remove the part of the first source electrode 5 and the first drain electrode 7 located above the graphene channel layer 10 (the part above the second plug 15) (thereby forming the second slot 14 on the first source electrode 5 and the first drain electrode 7), and to make there a distance between the first source electrode 5 and the first drain electrode 7 and the end of the first plug 11, that is, to increase the depth of the second slot 14, and the end of the second plug 15 will not abut against the bottom of the second slot 14.
[0056] In this embodiment, there is a distance between the end of the first plug 11 and the bottom of the first slot 12, and between the end of the second plug 15 and the bottom of the second slot 14. This ensures that the end of the first plug 11 and the bottom of the first slot 12 do not abut, and the end of the second plug 15 and the bottom of the second slot 14 do not abut. When the transistor is in use, since the first source 5 and the first drain 7 are made of metal, they are prone to thermal expansion due to heat generation. This provides space for expansion for both the first source 5 and the first drain 7, preventing them from pushing and deforming the graphene channel layer 10 and detaching from the gate structure 2, thus ensuring the stability of the transistor.
[0057] Example 3
[0058] Combination Figure 1 and Figure 5 As shown, this embodiment, based on the manufacturing method of embodiment 1, further includes,
[0059] S6. A shielding layer 6 is bonded between the first silicon oxide layer 18 and the second silicon oxide layer 17 using a vacuum bonding machine. The shielding layer 6 is made of silicon oxide. Then, a photolithographic pattern is formed on the side of the shielding layer 6 away from the substrate 1, and a groove is formed. Then, a graphene thermal conductive layer 16 is placed in the groove. The graphene thermal conductive layer 16 is a graphene film produced by CVD chemical vapor deposition and transferred into the groove.
[0060] In this design, a groove is formed on the shielding layer 6, and a graphene thermally conductive layer 16 is placed within the groove. This utilizes the excellent thermal conductivity of graphene to improve the heat dissipation performance of the shielding layer 6, enabling the heat generated during transistor operation to be dissipated promptly and reducing the obstruction of heat dissipation by the shielding layer 6. The groove is designed to reduce the thickness of the shielding layer 6 below the graphene thermally conductive layer 16, thus reducing the path for heat transfer to the graphene thermally conductive layer 16 and resulting in better heat conduction and dissipation.
[0061] The above descriptions are merely embodiments of the present invention, and common knowledge such as specific technical solutions and / or characteristics are not described in detail here. It should be noted that those skilled in the art can make various modifications and improvements without departing from the technical solutions of the present invention, and these should also be considered within the scope of protection of the present invention. These modifications and improvements will not affect the effectiveness of the implementation of the present invention or the practicality of the patent. The scope of protection claimed in this application should be determined by the content of its claims, and the specific embodiments described in the specification can be used to interpret the content of the claims.
Claims
1. A graphene transistor, comprising a substrate, wherein a conductive layer and a gate structure are disposed on the substrate, a first drain and a second drain are disposed on the conductive layer, the first drain and the second drain being electrically connected through the conductive layer; a first source and a second source are disposed on the substrate, the first source and the second source being electrically connected through the substrate, the first source and the first drain being opposite to each other, the gate structure being located between the first drain and the first source, and a graphene channel layer being disposed between the first drain and the first source, characterized in that: The top of the gate structure is provided with multiple protrusions, which are arranged horizontally in parallel and with gaps between adjacent protrusions; the graphene channel layer is located on the protrusions at the top of the gate structure. Multiple first slots are provided at both ends of the graphene channel layer, and the multiple first slots are arranged along the width direction of the graphene channel layer; multiple first plugs are integrally formed on the first source and the first drain, and the first plugs are inserted into the first slots; a second slot is formed between adjacent first plugs, and a second plug is formed between two adjacent first slots at the end of the graphene channel layer, and the second plug is located in the second slot; there is a distance between the end of the first plug and the bottom of the first slot, and between the end of the second plug and the bottom of the second slot.
2. The graphene transistor according to claim 1, characterized in that: The cross-sectional shape of the protrusion is semi-circular, and the graphene channel layer is located on the arc-shaped surface of the protrusion.
3. A graphene transistor according to claim 1, characterized in that: The distance is 100-1000nm.
4. A method for manufacturing a graphene transistor, characterized in that: Includes the following steps: S1. A silicon oxide layer is formed on the substrate; a gate structure precursor and a conductivity layer are formed below the silicon oxide layer on the substrate. S2. Part of the silicon oxide layer on the substrate is removed to expose the gate structure precursor, and a first silicon oxide layer is formed on the conductive layer and a second silicon oxide layer is formed on the substrate. S3. Multiple horizontally parallel protrusions are etched on the top of the gate structure precursor, with gaps between adjacent protrusions. Then, a dielectric is covered on the top of the gate structure precursor to form a gate structure. S4. A graphene channel layer is formed on the gate structure, and the graphene channel layer is located on the convex strip; multiple first slots are processed at both ends of the graphene channel layer. S5. A first drain and a second drain are respectively disposed on both sides of the first silicon oxide layer, and a first source and a second source are respectively disposed on both sides of the second silicon oxide layer. The first source and the first drain are opposite to each other, and the two ends of the graphene channel layer are respectively connected to the first source and the first drain. The first source and the first drain are both formed by metal deposition. During metal deposition, the first source and the first drain are respectively deposited and embedded in the first slot, and the ends of the first source and the first drain deposited and embedded in the first slot are both at a distance from the bottom of the first slot. Then, the first source and the first drain are photolithographically patterned and etched to remove the parts of the first source and the first drain located above the graphene channel layer and to make the first source and the first drain both at a distance from the end of the first plug.
5. The method for manufacturing a graphene transistor according to claim 4, characterized in that: Also includes S6. A shielding layer is bonded between the first silicon oxide layer and the second silicon oxide layer. The shielding layer has a groove on its side away from the substrate, and then a graphene thermally conductive layer is disposed in the groove.
6. The method for manufacturing a graphene transistor according to claim 4, characterized in that: The graphene channel layer is a graphene film.
7. A method for manufacturing a graphene transistor according to claim 6, characterized in that: The graphene film was formed by chemical vapor deposition.
8. A method for manufacturing a graphene transistor according to claim 4, characterized in that: The deposited metal is at least one of Ti, Pt, Cr, Au, Al, Ni, Cu, and Ag.