Semiconductor device, manufacturing method thereof, and memory

Abstract

The embodiments of the present disclosure disclose a semiconductor device, a manufacturing method thereof, and a memory. The semiconductor device includes: an active layer, including a channel region and a source region and a drain region located on both sides of the channel region; a gate dielectric layer, located on the channel region; a gate conductive layer, located on the gate dielectric layer; a first isolation layer, located on the gate dielectric layer and covering the sidewalls of the gate conductive layer; a first insulating layer, including a first part and a second part, the first part covering the gate dielectric layer and the sidewalls of the first isolation layer close to the drain region, the second part being located on the drain region; a second isolation layer, located on the second part and covering the sidewalls of the first part.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and a memory. Background Art

[0002] To improve the integration density and cost-effectiveness of semiconductor devices, their feature sizes are continuously shrinking. On the one hand, this can increase the operating speed and reduce power consumption of semiconductor devices. On the other hand, this allows more components to be integrated onto the same substrate, which in turn improves the integration density and cost-effectiveness of semiconductor devices.

[0003] However, as the feature size of semiconductor devices continues to shrink, the feature size of transistors in semiconductor devices is also shrinking. This shrinking feature size poses greater challenges to transistor performance, such as reduced transistor reliability. Summary of the Invention

[0004] According to a first aspect of an embodiment of the present disclosure, there is provided a semiconductor device, including:

[0005] An active layer comprising a channel region and a source region and a drain region located on both sides of the channel region;

[0006] a gate dielectric layer, located on the channel region;

[0007] a gate conductive layer, located on the gate dielectric layer;

[0008] a first isolation layer, located on the gate dielectric layer and covering a sidewall of the gate conductive layer;

[0009] a first insulating layer, comprising a first portion and a second portion, wherein the first portion covers the gate dielectric layer and a sidewall of the first isolation layer close to the drain region, and the second portion is located on the drain region;

[0010] The second isolation layer is located on the second portion and covers the sidewall of the first portion.

[0011] In some embodiments, a material of the first insulating layer is the same as a material of the gate dielectric layer.

[0012] In some embodiments, a thickness of the second portion between the second isolation layer and the active layer is less than a thickness of the gate dielectric layer between the first isolation layer and the active layer.

[0013] In some embodiments, a bottom surface of the second isolation layer is located between a bottom surface of the gate dielectric layer and a top surface of the gate dielectric layer.

[0014] In some embodiments, the semiconductor device further comprises:

[0015] a second insulating layer, comprising a third portion and a fourth portion, the third portion covering the gate dielectric layer and a sidewall of the first isolation layer close to the source region, and the fourth portion being located on the source region;

[0016] The third isolation layer is located on the fourth portion and covers the sidewall of the third portion.

[0017] In some embodiments, a thickness of the fourth portion between the third isolation layer and the active layer is less than a thickness of the gate dielectric layer between the first isolation layer and the active layer.

[0018] In some embodiments, the constituent materials of the first isolation layer and the second isolation layer include: silicon nitride;

[0019] The first insulating layer is made of silicon oxide.

[0020] In some embodiments, the drain region includes: a first sub-drain region and a second sub-drain region; wherein the first sub-drain region is located between the channel region and the second sub-drain region; and the doping concentration of the first sub-drain region is less than the doping concentration of the second sub-drain region.

[0021] In some embodiments, the semiconductor device further comprises:

[0022] A third insulating layer covers the second portion and side walls of the second isolation layer.

[0023] According to a second aspect of an embodiment of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising:

[0024] forming an active layer; wherein the active layer includes a channel region and a source region and a drain region located on both sides of the channel region;

[0025] forming a gate dielectric layer on the channel region;

[0026] forming a gate conductive layer on the gate dielectric layer;

[0027] forming a first isolation layer on the gate dielectric layer; wherein the first isolation layer covers the sidewalls of the gate conductive layer;

[0028] After forming the first isolation layer, forming a first insulating layer; wherein the first insulating layer includes a first portion and a second portion, the first portion covers the gate dielectric layer and a sidewall of the first isolation layer close to the drain region, and the second portion is located on the drain region;

[0029] A second isolation layer is formed on the second portion; wherein the second isolation layer covers the sidewall of the first portion.

[0030] In some embodiments, the manufacturing method further comprises:

[0031] When forming the first insulating layer, forming a second insulating layer; wherein the second insulating layer includes a third portion and a fourth portion, the third portion covers the sidewalls of the gate dielectric layer and the first isolation layer close to the source region, and the fourth portion is located on the source region;

[0032] When the second isolation layer is formed on the second portion, a third isolation layer is formed on the fourth portion; wherein the third isolation layer covers the sidewall of the third portion.

[0033] In some embodiments, forming a second insulating layer when forming the first insulating layer includes:

[0034] After forming the first isolation layer, forming an insulating material layer covering the source region, the gate dielectric layer, the first isolation layer and the drain region;

[0035] The insulating material layer covering the top of the first isolation layer is etched in a direction toward the active layer to form the first insulating layer and the second insulating layer respectively.

[0036] In some embodiments, when forming the second isolation layer on the second portion, forming the third isolation layer on the fourth portion includes:

[0037] Before etching the insulating material layer, forming an isolation material layer covering the insulating material layer;

[0038] The isolation material layer covering the top of the insulating material layer is etched in a direction toward the active layer to form the second isolation layer and the third isolation layer respectively.

[0039] In some embodiments, the gate conductive layer includes: a first sub-conductive layer, a conductive connecting layer, and a second sub-conductive layer that are stacked;

[0040] The forming of a gate conductive layer on the gate dielectric layer comprises:

[0041] forming a first sub-conductive material layer on the gate dielectric layer;

[0042] forming a connection material layer covering the first sub-conductive material layer;

[0043] forming a second sub-conductive material layer covering the connecting material layer;

[0044] The second sub-conductive material layer, the connecting material layer and the first sub-conductive material layer are etched in a direction toward the active layer; wherein the remaining second sub-conductive material layer is the second sub-conductive layer, the remaining connecting material layer is the connecting layer, and the remaining first sub-conductive material layer is the first sub-conductive layer.

[0045] In some embodiments, the constituent materials of the first isolation layer and the second isolation layer include: silicon nitride;

[0046] The first insulating layer is made of silicon oxide.

[0047] In some embodiments, the drain region includes: a first sub-drain region and a second sub-drain region;

[0048] The forming of the active layer comprises:

[0049] providing a substrate;

[0050] performing a first doping operation on the substrate to form the first sub-drain region;

[0051] A second doping is performed on the substrate to form the second sub-drain region; the first sub-drain region is located between the channel region and the second sub-drain region; and a doping concentration of the first doping is less than a doping concentration of the second doping.

[0052] In some embodiments, the manufacturing method further includes: forming a third insulating layer covering the second portion and a sidewall of the second isolation layer.

[0053] According to a third aspect of the embodiments of the present disclosure, a memory is provided, comprising the semiconductor device described in any one of the above embodiments.

[0054] In the embodiment of the present disclosure, a composite sidewall structure including a first insulating layer and a second isolation layer is provided on the sidewalls of the gate dielectric layer and the first isolation layer near the drain region. The charge trap centers of the second isolation layer can capture hot carriers generated in the channel region, thereby modulating the accumulated position of the hot carriers, and then modulating the electric field in the channel region, prolonging the time for hot carrier injection into the gate dielectric layer, which is beneficial to delaying the occurrence of abnormal hot carrier injection failure, that is, it is beneficial to slow down the degradation of transistor performance and improve the reliability of semiconductor devices.

[0055] Moreover, by providing a first insulating layer between the gate dielectric layer and the second isolation layer, the first insulating layer can at least prolong the injection of hot carriers captured by the charge trap centers of the second isolation layer into the gate dielectric layer, that is, the composite sidewall structure is more conducive to delaying the occurrence of abnormal hot carrier injection failure, that is, it is more conducive to slowing down the degradation of semiconductor device performance and further improving the reliability of semiconductor devices.

[0056] In addition, by providing the first insulating layer between the first isolation layer and the second isolation layer, the distance between the first isolation layer and the second isolation layer can be increased, which is beneficial to reducing the probability of a strong negative charge center appearing at the edge of the gate dielectric layer close to the second isolation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1a and Figure 1b is a schematic structural diagram of a semiconductor device according to an exemplary embodiment;

[0058] Figure 1c is a test data diagram of a semiconductor device according to an exemplary embodiment;

[0059] Figure 1d is a schematic diagram showing a failure process of a semiconductor device according to an exemplary embodiment;

[0060] Figure 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure;

[0061] Figure 3 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0062] Figures 4 to 9 It is a schematic diagram of a manufacturing process of a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0063] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings illustrate exemplary implementations of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0064] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0065] It will be understood that the meanings of “on,” “over,” and “over” throughout this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0066] In the embodiments of the present disclosure, the terms "first," "second," "third," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0067] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is smaller than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0068] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0069] Figure 1a and Figure 1b FIG1 is a schematic structural diagram of a semiconductor device 100 according to an exemplary embodiment. Figure 1a As shown, the semiconductor device 100 includes an active layer 101, a gate dielectric layer 102, a gate structure 103, an isolation layer 104 and an insulating layer 105. The isolation layer 104 covers the gate structure 103; the insulating layer 105 covers the sidewalls of the isolation layer 104 and the sidewalls of the gate dielectric layer 102. Figure 1b As shown, the active layer 101 includes a source region 101 b , a channel region 101 a and a drain region 101 c .

[0070] As the characteristic size of semiconductor devices continues to shrink, the characteristic size of the active layer 101 also continues to shrink. Figure 1b As shown, the length of the channel region 101a becomes shorter, causing the electric field between the source region 101b and the drain region 101c to increase sharply. The transistor experiences abnormal hot carrier injection (HCI) failure, for example, the channel region 101a Figure 1b The device 100 is pinched off at point A, causing the performance of the semiconductor device 100 to be severely degraded.

[0071] Normal hot carrier injection failure is: as the current stress time accumulates, the saturation leakage current of the device continues to decrease (i.e. degradation), such as Figure 1c However, shrinking the feature size leads to abnormal hot carrier injection failure in transistors, as shown in the dashed curve. Figure 1c Shown as the solid line curve.

[0072] Still refer to Figure 1cAs shown in the figure, abnormal hot carrier injection failure includes three stages: in stage I, the saturation leakage current of the device decays normally; in stage II, the saturation leakage current of the device begins to rise; in stage III, the saturation leakage current of the device decays sharply.

[0073] Reference Figure 1d As shown, in stage I, hot carriers (e.g., electrons e-) generated in the channel region 101a relatively close to the drain region 101c are injected into the gate dielectric layer 102, causing the saturation leakage current of the device to decay normally; in stage II, abnormal positive charges (e.g., holes h + ) is injected into the gate dielectric layer 102, causing the device's saturation leakage current to begin to increase. In stage III, the accumulation of positive charges in the gate dielectric layer 102 leads to more severe injection of negative charges, causing the device's saturation leakage current to rapidly decrease. This accelerates the degradation of transistor performance and reduces the reliability of the semiconductor device.

[0074] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.

[0075] Figure 2 FIG2 is a schematic structural diagram of a semiconductor device 200 according to an embodiment of the present disclosure. Figure 2 As shown, the semiconductor device 200 includes:

[0076] The active layer 201 includes a channel region 201 a and a source region 201 b and a drain region 201 c located on both sides of the channel region 201 a ;

[0077] A gate dielectric layer 202 is located on the channel region 201a;

[0078] A gate conductive layer 203 is located on the gate dielectric layer 202;

[0079] a first isolation layer 204 , located on the gate dielectric layer 202 and covering the sidewalls of the gate conductive layer 203 ;

[0080] The first insulating layer 205 includes a first portion 205 a and a second portion 205 b , wherein the first portion 205 a covers the sidewalls of the gate dielectric layer 202 and the first isolation layer 204 close to the drain region 201 c , and the second portion 205 b is located on the drain region 201 c ;

[0081] The second isolation layer 206 is located on the second portion 205b and covers the sidewalls of the first portion 205a.

[0082] The active layer 201 is made of materials such as doped single-crystalline silicon, doped polycrystalline silicon, or doped amorphous silicon. In one example, the active layer 201 is p-type doped, and the source region 201b and the drain region 201c are n-type doped. In another example, the active layer 201 is n-type doped, and the source region 201b and the drain region 201c are p-type doped.

[0083] Reference Figure 2 As shown, the gate conductive layer 203 is located on the gate dielectric layer 202, and the width of the gate conductive layer 203 is smaller than the width of the gate dielectric layer 202. The first isolation layer 204 is located on the gate dielectric layer 202, covering the sidewalls of the gate conductive layer 203 and the top of the gate conductive layer 203. Figure 2 As shown, the sum of the width of the first isolation layer 204 covering the sidewall of the gate conductive layer 203 and the width of the gate conductive layer 203 is substantially equal to the width of the gate dielectric layer 202 .

[0084] It should be noted that the “essentially equal” used in the present disclosure includes: the two are completely equal; or there is an error between the two, and the error is very small and can be ignored. No further details will be given hereafter. For example, the sum of the width of the first isolation layer 204 covering the side wall of the gate conductive layer 203 and the width of the gate conductive layer 203 is substantially equal to the width of the gate dielectric layer 202, including: the sum of the width of the first isolation layer 204 covering the side wall of the gate conductive layer 203 and the width of the gate conductive layer 203 is completely equal to the width of the gate dielectric layer 202; or there is an error between the sum of the width of the first isolation layer 204 covering the side wall of the gate conductive layer 203 and the width of the gate conductive layer 203 and the width of the gate dielectric layer 202, and the error is very small and can be ignored.

[0085] In one example, the gate conductive layer 203 is a single layer, for example, a polysilicon layer or a metal layer. In another example, the gate conductive layer 203 is a composite layer, such as Figure 2 As shown, the gate conductive layer 203 includes a stacked first sub-conductive layer 2031, a conductive connection layer 2032, and a second sub-conductive layer 2033. The first sub-conductive layer 2031 is located between the gate dielectric layer 202 and the connection layer 2032. The first sub-conductive layer 2031 is made of a semiconductor material, such as single crystal silicon, polycrystalline silicon, or amorphous silicon. The connection layer 2032 is made of a metal silicide, such as tungsten silicide, titanium silicide, or tantalum silicide. The second sub-conductive layer 2033 is made of a metal material, such as tungsten, titanium, tantalum, platinum, or nickel.

[0086] Reference Figure 2As shown, the first insulating layer 205 is L-shaped and includes a vertical portion covering the sidewalls of the gate dielectric layer 202 and the first isolation layer 204 near the drain region 201c, denoted as the first portion 205a; and a horizontal portion located above the drain region 201c, denoted as the second portion 205b. Here, the first portion 205a and the second portion 205b are merely used to distinguish between different locations of the first insulating layer 205 and are not intended to describe a specific order or precedence.

[0087] Reference Figure 2 As shown, the first portion 205a is located between the gate dielectric layer 202 and the second isolation layer 206 and between the first isolation layer 204 and the second isolation layer 206, and the second portion 205b is located between the drain region 201c and the second isolation layer 206, and the sum of the width of the second isolation layer 206 and the width of the first portion 205a is substantially equal to the width of the second portion 205b.

[0088] In some embodiments, the first isolation layer 204 and the second isolation layer 206 are made of silicon nitride, such as silicon nitride or silicon oxynitride. The first insulating layer 205 is made of silicon oxide, such as silicon oxide.

[0089] In some embodiments, the second isolation layer 206 includes: a charge trap center, and the charge trap center of the second isolation layer 206 is used to capture hot carriers (including electrons and / or holes) generated in the channel region 201a. For example, the second isolation layer 206 is a silicon nitride layer, and the charge trap center of the silicon nitride layer is used to capture hot carriers generated in an area of ​​the channel region 201a relatively close to the drain region 201c.

[0090] In the embodiment of the present disclosure, a composite sidewall structure including a first insulating layer and a second isolation layer is provided on the sidewalls of the gate dielectric layer and the first isolation layer near the drain region. The charge trap centers of the second isolation layer can capture hot carriers generated in the channel region, thereby modulating the accumulated position of the hot carriers, and then modulating the electric field in the channel region, prolonging the time for hot carrier injection into the gate dielectric layer, which is beneficial to delaying the occurrence of abnormal hot carrier injection failure, that is, it is beneficial to slow down the degradation of transistor performance and improve the reliability of semiconductor devices.

[0091] Moreover, by providing a first insulating layer between the gate dielectric layer and the second isolation layer, the first insulating layer can at least prolong the injection of hot carriers captured by the charge trap centers of the second isolation layer into the gate dielectric layer, that is, the composite sidewall structure is more conducive to delaying the occurrence of abnormal hot carrier injection failure, that is, it is more conducive to slowing down the degradation of semiconductor device performance and improving the reliability of semiconductor devices.

[0092] In addition, by providing the first insulating layer between the first isolation layer and the second isolation layer, the distance between the first isolation layer and the second isolation layer can be increased, which is beneficial to reducing the probability of a strong negative charge center appearing at the edge of the gate dielectric layer close to the second isolation layer.

[0093] In some embodiments, the material of the first insulating layer 205 is the same as that of the gate dielectric layer 202. For example, the material of the first insulating layer 205 and the material of the gate dielectric layer 202 include silicon oxide. In a specific example, the material of the first insulating layer 205 and the material of the gate dielectric layer 202 include silicon oxide.

[0094] In some embodiments, reference Figure 2 As shown, the thickness of the second portion 205b between the second isolation layer 206 and the active layer 201 is less than the thickness of the gate dielectric layer 202 between the first isolation layer 204 and the active layer 201. For example, the thickness of the second portion 205b between the second isolation layer 206 and the drain region 201c is less than the thickness of the gate dielectric layer 202 between the first isolation layer 204 and the channel region 201a.

[0095] In some embodiments, reference Figure 2 As shown, the bottom surface of the second portion 205b between the second isolation layer 206 and the drain region 201c is flush with the bottom surface of the gate dielectric layer 202, and the top surface of the second portion 205b between the second isolation layer 206 and the drain region 201c is located between the bottom surface of the gate dielectric layer 202 and the top surface of the gate dielectric layer 202.

[0096] In the embodiment of the present disclosure, by setting the thickness of the second portion between the second isolation layer and the active layer to be smaller than the thickness of the gate dielectric layer between the first isolation layer and the active layer, it can be ensured that there is at least a partial space on the side wall of the gate dielectric layer for setting the second isolation layer, and it can be ensured that at least a charge trap center is set on the side wall of the gate dielectric layer to capture hot carriers generated in the channel region.

[0097] Moreover, by setting the thickness of the second portion between the second isolation layer and the active layer to be smaller than the thickness of the gate dielectric layer between the first isolation layer and the active layer, it is more conducive for the second isolation layer to capture hot carriers generated in the channel region, thereby reducing the number of hot carriers injected into the gate dielectric layer and / or the first isolation layer.

[0098] In some embodiments, the charge transfer barrier of the first insulating layer 205 is greater than the charge transfer barrier of the second isolation layer 206. By setting the charge transfer barrier of the first insulating layer 205 to be greater than the charge transfer barrier of the second isolation layer 206, the first insulating layer 205 can at least block a portion of hot carriers captured by the second isolation layer 206 from being injected into the gate dielectric layer, thereby further delaying the occurrence of abnormal hot carrier injection failure and further improving the reliability of the semiconductor device.

[0099] In some embodiments, the bottom surface of the second isolation layer 206 is located between the bottom surface and the top surface of the gate dielectric layer 202. Here, the bottom surface of the second isolation layer 206 contacts the top surface of the second portion 205b between the second isolation layer 206 and the drain region 201c.

[0100] In the embodiment of the present disclosure, by setting the bottom surface of the second isolation layer between the bottom surface of the gate dielectric layer and the top surface of the gate dielectric layer, it can be ensured that there is at least a partial space on the side wall of the gate dielectric layer for setting the second isolation layer, and it can be ensured that at least a charge trap center is set on the side wall of the gate dielectric layer to capture the hot carriers generated in the channel region.

[0101] In some embodiments, the semiconductor device further comprises:

[0102] The second insulating layer 207 includes a third portion 207 a and a fourth portion 207 b , wherein the third portion 207 a covers the sidewalls of the gate dielectric layer 202 and the first isolation layer 204 close to the source region 201 b , and the fourth portion 207 b is located on the source region 201 b ;

[0103] The third isolation layer 208 is located on the fourth portion 207b and covers the sidewalls of the third portion 207a.

[0104] Reference Figure 2 As shown, the second insulating layer 207 includes a vertical portion covering the sidewalls of the gate dielectric layer 202 and the first isolation layer 204 near the source region 201b, denoted as the third portion 207a; and a horizontal portion located above the source region 201b, denoted as the fourth portion 207b. Here, the third portion 207a and the fourth portion 207b are merely used to distinguish between different locations of the second insulating layer 207 and are not used to describe a specific order or precedence.

[0105] Reference Figure 2 As shown, the third portion 207a is located between the gate dielectric layer 202 and the third isolation layer 208 and between the first isolation layer 204 and the third isolation layer 208, and the fourth portion 207b is located between the source region 201b and the third isolation layer 208, and the sum of the width of the third isolation layer 208 and the width of the third portion 207a is substantially equal to the width of the fourth portion 207b.

[0106] In some embodiments, the third isolation layer 208 is formed of silicon nitride, such as silicon nitride or silicon oxynitride. The second insulating layer 207 is formed of silicon oxide, such as silicon oxide.

[0107] In some embodiments, the material of the third isolation layer 208 is the same as that of the second isolation layer 206, and the material of the second insulating layer 207 is the same as that of the first insulating layer 205. In other embodiments, the material of the third isolation layer 208 is different from that of the second isolation layer 206, and the material of the second insulating layer 207 is different from that of the first insulating layer 205.

[0108] In some embodiments, the first insulating layer 205 and the second insulating layer 207 are symmetrically arranged, for example, the first portion 205a and the third portion 207a are symmetrically arranged; and / or the second portion 205b and the fourth portion 207b are symmetrically arranged. Preferably, the first portion 205a and the third portion 207a are symmetrically arranged, and the second portion 205b and the fourth portion 207b are symmetrically arranged. In this way, the first insulating layer 205 and the second insulating layer 207 can be formed simultaneously in the same process, which helps reduce the manufacturing cost of the semiconductor device.

[0109] In some embodiments, the second isolation layer 206 and the third isolation layer 208 are symmetrically arranged. Thus, the second isolation layer 206 and the third isolation layer 208 can be formed simultaneously in the same process, which is beneficial to reducing the manufacturing cost of the semiconductor device.

[0110] In some embodiments, the thickness of the fourth portion 207b between the third isolation layer 208 and the active layer 201 is less than the thickness of the gate dielectric layer 202 between the first isolation layer 204 and the active layer 201. For example, the thickness of the fourth portion 207b between the third isolation layer 208 and the source region 201b is less than the thickness of the gate dielectric layer 202 between the first isolation layer 204 and the channel region 201a.

[0111] In some embodiments, reference Figure 2 As shown, the bottom surface of the fourth portion 207b between the third isolation layer 208 and the source region 201b is flush with the bottom surface of the gate dielectric layer 202, and the top surface of the fourth portion 207b between the third isolation layer 208 and the source region 201b is located between the bottom surface of the gate dielectric layer 202 and the top surface of the gate dielectric layer 202.

[0112] In some embodiments, reference Figure 2 As shown, the drain region 201c includes: a first sub-drain region 2011c and a second sub-drain region 2012c; wherein, the first sub-drain region 2011c is located between the channel region 201a and the second sub-drain region 2012c; the doping concentration of the first sub-drain region 2011c is less than the doping concentration of the second sub-drain region 2012c.

[0113] Here, the first sub-drain region 2011c with a smaller doping concentration is recorded as a lightly doped drain region, and the second sub-drain region 2012c with a larger doping concentration is recorded as a heavily doped drain region. By setting a lightly doped drain region between the channel region and the heavily doped drain region, the channel electric field can be modulated, and the time for hot carrier injection into the gate dielectric layer can be further extended, which is beneficial to further delay the time when abnormal hot carrier injection failure occurs, and further improve the reliability of the semiconductor device.

[0114] In some embodiments, reference Figure 2 As shown, the source region 201b includes: a first sub-source region 2011b and a second sub-source region 2012b; wherein the first sub-source region 2011b is located between the channel region 201a and the second sub-source region 2012b; the doping concentration of the first sub-source region 2011b is less than the doping concentration of the second sub-source region 2012b.

[0115] In some embodiments, reference Figure 2 As shown, the semiconductor device 200 further includes:

[0116] a third insulating layer 209 covering the second portion 205 b and sidewalls of the second isolation layer 206 ;

[0117] The fourth insulating layer 210 covers the sidewalls of the fourth portion 207 b and the third isolation layer 208 .

[0118] The third insulating layer 209 and the fourth insulating layer 210 are made of silicon oxide, for example, silicon oxide.

[0119] In some embodiments, the first insulating layer 205 , the second insulating layer 207 , the third insulating layer 209 and the fourth insulating layer 210 are made of the same material. In other embodiments, the first insulating layer 205 , the second insulating layer 207 , the third insulating layer 209 and the fourth insulating layer 210 are made of different materials.

[0120] In some embodiments, the third insulating layer 209 and the fourth insulating layer 210 are symmetrically arranged. Thus, the third insulating layer 209 and the fourth insulating layer 210 can be formed simultaneously in the same process, which is beneficial to reducing the manufacturing cost of the semiconductor device.

[0121] It should be understood that when the semiconductor device has a symmetrical structure, the source region and the drain region can be interchanged.

[0122] Figure 3 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 3 As shown, the production method comprises at least the following steps:

[0123] S110: forming an active layer; wherein the active layer includes a channel region and a source region and a drain region located on both sides of the channel region;

[0124] S120: forming a gate dielectric layer on the channel region;

[0125] S130: forming a gate conductive layer on the gate dielectric layer;

[0126] S140: forming a first isolation layer on the gate dielectric layer; wherein the first isolation layer covers the sidewalls of the gate conductive layer;

[0127] S150: After forming the first isolation layer, forming a first insulating layer; wherein the first insulating layer includes a first portion and a second portion, the first portion covers the gate dielectric layer and a sidewall of the first isolation layer close to the drain region, and the second portion is located on the drain region;

[0128] S160: forming a second isolation layer on the second portion; wherein the second isolation layer covers the sidewall of the first portion.

[0129] In the embodiment of the present disclosure, by forming a composite sidewall structure including a first insulating layer and a second isolation layer, the charge trap center of the second isolation layer can capture hot carriers generated in the channel region, thereby modulating the accumulated position of the hot carriers, and then modulating the electric field in the channel region, extending the time for hot carrier injection into the gate dielectric layer, which is beneficial to delaying the time when abnormal hot carrier injection failure occurs, that is, it is beneficial to slow down the degradation of transistor performance and improve the reliability of semiconductor devices.

[0130] Figures 4 to 9 This is a schematic diagram of a manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Figure 3 、 Figures 4 to 9 The present disclosure will be described in further detail.

[0131] First, refer to Figure 4 As shown, step S110 is performed: forming an active layer 301; wherein the active layer 301 includes a channel region 301a and a source region 301b and a drain region 301c located on both sides of the channel region 301a.

[0132] The active layer 301 may be made of materials such as doped single-crystalline silicon, doped polycrystalline silicon, or doped amorphous silicon. In one example, the active layer 301 is p-type doped, while the source region 301b and the drain region 301c are n-type doped. In another example, the active layer 301 is n-type doped, while the source region 301b and the drain region 301c are p-type doped. For example, a shallow trench isolation structure may be formed on a substrate to define the active layer 301.

[0133] It should be noted that the source region 301b includes a first sub-source region 3011b. Figure 4The first sub-source region 3011b is used to define the position of the source region 301b in the active layer 301; the drain region 301c includes the first sub-drain region 3011c, and the first sub-drain region 3011c is used to define the position of the drain region 301c in the active layer 301, which will be explained below and will not be repeated here.

[0134] Then, refer to Figure 4 As shown, step S120 is performed: a gate dielectric layer 302 is formed on the channel region 301 a.

[0135] In one example, a gate dielectric material layer may be deposited on the channel region 301a by a thin film deposition process, and a photolithography and etching process may be performed on the gate dielectric material layer to form a gate dielectric layer. Figure 4 In another example, the active layer 301 can be oxidized to form an oxide material layer covering the active layer 301, and the oxide material layer can be photolithographically and etched to form a gate dielectric layer 302 as shown. Figure 4 The gate dielectric layer 302 is shown.

[0136] Thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or a combination thereof. Etching processes include, but are not limited to, dry etching, wet etching, or a combination thereof. Doping processes include, but are not limited to, ion implantation or ion diffusion.

[0137] The gate dielectric layer 302 is made of silicon oxide, for example, silicon oxide.

[0138] Next, refer to Figure 4 As shown, step S130 and step S140 are performed: forming a gate conductive layer 303 on the gate dielectric layer 302;

[0139] A first isolation layer 304 is formed on the gate dielectric layer 302 , wherein the first isolation layer 304 covers the sidewalls of the gate conductive layer 303 .

[0140] In one example, combining Figure 4 As shown, a gate dielectric material layer, a gate conductive material layer, and a protective material layer covering the active layer 301 are formed in sequence, and the protective material layer and the gate conductive material layer are etched in a direction toward the active layer 301 to form a gate conductive layer 303 and a protective layer, respectively; a first isolation material layer (for example, formed by an atomic layer deposition process) is formed covering the gate dielectric material layer, the sidewalls of the gate conductive layer 303, the sidewalls of the protective layer, and the top of the protective layer, and the first isolation material layer and the gate dielectric material layer are etched in a direction toward the active layer 301 to form Figure 4 The structure shown.

[0141] Here, the protective material layer and the first isolation material layer may be made of the same material. Figure 4 The protective layer and the first isolation layer are not distinguished in the present invention. The protective material layer is used to protect the gate conductive material layer used to form the gate conductive layer during the etching process. In other embodiments, the protective material layer and the first isolation material layer may be made of different materials.

[0142] In another example, combining Figure 4 As shown, a gate dielectric material layer and a gate conductive material layer covering the active layer 301 are formed in sequence, and the gate conductive material layer is etched in a direction toward the active layer 301 to form a gate dielectric material layer as shown in FIG. Figure 4 The gate conductive layer 303 shown in FIG. 1 is formed to cover the gate dielectric material layer, the sidewall of the gate conductive layer 303 and the top of the gate conductive layer 303. The first isolation material layer and the gate dielectric material layer are etched in a direction toward the active layer 301 to form a Figure 4 The sum of the width of the first isolation layer 304 covering the sidewalls of the gate conductive layer 303 and the width of the gate conductive layer 303 is substantially equal to the width of the gate dielectric layer 302 .

[0143] In some embodiments, reference Figure 4 As shown, the gate conductive layer 303 includes: a first sub-conductive layer 3031, a conductive connecting layer 3032 and a second sub-conductive layer 3033 which are stacked;

[0144] The above step S130 includes:

[0145] forming a first sub-conductive material layer on the gate dielectric layer 302;

[0146] forming a connection material layer covering the first sub-conductive material layer;

[0147] forming a second sub-conductive material layer covering the connecting material layer;

[0148] The second sub-conductive material layer, the connecting material layer and the first sub-conductive material layer are etched in the direction toward the active layer 301 ; wherein the remaining second sub-conductive material layer is the second sub-conductive layer 3033 , the remaining connecting material layer is the connecting layer 3032 , and the remaining first sub-conductive material layer is the first sub-conductive layer 3031 .

[0149] It should be understood that, in this example, the gate conductive material layer includes a first sub-conductive material layer, a connecting material layer, and a second sub-conductive material layer that are stacked. The constituent material of the first sub-conductive layer 3031 (first sub-conductive material layer) includes a semiconductor material, for example, single crystal silicon, polycrystalline silicon, or amorphous silicon. The constituent material of the connecting layer 3032 (connecting material layer) includes a metal silicide, for example, tungsten silicide, titanium silicide, or tantalum silicide. The constituent material of the second sub-conductive layer 3033 (second sub-conductive material layer) includes a metal material, for example, tungsten, titanium, tantalum, platinum, or nickel. In other examples, the gate conductive material layer is a single-layer polysilicon material layer or a single-layer metal material layer, and the gate conductive layer 303 is a single-layer film layer.

[0150] The first isolation layer 304 is formed of a material including silicon nitride, for example, silicon nitride or silicon oxynitride.

[0151] Next, combine Figures 4 to 7 As shown, step S150 and step S160 are performed: after forming the first isolation layer 304, a first insulating layer 305 is formed; wherein the first insulating layer 305 includes a first portion 305a and a second portion 305b, the first portion 305a covers the gate dielectric layer 302 and the sidewall of the first isolation layer 304 close to the drain region 301c, and the second portion 305b is located on the drain region 301c;

[0152] A second isolation layer 306 is formed on the second portion 305 b , wherein the second isolation layer 306 covers the sidewalls of the first portion 305 a .

[0153] The first insulating layer 305 is made of silicon oxide, for example, silicon oxide.

[0154] The second isolation layer 306 is formed of a material including silicon nitride, for example, silicon nitride or silicon oxynitride.

[0155] In some embodiments, the second isolation layer 306 includes: a charge trap center, and the charge trap center of the second isolation layer 306 is used to capture hot carriers (including electrons and / or holes) generated in the channel region 301a. For example, the second isolation layer 306 is a silicon nitride layer, and the charge trap center of the silicon nitride layer is used to capture hot carriers generated in an area of ​​the channel region 301a relatively close to the drain region 301c.

[0156] In some embodiments, the above-mentioned manufacturing method further comprises:

[0157] When forming the first insulating layer 305, a second insulating layer 307 is formed; wherein the second insulating layer 307 includes a third portion 307a and a fourth portion 307b, the third portion 307a covers the sidewalls of the gate dielectric layer 302 and the first isolation layer 304 close to the source region 301b, and the fourth portion 307b is located on the source region 301b;

[0158] When the second isolation layer 306 is formed on the second portion 305 b , a third isolation layer 308 is formed on the fourth portion 307 b ; wherein the third isolation layer 308 covers the sidewall of the third portion 307 a .

[0159] The second insulating layer 307 is made of silicon oxide, for example, silicon oxide.

[0160] The third isolation layer 308 is formed of a material including silicon nitride, for example, silicon nitride or silicon oxynitride.

[0161] It can be understood that in this example, the first insulating layer 305 and the second insulating layer 307 can be formed simultaneously in the same process, and the second isolation layer 306 and the third isolation layer 308 can be formed simultaneously in the same process, which is beneficial to reducing the manufacturing cost of the semiconductor device.

[0162] In some embodiments, combined Figures 4 to 7 As shown, when forming the first insulating layer 305, forming the second insulating layer 307 includes:

[0163] After forming the first isolation layer 304 , an insulating material layer 3051 is formed to cover the source region 301 b , the gate dielectric layer 302 , the first isolation layer 304 and the drain region 301 c ;

[0164] Etching the insulating material layer 3051 covering the top of the first isolation layer 304 in a direction toward the active layer 301 to form a first insulating layer 305 and a second insulating layer 307 respectively;

[0165] When the second isolation layer 306 is formed on the second portion 305 b, the third isolation layer 308 is formed on the fourth portion 307 b, including:

[0166] Before etching the insulating material layer 3051 , forming an isolation material layer 3061 covering the insulating material layer 3051 ;

[0167] The isolation material layer 3061 covering the top of the insulating material layer 3051 is etched in a direction toward the active layer 301 to form a second isolation layer 306 and a third isolation layer 308 , respectively.

[0168] For example, an insulating material layer 3051 is formed covering the source region 301b, the gate dielectric layer 302, the first isolation layer 304 and the drain region 301c. Figure 5 As shown; forming an isolation material layer 3061 covering the insulating material layer 3051, as Figure 6 Etching the isolation material layer 3061 and the insulating material layer 3051 in the direction toward the active layer 301 to form Figure 7 The structure shown.

[0169] It can be understood that, in this example, the first insulating layer 305 , the second insulating layer 307 , the second isolation layer 306 and the third isolation layer 308 can be formed by a single etching process, which is beneficial to further reduce the manufacturing cost of the semiconductor device.

[0170] In a specific example, a portion of the isolation material layer 3061 is first removed by dry etching, and then another portion of the isolation material layer 3061 is removed by wet etching to form Figure 7 The second isolation layer 306 and the third isolation layer 308 are shown. Here, performing wet etching after dry etching can reduce defects on the surface of the isolation material layer 3061 after dry etching, which is beneficial to improving the film quality of the second isolation layer 306 and the third isolation layer 308.

[0171] In some embodiments, reference Figure 9 As shown, the above manufacturing method further includes: forming a third insulating layer 309 covering the second portion 305b and the sidewall of the second isolation layer 306;

[0172] When the third insulating layer 309 is formed, a fourth insulating layer 310 is formed to cover the sidewalls of the fourth portion 307 b and the third isolation layer 308 .

[0173] Exemplarily, a third insulating material layer 3091 is formed covering the source region 301b, the second insulating layer 307, the third isolation layer 308, the first isolation layer 304, the first insulating layer 305, the second isolation layer 306 and the drain region 301c, as shown in FIG. Figure 8 Etching the third insulating material layer 3091 in the direction toward the active layer 301 to form Figure 9 The structure shown.

[0174] The third insulating layer 309 and the fourth insulating layer 310 are made of silicon oxide, for example, silicon oxide.

[0175] In some embodiments, the first insulating layer 305 , the second insulating layer 307 , the third insulating layer 309 and the fourth insulating layer 310 are made of the same material. In other embodiments, the first insulating layer 305 , the second insulating layer 307 , the third insulating layer 309 and the fourth insulating layer 310 are made of different materials.

[0176] It can be understood that, in this example, the third insulating layer 309 and the fourth insulating layer 310 can be formed by a single etching process, which is beneficial for further reducing the manufacturing cost of the semiconductor device.

[0177] In some embodiments, the drain region 301c includes: a first sub-drain region 3011c and a second sub-drain region 3012c; the above step S110 includes:

[0178] providing a substrate;

[0179] Performing a first doping step on the substrate to form a first sub-drain region 3011 c;

[0180] A second doping is performed on the substrate to form a second sub-drain region 3012c; the first sub-drain region 3011c is located between the channel region 301a and the second sub-drain region 3012c; and the doping concentration of the first doping is lower than the doping concentration of the second doping.

[0181] Illustratively, the substrate (not shown) includes an active layer 301, i.e., the active layer 301 is part of the substrate. The substrate may be made of a single element semiconductor material (e.g., silicon, germanium), a Group III-V compound semiconductor material, a Group II-VI compound semiconductor material, an organic semiconductor material, or other semiconductor materials known in the art.

[0182] After forming the first isolation layer 304 and before forming the insulating material layer 3051, the substrate on both sides of the channel region 301a is subjected to a first doping operation to form a first sub-drain region 3011c on one side of the channel region 301a and a first sub-source region 3011b on the other side of the channel region 301a. Figure 4 During the first doping process, the first isolation layer 304 can be used as a mask to protect Figure 4 The structure that has been formed.

[0183] After forming the third insulating layer 309 and the fourth insulating layer 310, the second doping is performed on the exposed first sub-drain region 3011c to form a second sub-drain region 3012c on a side of the first sub-drain region 3011c away from the channel region 301a. While the second doping is performed on the exposed first sub-drain region 3011c, the second doping may be performed on the exposed first sub-source region 3011b to form a second sub-source region 3012b on a side of the first sub-source region 3011b away from the channel region 301a. Figure 9 During the second doping process, the first insulating layer 305, the second isolation layer 306 and the third insulating layer 309 as well as the second insulating layer 307, the third isolation layer 308 and the fourth insulating layer 310 can be used as masks to protect the Figure 9 The structure that has been formed.

[0184] In the embodiment of the present disclosure, by forming a first sub-drain region and forming a second sub-drain region on the side of the first sub-drain region away from the channel region, the channel electric field can be modulated, further extending the time for hot carrier injection into the gate dielectric layer, which is beneficial to further delay the time when abnormal hot carrier injection failure occurs and further improve the reliability of the semiconductor device.

[0185] An embodiment of the present disclosure further provides a memory, comprising the semiconductor device 200 in any of the above embodiments.

[0186] In some embodiments, the above-mentioned memory includes but is not limited to dynamic random access memory (DRAM), ferroelectric random access memory (FeRAM), phase change memory (PCM), etc.

[0187] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: An active layer comprising a channel region and a source region and a drain region located on both sides of the channel region; a gate dielectric layer, located on the channel region; a gate conductive layer, located on the gate dielectric layer; a first isolation layer, located on the gate dielectric layer and covering the sidewalls of the gate conductive layer; a first insulating layer, comprising a first portion and a second portion, wherein the first portion covers the gate dielectric layer and a sidewall of the first isolation layer close to the drain region, and the second portion is located on the drain region; a second isolation layer, located on the second portion and covering a sidewall of the first portion; The thickness of the second portion between the second isolation layer and the active layer is smaller than the thickness of the gate dielectric layer between the first isolation layer and the active layer.

2. The semiconductor device according to claim 1, wherein The material of the first insulating layer is the same as that of the gate dielectric layer.

3. The semiconductor device according to claim 1, wherein A bottom surface of the second isolation layer is located between a bottom surface of the gate dielectric layer and a top surface of the gate dielectric layer.

4. The semiconductor device according to claim 1, wherein The semiconductor device further includes: a second insulating layer, comprising a third portion and a fourth portion, the third portion covering the gate dielectric layer and a sidewall of the first isolation layer close to the source region, and the fourth portion being located on the source region; The third isolation layer is located on the fourth portion and covers the sidewall of the third portion.

5. The semiconductor device according to claim 4, wherein A thickness of the fourth portion between the third isolation layer and the active layer is smaller than a thickness of the gate dielectric layer between the first isolation layer and the active layer. The semiconductor device according to claim 1 , wherein: The constituent materials of the first isolation layer and the second isolation layer include: silicon nitride; The first insulating layer is made of silicon oxide.

7. The semiconductor device according to claim 1, wherein The drain region includes: a first sub-drain region and a second sub-drain region; wherein the first sub-drain region is located between the channel region and the second sub-drain region; and the doping concentration of the first sub-drain region is lower than the doping concentration of the second sub-drain region.

8. The semiconductor device according to claim 1, wherein The semiconductor device further includes: A third insulating layer covers the second portion and side walls of the second isolation layer.

9. A method for manufacturing a semiconductor device, characterized in that: include: forming an active layer; wherein the active layer includes a channel region and a source region and a drain region located on both sides of the channel region; forming a gate dielectric layer on the channel region; forming a gate conductive layer on the gate dielectric layer; forming a first isolation layer on the gate dielectric layer; wherein the first isolation layer covers the sidewalls of the gate conductive layer; After forming the first isolation layer, forming a first insulating layer; wherein the first insulating layer includes a first portion and a second portion, the first portion covers the gate dielectric layer and a sidewall of the first isolation layer close to the drain region, and the second portion is located on the drain region; forming a second isolation layer on the second portion; wherein the second isolation layer covers the sidewalls of the first portion; The thickness of the second portion between the second isolation layer and the active layer is smaller than the thickness of the gate dielectric layer between the first isolation layer and the active layer.

10. The manufacturing method according to claim 9, characterized in that: The production method further comprises: When forming the first insulating layer, forming a second insulating layer; wherein the second insulating layer includes a third portion and a fourth portion, the third portion covers the sidewalls of the gate dielectric layer and the first isolation layer close to the source region, and the fourth portion is located on the source region; When the second isolation layer is formed on the second portion, a third isolation layer is formed on the fourth portion; wherein the third isolation layer covers the sidewall of the third portion.

11. The manufacturing method according to claim 10, characterized in that: The step of forming a second insulating layer when forming the first insulating layer comprises: After forming the first isolation layer, forming an insulating material layer covering the source region, the gate dielectric layer, the first isolation layer and the drain region; The insulating material layer covering the top of the first isolation layer is etched in a direction toward the active layer to form the first insulating layer and the second insulating layer respectively.

12. The manufacturing method according to claim 11, characterized in that: When forming the second isolation layer on the second portion, forming the third isolation layer on the fourth portion comprises: Before etching the insulating material layer, forming an isolation material layer covering the insulating material layer; The isolation material layer covering the top of the insulating material layer is etched in a direction toward the active layer to form the second isolation layer and the third isolation layer respectively.

13. The manufacturing method according to claim 9, characterized in that: The gate conductive layer comprises: a first sub-conductive layer, a conductive connecting layer and a second sub-conductive layer which are stacked; The forming of a gate conductive layer on the gate dielectric layer comprises: forming a first sub-conductive material layer on the gate dielectric layer; forming a connection material layer covering the first sub-conductive material layer; forming a second sub-conductive material layer covering the connecting material layer; The second sub-conductive material layer, the connecting material layer and the first sub-conductive material layer are etched in a direction toward the active layer; wherein the remaining second sub-conductive material layer is the second sub-conductive layer, the remaining connecting material layer is the connecting layer, and the remaining first sub-conductive material layer is the first sub-conductive layer.

14. The manufacturing method according to claim 9, characterized in that: The constituent materials of the first isolation layer and the second isolation layer include: silicon nitride; The first insulating layer is made of silicon oxide.

15. The manufacturing method according to claim 9, characterized in that: The drain region includes: a first sub-drain region and a second sub-drain region; The forming of the active layer comprises: providing a substrate; performing a first doping operation on the substrate to form the first sub-drain region; A second doping is performed on the substrate to form the second sub-drain region; the first sub-drain region is located between the channel region and the second sub-drain region; and a doping concentration of the first doping is less than a doping concentration of the second doping.

16. The manufacturing method according to claim 9, characterized in that: The production method further comprises: A third insulating layer is formed covering the second portion and the sidewall of the second isolation layer.

17. A memory, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 8.

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