Junction field effect device and method of manufacturing the same

Abstract

The application provides a junction field effect device and a manufacturing method thereof, in the junction field effect device, a gate region structure in a channel region comprises a first layer gate region and a second layer polysilicon gate region, that is, the gate region structure is a double-layer structure, a contact area between the first layer gate region and the gate region polysilicon is doped to form the second layer polysilicon gate region, compared with direct contact between the first layer gate region and the gate region polysilicon, local parts of the gate region polysilicon and the first layer gate region are doped, the conductive performance of the gate contact area is improved, the potential area resistance of the gate contact area can be effectively reduced, the leakage current of the device is reduced, the threshold voltage of the device is also reduced, and the consistency of key parameters such as the leakage current and the threshold voltage is effectively improved; based on the standard design of the structure, a full-poly self-alignment process can be used in the corresponding process, the process is simple, and the process is highly compatible with a polysilicon integrated circuit process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a junction field effect device and a manufacturing method thereof. BACKGROUND

[0002] The high-precision junction field effect transistor (JFET) input operational amplifier manufactured based on a modern BiFET bipolar process has the characteristics of low noise, high input impedance, small temperature drift and input bias current, and is used for signal amplification in an electronic system. In the production of the high-precision JFET input operational amplifier, the most important thing in the modern BiFET bipolar process is the development of a junction field effect device.

[0003] The JFET has a series of advantages such as high input impedance and low bias current, and is widely used. However, with the continuous development of bipolar process integration technology and the continuous improvement of integration density, the JFET is increasingly challenged in terms of input impedance, leakage current, threshold voltage and voltage resistance. The leakage current is too high, and the consistency of the leakage current and the threshold voltage and other key parameters is getting worse and worse, and the JFET is less and less suitable for miniaturization, high-density integration and fine electronic systems.

[0004] Therefore, how to reduce the leakage current of the junction field effect device and improve the consistency of its key parameters is a technical problem to be solved at present. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a technical solution of a junction field effect device for solving the above-mentioned technical problems.

[0006] In order to achieve the above-mentioned purposes and other related purposes, the technical solution provided by the present application is as follows.

[0007] A junction field effect device comprises:

[0008] a substrate;

[0009] an epitaxial layer having a first type of doping and arranged on the substrate;

[0010] a channel region having a second type of doping and arranged in the epitaxial layer;

[0011] a first layer gate region having a first type of doping and arranged in the channel region;

[0012] a second layer polysilicon gate region having a first type of doping and arranged in the first layer gate region and located on top of the first layer gate region;

[0013] a polysilicon heavily doped source region having a second type of doping, disposed in the channel region, on one side of the first layer gate region;

[0014] a polysilicon heavily doped drain region having a second type of doping, disposed in the channel region, on another side of the first layer gate region;

[0015] a field oxide layer disposed on the epitaxial layer, exposing the second layer polysilicon gate region, the polysilicon heavily doped source region, and the polysilicon heavily doped drain region;

[0016] a gate polysilicon disposed on the epitaxial layer, contacting the second layer polysilicon gate region through the field oxide layer;

[0017] a source polysilicon disposed on the epitaxial layer, contacting the polysilicon heavily doped source region through the field oxide layer;

[0018] a drain polysilicon disposed on the epitaxial layer, contacting the polysilicon heavily doped drain region through the field oxide layer;

[0019] a dielectric layer disposed on the field oxide layer, the gate polysilicon, the source polysilicon, and the drain polysilicon, exposing the gate polysilicon, the source polysilicon, and the drain polysilicon;

[0020] a gate metal disposed on the dielectric layer, contacting the gate polysilicon through the dielectric layer;

[0021] a source metal disposed on the dielectric layer, contacting the source polysilicon through the dielectric layer;

[0022] a drain metal disposed on the dielectric layer, contacting the drain polysilicon through the dielectric layer.

[0023] Optionally, the junction field effect device further comprises:

[0024] a buried layer disposed in the substrate and at an edge of a top portion of the substrate;

[0025] an isolation penetration region disposed in the epitaxial layer and surrounding the channel region, at an edge of the epitaxial layer and contacting the buried layer.

[0026] Optionally, the substrate has a P-type doping, the buried layer has an N-type doping, and the isolation penetration region has an N-type doping.

[0027] Optionally, the first type of doping and the second type of doping are opposite types of doping, if the first type of doping is a P-type doping, the second type of doping is an N-type doping, and if the first type of doping is an N-type doping, the second type of doping is a P-type doping.

[0028] Optionally, the material of the substrate or the epitaxial layer comprises at least one of silicon, silicon carbide, gallium arsenide, indium phosphide and silicon germanium.

[0029] A method for manufacturing a junction field effect device, comprising:

[0030] providing a substrate;

[0031] forming a buried layer in the substrate, the buried layer being located at the edge of the top of the substrate;

[0032] forming an epitaxial layer on the substrate, the epitaxial layer having a first type of doping;

[0033] forming an isolation penetration region in the epitaxial layer, the isolation penetration region being located at the edge of the epitaxial layer and in contact with the buried layer;

[0034] forming a channel region in the epitaxial layer, the channel region having a second type of doping;

[0035] forming a field oxide layer on the epitaxial layer, the field oxide layer having a gate region window, a source region window and a drain region window pre-provided thereon;

[0036] forming a first layer of gate region in the channel region through the gate region window, the first layer of gate region having the first type of doping;

[0037] forming a gate region polysilicon at the gate region window, a source region polysilicon at the source region window and a drain region polysilicon at the drain region window, the gate region polysilicon being in contact with the first layer of gate region, the source region polysilicon and the drain region polysilicon being in contact with the channel region respectively;

[0038] forming a second layer of polysilicon gate region in the first layer of gate region through the gate region polysilicon, the second layer of polysilicon gate region having the first type of doping and being located at the top of the first layer of gate region;

[0039] forming a polysilicon heavily doped source region in the channel region through the source region polysilicon and a polysilicon heavily doped drain region in the channel region through the drain region polysilicon, the polysilicon heavily doped source region having the second type of doping and being located at one side of the first layer of gate region, the polysilicon heavily doped drain region having the second type of doping and being located at the other side of the first layer of gate region.

[0040] Optionally, after forming the polysilicon heavily doped source region and the polysilicon heavily doped drain region, the method for manufacturing a junction field effect device further comprises:

[0041] forming a first dielectric layer on the field oxide layer, the gate region polysilicon, the source region polysilicon and the drain region polysilicon and etching, to expose the gate region polysilicon, the source region polysilicon and the drain region polysilicon;

[0042] forming a first metal layer on the residual first dielectric layer, the gate region polysilicon, the source region polysilicon and the drain region polysilicon and etching, to obtain independent gate metal, source metal and drain metal, the gate metal contacts the gate region polysilicon through the residual first dielectric layer, the source metal contacts the source region polysilicon through the residual first dielectric layer, and the drain metal contacts the drain region polysilicon through the residual first dielectric layer.

[0043] Optionally, after forming the gate metal, the source metal and the drain metal, the manufacturing method of the junction type field effect device further comprises:

[0044] forming a second dielectric layer on the gate metal, the source metal and the drain metal and etching, to expose the gate metal, the source metal and the drain metal;

[0045] forming a second metal layer on the residual second dielectric layer, the gate metal, the source metal and the drain metal and etching, to obtain independent gate additional metal, source additional metal and drain additional metal, the gate additional metal contacts the gate metal through the residual second dielectric layer, the source additional metal contacts the source metal through the residual second dielectric layer, and the drain additional metal contacts the drain metal through the residual second dielectric layer;

[0046] forming a passivation layer covering the gate additional metal, the source additional metal and the drain additional metal;

[0047] etching the passivation layer to expose the gate additional metal, the source additional metal and the drain additional metal.

[0048] Optionally, the second metal layer comprises an alloy layer.

[0049] Optionally, after etching the passivation layer to expose the gate additional metal, the source additional metal and the drain additional metal, the manufacturing method of the junction type field effect device further comprises:

[0050] performing low-temperature annealing treatment;

[0051] sequentially performing testing, cutting, mounting, sintering, packaging and post-packaging testing treatment.

[0052] As described above, the junction type field effect device and the manufacturing method thereof have the following beneficial effects:

[0053] The gate region structure in the channel region includes a first layer of gate region and a second layer of polysilicon gate region, i.e. the gate region structure is a double-layer structure. The contact area between the first layer of gate region and the gate region polysilicon is doped to form the second layer of polysilicon gate region. Compared with the direct contact between the first layer of gate region and the gate region polysilicon, the local gate region polysilicon and the first layer of gate region are doped, the conductivity of the gate contact area is improved, the potential area resistance of the gate contact area is effectively reduced, the leakage current of the device is reduced, the threshold voltage of the device is also reduced, and the consistency of the key parameters such as leakage current and threshold voltage is effectively improved. Based on the standard design of the structure, the corresponding process can adopt a full-poly self-alignment process, the process is simple, and is highly compatible with the polysilicon integrated circuit process. BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1 A structure schematic diagram of a junction field effect device in the application is shown.

[0055] Figure 2 A step schematic diagram of a manufacturing method of a junction field effect device in the application is shown.

[0056] Figures 3-26 A process flow chart of a manufacturing method of a junction field effect device in an optional embodiment of the application is shown. DETAILED DESCRIPTION

[0057] The embodiments of the present application will be described herein below with reference to specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in the specification. The present application can also be implemented or applied in different specific embodiments, and various modifications or changes can be made to the details in the specification without departing from the spirit of the present application.

[0058] Please refer to Figures 1-26 It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concept of the present application, and the diagrams only show the components related to the present application, not the number, shape and size of the components in actual implementation. The shape, number and proportion of each component in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complex. The structure, proportion, size, etc. shown in the diagrams attached to the specification are only used to understand and read the content disclosed in the specification by those skilled in the art, and do not limit the conditions under which the present application can be implemented, so they do not have technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effect and purpose that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application.

[0059] As described in the foregoing background, the inventors have found that, with the continuous development of bipolar process integration technology and the continuous improvement of integration density, the requirements for junction field effect transistors in input impedance, leakage current, threshold voltage, voltage resistance and other aspects are increasingly high, the leakage current is too high, and the consistency of the leakage current and threshold voltage and other key parameters is increasingly poor, and the junction field effect transistors are increasingly unsuitable for miniaturization, high-density integration and fine electronic systems.

[0060] Based on this, the present application provides a technical solution of a junction field effect device: doping the contact area of the first layer gate region and the gate region polysilicon to form a second layer polysilicon gate region, obtaining a double-layer structure gate region structure, to improve the conductivity of the gate contact area, reduce the potential area resistance of the gate contact area, reduce the leakage current and threshold voltage of the device, and improve the consistency of the leakage current and threshold voltage and other key parameters.

[0061] As shown in Figure 1 , the present application provides a junction field effect device, which comprises:

[0062] a substrate 100;

[0063] an epitaxial layer 102 having a first type of doping, disposed on the substrate 100;

[0064] a channel region 106 having a second type of doping, disposed in the epitaxial layer 102;

[0065] a first layer gate region 108 having a first type of doping, disposed in the channel region 106;

[0066] a second layer polysilicon gate region 112 having a first type of doping, disposed in the first layer gate region 108 and located on top of the first layer gate region 108;

[0067] a polysilicon heavily doped source region 113 having a second type of doping, disposed in the channel region 106 and located on one side of the first layer gate region 108;

[0068] a polysilicon heavily doped drain region 114 having a second type of doping, disposed in the channel region 106 and located on the other side of the first layer gate region 108;

[0069] a field oxide layer 107 disposed on the epitaxial layer 102, and exposing the second layer polysilicon gate region 112, the polysilicon heavily doped source region 113 and the polysilicon heavily doped drain region 114;

[0070] a gate region polysilicon 109 disposed on the epitaxial layer 102 and in contact with the second layer polysilicon gate region 112 through the field oxide layer 107;

[0071] The source region polysilicon 110 is disposed on the epitaxial layer 102 and contacts the polysilicon heavily doped source region 113 through the field oxide layer 107.

[0072] The drain region polysilicon 111 is disposed on the epitaxial layer 102 and contacts the polysilicon heavily doped drain region 114 through the field oxide layer 107.

[0073] The dielectric layer 115 is disposed on the field oxide layer 107, the gate region polysilicon 109, the source region polysilicon 110 and the drain region polysilicon 111 and exposes the gate region polysilicon 109, the source region polysilicon 110 and the drain region polysilicon 111.

[0074] The gate metal 116 is disposed on the dielectric layer 115 and contacts the gate region polysilicon 109 through the dielectric layer 115.

[0075] The source metal 117 is disposed on the dielectric layer 115 and contacts the source region polysilicon 110 through the dielectric layer 115.

[0076] The drain metal 118 is disposed on the dielectric layer 115 and contacts the drain region polysilicon 111 through the dielectric layer 115.

[0077] The first type of doping and the second type of doping are opposite types of doping, if the first type of doping is P-type doping, the second type of doping is N-type doping; if the first type of doping is N-type doping, the second type of doping is P-type doping.

[0078] In detail, as shown in Figure 1 The junction field effect device further comprises:

[0079] The buried layer 101 is disposed in the substrate 100 and located at the edge of the top of the substrate 100.

[0080] The isolation penetration region 103 is disposed in the epitaxial layer 102 and surrounds the channel region 106, is located at the edge of the epitaxial layer 102 and contacts the buried layer 101.

[0081] More specifically, the substrate 100 has P-type doping, the buried layer 101 has N-type doping, and the isolation penetration region 103 has N-type doping. It can be understood that the substrate 100 can also have N-type doping, and the corresponding buried layer 101 and isolation penetration region 103 have P-type doping respectively. Compared with the N-type doping substrate, the junction field effect device made of the P-type doping substrate has better electrical performance and higher economic benefit, and the substrate 100 is generally selected to have P-type doping.

[0082] In detail, the material of the substrate 100 or the epitaxial layer 102 at least includes one of bulk silicon, silicon carbide, gallium arsenide, indium phosphide and germanium silicon.

[0083] Meanwhile, as shown in Figure 2As shown, the application also provides a manufacturing method of a junction field effect device, for manufacturing the above-mentioned junction field effect device, comprising the steps of:

[0084] S1, providing a substrate;

[0085] S2, forming a buried layer in the substrate, the buried layer being located at the edge of the top of the substrate;

[0086] S3, forming an epitaxial layer on the substrate, the epitaxial layer having a first type of doping;

[0087] S4, forming an isolation penetration region in the epitaxial layer, the isolation penetration region being located at the edge of the epitaxial layer and in contact with the buried layer, the isolation penetration region being arranged around the channel region;

[0088] S5, forming a channel region in the epitaxial layer, the channel region having a second type of doping;

[0089] S6, forming a field oxide layer on the epitaxial layer, the field oxide layer being provided with a gate window, a source window and a drain window;

[0090] S7, forming a first layer of gate region in the channel region through the gate window, the first layer of gate region having the first type of doping;

[0091] S8, forming a gate polysilicon at the gate window, a source polysilicon at the source window and a drain polysilicon at the drain window, the gate polysilicon being in contact with the first layer of gate region, and the source polysilicon and the drain polysilicon being in contact with the channel region respectively;

[0092] S9, forming a second layer of polysilicon gate region in the first layer of gate region through the gate polysilicon, the second layer of polysilicon gate region having the first type of doping and being located at the top of the first layer of gate region;

[0093] S10, forming a polysilicon heavily doped source region in the channel region through the source polysilicon, and forming a polysilicon heavily doped drain region in the channel region through the drain polysilicon, the polysilicon heavily doped source region having the second type of doping and being located at one side of the first layer of gate region, and the polysilicon heavily doped drain region having the second type of doping and being located at the other side of the first layer of gate region.

[0094] In detail, as shown in the optional embodiment of the application, Figure 3 in step S1, a P<111> single crystal wafer with less defects is selected as the substrate 100, i.e. the substrate 100 has P-type doping, the wafer thickness is about 500-700 μm, the resistivity is 5-30 Ω·cm, and the wafer is ready for use after marking cleaning and drying.

[0095] In detail, as shown in the optional embodiment of the application, Figure 3 after step S1 and before step S2, the manufacturing method of the junction field effect device further comprises the steps of:

[0096] Stp1, using dry and wet oxidation process, grow a layer with a thickness of The thick oxide layer 001 has a growth temperature of 1100-1150°C and a growth time of 100-120 minutes;

[0097] Stp2, perform the first photolithography, after photolithography and etching, use pure dry oxidation process to grow a layer with a thickness of The thin oxide layer 002 has a growth temperature of 1000-1020°C and a growth time of 30-40 minutes.

[0098] In detail, such as Figures 4-5 As shown, in an optional embodiment of the present invention, in step S2, a buried layer 101 with N-type doping is formed in the substrate 100, ion implantation is first performed, annealing is performed, and redistribution is performed, and finally the thick oxide layer 001 and the thin oxide layer 002 are removed to form a buried layer 101 around the top periphery of the substrate 100. The ion implantation conditions are: the dose is 4e15~8e15cm -2 , energy is 60~100KeV. Annealing redistribution conditions are: pure N 2 Atmosphere annealing, temperature is 1100-1150°C, and time is 100min-120min.

[0099] In detail, such as Figure 6 As shown, in an optional embodiment of the present invention, in step S3, an epitaxial growth process is adopted to form an epitaxial layer 102 with P-type doping on the substrate 100, the growth temperature is 1100°C to 1150°C, the thickness of the formed epitaxial layer 102 is 5 to 30 μm, and the resistivity of the formed epitaxial layer 102 is 4 to 40 Ω·cm.

[0100] In detail, such as Figure 7 As shown, in an optional embodiment of the present invention, after step S3 and before step S4, the method for manufacturing a junction field effect device further includes the following steps:

[0101] Stp3, using pure dry oxidation process, grow a layer with a thickness of The thin oxide layer 104 has a growth temperature of 1000-1020° C. and a growth time of 30 min-40 min.

[0102] In detail, such as Figures 8-9As shown, in an optional embodiment of the present invention, in step S4, a second photolithography is performed, and after the photolithography, ion implantation is performed on a circle around the top periphery of the epitaxial layer 102 to form an isolation penetration region 103 with N-type doping in the epitaxial layer 102. The isolation penetration region 103 is located at the edge of the epitaxial layer 102 and contacts the buried layer 101 in the substrate 100. The ion implantation conditions are: a dose of 1e15 to 8e15 cm -2 , energy is 60~100KeV.

[0103] In detail, such as Figures 10-11 As shown, in an optional embodiment of the present invention, in step S5, a third photolithography is performed, and after the photolithography, ion implantation is performed in the middle area of ​​the epitaxial layer 102, followed by annealing and redistribution, to form an N-type doped channel region 106 in the middle of the epitaxial layer 102. The ion implantation conditions are: a dose of 1e13 to 5e13 cm -2 The energy is 60-100 KeV. The annealing redistribution conditions are: oxygen-free annealing, temperature 1100-1150° C., and time 100-200 minutes.

[0104] In detail, such as Figures 12-13 As shown, in an optional embodiment of the present invention, after step S5 and before step S6, the method for manufacturing a junction field effect device further includes the steps of:

[0105] Stp4, such as Figure 12 As shown, a low pressure chemical vapor deposition process (LPCVD) is used to form a nitride layer 105 on the thin oxide layer 104. The thickness of the nitride layer 105 is

[0106] Stp5, such as Figure 13 As shown, the fourth photolithography is performed. After the nitride layer 105 is etched, the Figure 13 The window shown is used for N-type impurity ion implantation, with an ion implantation dose of 1e11-5e11cm -2 , the energy is 60-100 KeV, which reinforces the doping in the channel region 106 to prevent the local area from being inverted due to the transition doping during subsequent doping.

[0107] In detail, such as Figure 14 As shown, in an optional embodiment of the present invention, in step S6, the residual nitride layer 105 is used as a mask, and a dry-wet oxidation process is adopted to grow a field oxide layer 107 on the epitaxial layer 102. The thickness of the field oxide layer 107 is The growth temperature is 1000-1050℃, the growth time is 200-400min, and finally annealing and redistribution are performed. The annealing and redistribution conditions are: pure N 2Ambient annealing, temperature 1100-1150℃, time 100-120min.

[0108] More specifically, as shown in FIG. 5, the region shown by the residual nitride layer 105, which neither forms the field oxide layer 107 nor the region of the gate window, the source window and the drain window, is pre-set as the gate region window, the source region window and the drain region window. Figure 14

[0109] More specifically, as shown in FIG. 5, the region shown by the residual nitride layer 105, which neither forms the field oxide layer 107 nor the region of the gate window, the source window and the drain window, is pre-set as the gate region window, the source region window and the drain region window. Figures 15-16 -2 , energy 60-100KeV.

[0110] More specifically, as shown in FIG. 5, the region shown by the residual nitride layer 105, which neither forms the field oxide layer 107 nor the region of the gate window, the source window and the drain window, is pre-set as the gate region window, the source region window and the drain region window. Figures 17-18

[0111] S81, the residual thin oxide layer 104 is first peeled off to expose the local region of the channel region 106 corresponding to the gate window, the source window and the drain window;

[0112] S82, a polysilicon film layer is deposited to cover the field oxide layer 107 and the region of the channel region 106 corresponding to the gate window, the source window and the drain window, and the thickness of the polysilicon film layer is 100-200nm.

[0113] S83, the sixth photolithography is performed, and after the photolithography, the excess polysilicon film layer is etched to form the gate polysilicon 109 at the gate window, the source polysilicon 110 at the source window and the drain polysilicon 111 at the drain window, the gate polysilicon 109 is in contact with the first layer gate region 108, and the source polysilicon 110 and the drain polysilicon 111 are in contact with the channel region 106.

[0114] More specifically, as shown in FIG. 5, the region shown by the residual nitride layer 105, which neither forms the field oxide layer 107 nor the region of the gate window, the source window and the drain window, is pre-set as the gate region window, the source region window and the drain region window. Figures 19-20 -2 , energy 20-40KeV.

[0115] More specifically, as shown in FIG. 5, the region shown by the residual nitride layer 105, which neither forms the field oxide layer 107 nor the region of the gate window, the source window and the drain window, is pre-set as the gate region window, the source region window and the drain region window. Figures 21-22 ​​​​As shown, in an optional embodiment of the present invention, in step S10, an eighth photolithography is performed, and after the photolithography, an ion implantation process is first performed and then an annealing and redistribution process is performed. A polysilicon heavily doped source region 113 is formed in the channel region 106 through the source region polysilicon 110, and a polysilicon heavily doped drain region 114 is formed in the channel region 106 through the drain region polysilicon 111. The polysilicon heavily doped source region 113 has an N-type doping and is located on one side of the first layer gate region 108, and the polysilicon heavily doped drain region 114 has an N-type doping and is located on the other side of the first layer gate region 108. The ion implantation conditions are: a dose of 1e15 to 5e15 cm -2 The energy is 20-40 KeV. The annealing and redistribution process adopts RTA annealing, and the RTA redistribution conditions are: oxygen-free environment, temperature 800-900°C, and time 30SEC-60SEC.

[0116] In detail, such as Figure 2 As shown, after forming the polysilicon heavily doped source region and the polysilicon heavily doped drain region, the method for manufacturing the junction field effect device further includes the steps of:

[0117] S11, forming a first dielectric layer on the field oxide layer, the gate polysilicon, the source polysilicon, and the drain polysilicon, and etching the first dielectric layer to expose the gate polysilicon, the source polysilicon, and the drain polysilicon;

[0118] S12. Form a first metal layer on the remaining first dielectric layer, gate polysilicon, source polysilicon and drain polysilicon and etch them to obtain independent gate metal, source metal and drain metal, the gate metal passes through the remaining first dielectric layer to contact the gate polysilicon, the source metal passes through the remaining first dielectric layer to contact the source polysilicon, and the drain metal passes through the remaining first dielectric layer to contact the drain polysilicon.

[0119] In more detail, Figures 23-24 As shown, in an optional embodiment of the present invention, in step S11, a first dielectric layer (such as an oxide layer) is deposited using a low pressure chemical vapor deposition process, and the thickness of the first dielectric layer is Eight more photolithography steps are performed, and after the photolithography, the first dielectric layer is etched to form three contact holes in the remaining first dielectric layer (denoted as dielectric layer 105). The three contact holes are respectively located within the gate polysilicon 109, within the source polysilicon 110, and within the drain polysilicon 111. The three contact holes then expose the gate polysilicon 109, the source polysilicon 110, and the drain polysilicon 111, respectively.

[0120] In more detail, Figures 23-24As shown in the optional embodiment of the present application, in step S12, first, a first layer of metal, such as metal AL, is formed by a deposition process, and then the ninth photoetching is performed. After the photoetching, the first layer of metal is etched to form the gate metal 116, the source metal 117 and the drain metal 118. The gate metal 116 contacts the gate poly 109 through the dielectric layer 15. The source metal 117 contacts the source poly 110 through the dielectric layer 105. The drain metal 118 contacts the drain poly 111 through the dielectric layer 105.

[0121] It should be noted that the gate, the source and the drain further include a second layer of metal or a third layer of metal in addition to the first layer of metal, so as to strengthen the structure of each electrode and facilitate the subsequent leading of the press welding points (pads).

[0122] Therefore, as shown in the optional embodiment of the present application, after the gate metal, the source metal and the drain metal are formed, the manufacturing method of the junction type field effect device further includes: Figure 2

[0123] S13, forming a second dielectric layer on the gate metal, the source metal and the drain metal and etching the second dielectric layer to expose the gate metal, the source metal and the drain metal;

[0124] S14, forming a second layer of metal on the residual second dielectric layer, the gate metal, the source metal and the drain metal and etching the second layer of metal to obtain mutually independent gate additional metal, source additional metal and drain additional metal. The gate additional metal contacts the gate metal through the residual second dielectric layer. The source additional metal contacts the source metal through the residual second dielectric layer. The drain additional metal contacts the drain metal through the residual second dielectric layer.

[0125] S15, forming a passivation layer covering the gate additional metal, the source additional metal and the drain additional metal;

[0126] S16, etching the passivation layer to expose the gate additional metal, the source additional metal and the drain additional metal.

[0127] In the steps S13-S14, the steps S11-S12 are similar, and thus will not be described herein again. The second layer of metal can include a metal layer or an alloy layer. In step S15, the passivation layer is grown, such as a growth process condition of a furnace temperature of 550°C and a time of 10-30 minutes. In step S16, the passivation layer is etched after the photoetching to form the press welding points.

[0128] Optionally, after the passivation layer is etched to expose the gate additional metal, the source additional metal and the drain additional metal, the manufacturing method of the junction type field effect device further includes:

[0129] ​S17, low temperature annealing treatment is performed on the whole device, such as temperature of 500-510℃, constant temperature for 30min, strengthening the structural stability of the device;

[0130] S18, sequentially performing testing, cutting, mounting, sintering, packaging and post-packaging testing.

[0131] Among them, steps S17-S18 are conventional technical means, which can refer to the prior art, and will not be repeated here.

[0132] It should be noted that the above-mentioned optional embodiment introduces the manufacturing process of N-type junction field effect device, and in other optional examples, P-type junction field effect device can also be manufactured according to the above-mentioned method process, only the doping type of part of the structure layer needs to be replaced, which will not be repeated here.

[0133] Finally, the junction field effect device as shown in Figure 25 or Figure 1 is obtained. In the junction field effect device of the present application, the gate region structure in the channel region includes the first layer gate region and the second layer polysilicon gate region, that is, the gate region structure is a double-layer structure. The contact area between the first layer gate region and the gate region polysilicon is doped to form the second layer polysilicon gate region. Compared with the direct contact between the first layer gate region and the gate region polysilicon, the local gate region polysilicon and the first layer gate region are doped, which improves the conductivity of the gate contact area, effectively reduces the potential area resistance of the gate contact area, reduces the leakage current of the device, and also reduces the threshold voltage of the device, effectively improving the consistency of the key parameters such as leakage current and threshold voltage. Based on the specification design of the structure, the corresponding process can adopt full-poly self-alignment process, which is simple and highly compatible with polysilicon integrated circuit process.

[0134] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A junction field effect device, characterized by, The junction field effect device comprises: a substrate; an epitaxial layer having a first type of doping disposed on the substrate; a channel region having a second type of doping disposed in the epitaxial layer; a first layer gate region having the first type of doping disposed in the channel region; a second layer polysilicon gate region having the first type of doping disposed in the first layer gate region and on top of the first layer gate region; a polysilicon heavily doped source region having the second type of doping disposed in the channel region and on one side of the first layer gate region; a polysilicon heavily doped drain region having the second type of doping disposed in the channel region and on another side of the first layer gate region; a field oxide layer disposed on the epitaxial layer and exposing the second layer polysilicon gate region, the polysilicon heavily doped source region and the polysilicon heavily doped drain region; a gate polysilicon disposed on the epitaxial layer and in contact with the second layer polysilicon gate region through the field oxide layer; a source polysilicon disposed on the epitaxial layer and in contact with the polysilicon heavily doped source region through the field oxide layer; a drain polysilicon disposed on the epitaxial layer and in contact with the polysilicon heavily doped drain region through the field oxide layer; a dielectric layer disposed on the field oxide layer, the gate polysilicon, the source polysilicon and the drain polysilicon and exposing the gate polysilicon, the source polysilicon and the drain polysilicon; a gate metal disposed on the dielectric layer and in contact with the gate polysilicon through the dielectric layer; a source metal disposed on the dielectric layer and in contact with the source polysilicon through the dielectric layer; a drain metal disposed on the dielectric layer and in contact with the drain polysilicon through the dielectric layer.

2. The junction field-effect device according to claim 1, wherein The junction field effect device further comprises: a buried layer disposed in the substrate and on an edge of the top of the substrate; an isolation penetration region disposed in the epitaxial layer and surrounding the channel region and on an edge of the epitaxial layer and in contact with the buried layer.

3. The junction field-effect device of claim 2, wherein The substrate has a P-type doping, the buried layer has an N-type doping and the isolation penetration region has an N-type doping.

4. The junction field-effect device according to claim 1 or 3, characterized in that The first type of doping and the second type of doping are opposite types of doping, if the first type of doping is a P-type doping, the second type of doping is an N-type doping, and if the first type of doping is an N-type doping, the second type of doping is a P-type doping.

5. The junction field-effect device according to any one of claims 1 to 3, wherein The material of the substrate or the epitaxial layer comprises at least one of silicon, silicon carbide, gallium arsenide, indium phosphide and silicon germanium.

6. A method of manufacturing a junction field effect device, characterized by, The method for manufacturing a junction field effect device comprises: providing a substrate; forming a buried layer in the substrate, the buried layer being on an edge of the top of the substrate; forming an epitaxial layer on the substrate, the epitaxial layer having a first type of doping; forming an isolation penetration region in the epitaxial layer, the isolation penetration region being on an edge of the epitaxial layer and in contact with the buried layer; forming a channel region in the epitaxial layer, the channel region having a second type of doping; forming a field oxide layer on the epitaxial layer, the field oxide layer having a gate region window, a source region window and a drain region window preformed thereon; forming a first layer gate region in the channel region through the gate region window, the first layer gate region having the first type of doping; forming a gate region polysilicon at the gate region window, forming a source region polysilicon at the source region window, and forming a drain region polysilicon at the drain region window, the gate region polysilicon being in contact with the first layer gate region, the source region polysilicon and the drain region polysilicon being in contact with the channel region respectively; forming a second layer polysilicon gate region in the first layer gate region through the gate region polysilicon, the second layer polysilicon gate region having a first type of doping and being located on top of the first layer gate region; forming a polysilicon heavily doped source region in the channel region through the source region polysilicon and forming a polysilicon heavily doped drain region in the channel region through the drain region polysilicon, the polysilicon heavily doped source region having a second type of doping and being located on one side of the first layer gate region, the polysilicon heavily doped drain region having a second type of doping and being located on another side of the first layer gate region.

7. The method of producing a junction field effect transistor according to claim 6, wherein After forming the polysilicon heavily doped source region and the polysilicon heavily doped drain region, the manufacturing method of the junction type field effect device further comprises: forming a first dielectric layer on the field oxide layer, the gate region polysilicon, the source region polysilicon and the drain region polysilicon and etching to expose the gate region polysilicon, the source region polysilicon and the drain region polysilicon; forming a first metal layer on the residual first dielectric layer, the gate region polysilicon, the source region polysilicon and the drain region polysilicon and etching to obtain mutually independent gate metal, source metal and drain metal, the gate metal being in contact with the gate region polysilicon through the residual first dielectric layer, the source metal being in contact with the source region polysilicon through the residual first dielectric layer, and the drain metal being in contact with the drain region polysilicon through the residual first dielectric layer.

8. The method for manufacturing a junction field effect device according to claim 7, wherein: After forming the gate metal, the source metal and the drain metal, the manufacturing method of the junction type field effect device further comprises: forming a second dielectric layer on the gate metal, the source metal and the drain metal and etching to expose the gate metal, the source metal and the drain metal; forming a second metal layer on the residual second dielectric layer, the gate metal, the source metal and the drain metal and etching to obtain mutually independent gate additional metal, source additional metal and drain additional metal, the gate additional metal being in contact with the gate metal through the residual second dielectric layer, the source additional metal being in contact with the source metal through the residual second dielectric layer, and the drain additional metal being in contact with the drain metal through the residual second dielectric layer; forming a passivation layer covering the gate additional metal, the source additional metal and the drain additional metal; etching the passivation layer to expose the gate additional metal, the source additional metal and the drain additional metal.

9. The method of producing a junction field effect transistor according to Claim 8, wherein The second metal layer comprises an alloy layer.

10. The method of producing a junction field effect transistor according to Claim 8, wherein After etching the passivation layer to expose the gate additional metal, the source additional metal and the drain additional metal, the manufacturing method of the junction type field effect device further comprises: performing low temperature annealing treatment; sequentially performing testing, cutting, mounting, sintering, packaging and post-packaging testing treatment.

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