Method and device for controlling unbalance of three-phase four-leg full-bridge inverter and medium

Abstract

The application discloses a three-phase four-bridge-arm full-bridge inverter output voltage imbalance control method and device and a medium, and is suitable for the technical field of power electronics. According to the corresponding relationship among each output voltage reference value, an input direct current voltage value, each three-phase output voltage value and each three-phase output current value, the three-phase bridge-arm duty cycle of the next period is determined, so as to obtain the effective duty cycle and realize the control of the switching device of the three-phase bridge arm, thereby realizing the negative sequence imbalance degree suppression target. According to the corresponding relationship among each output voltage reference value, an input direct current voltage value, each three-phase output voltage value and each three-phase output current value, the zero sequence component is determined, the fourth phase bridge arm switching device duty cycle is calculated according to the differential feedforward algorithm, the control of the inverter neutral line current is realized, and the zero sequence imbalance degree of the inverter output voltage is suppressed.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a method, device and medium for controlling output voltage imbalance in a three-phase four-arm full-bridge inverter. Background Technology

[0002] As a high-power AC power device, the three-phase voltage source inverter is widely used in industrial applications such as distributed generation power supplies and microgrid systems, single-phase independent power supply and three-phase uninterruptible power supply, and three-phase AC motor drive systems due to its many advantages, including versatile operation and working modes, high power density, simple topology, and simple and flexible control and modulation methods. For specific three-phase linear balanced loads, traditional three-phase inverters can meet the control requirements of output three-phase balanced sinusoidal voltage. However, with the increasing number of single-phase loads and three-phase unbalanced loads in the system, the converter's output voltage will experience unbalanced distortion, and the negative sequence and zero sequence components in the three-phase unbalanced distorted voltage will adversely affect the load, thereby compromising the system's operational stability and reliability.

[0003] In addition to the abc three-phase bridge arms, the three-phase four-arm full-bridge inverter adds a z-bridge arm, thus offering advantages such as higher control freedom, zero-sequence control of load voltage and current, and three-phase imbalance suppression capability. To achieve the target of suppressing the output voltage imbalance of the three-phase four-arm full-bridge inverter, existing negative-sequence imbalance suppression methods and zero-sequence imbalance suppression methods both require modeling the control system, which involves a large amount of computation. The output voltage needs to be decomposed into positive, negative, and zero-sequence components, and then linear control is performed based on synchronous rotating coordinates. The implementation process of the control system is difficult and increases complexity, which to some extent limits industrial applications.

[0004] Therefore, finding a control method for the output voltage imbalance of a three-phase four-arm full-bridge inverter is urgently needed to be addressed by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a control method, device, and medium for unbalanced output voltage of a three-phase four-arm full-bridge inverter. This method can achieve three-phase load voltage balance control under unbalanced three-phase load conditions. The control method does not require a load voltage positive and negative sequence component separation algorithm, can be implemented in a stationary coordinate system, and the implementation process is relatively simple, thus having certain application value.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for controlling the output voltage imbalance of a three-phase four-arm full-bridge inverter, comprising:

[0007] Obtain the reference values ​​of each output voltage, the input DC voltage, each three-phase output voltage, and each three-phase output current of the three-phase four-arm full-bridge inverter for the current cycle;

[0008] The zero-sequence component and the duty cycle of the three-phase bridge arm are determined according to the corresponding relationship between the output voltage reference value, the input DC voltage value, the three-phase output voltage value, and the three-phase output current value for the next cycle.

[0009] The effective duty cycle of the three-phase bridge arm is determined according to the discrete control rules and the duty cycle of the three-phase bridge arm, and the effective duty cycle of the four-phase bridge arm is obtained by processing the zero-sequence component according to the differential feedforward algorithm.

[0010] The corresponding control signal is generated according to each effective duty cycle in order to control the power devices of the three-phase four-arm full-bridge inverter to suppress imbalance.

[0011] Preferably, determining the zero-sequence component and three-phase bridge arm duty cycle of the next cycle based on the correspondence between each of the output voltage reference values, the input DC voltage value, each of the three-phase output voltage values, and each of the three-phase output current values ​​includes:

[0012] The duty cycle of the three-phase bridge arm in the next cycle is determined based on the relationship between the output voltage reference value, the input DC voltage value, and the three-phase output current value.

[0013] The zero-sequence component output voltage value is obtained by processing the three-phase output voltage values ​​described above.

[0014] The zero-sequence component output current value is obtained by processing the three-phase output current values.

[0015] Preferably, the three-phase bridge arm duty cycle includes a high-power pulse duty cycle and a low-power pulse duty cycle. Determining the three-phase bridge arm duty cycle for the next cycle based on the relationship between each of the output voltage reference values, the input DC voltage value, and each of the three-phase output current values ​​includes:

[0016] Obtain the filtering parameters of the three-phase bridge arm, the angular frequency value of the three-phase output current, and the discrete control coefficient;

[0017] The first component of the three-phase bridge arm is determined based on the relationship between each of the output voltage reference values ​​and the input DC voltage values;

[0018] The second component of the three-phase bridge arm is determined based on the relationship between the filter parameters, the angular frequency value, and each of the three-phase output current values.

[0019] The first component and the second component are added together to obtain the component parameters;

[0020] The high-power pulse duty cycle is obtained by adding the component parameters to the discrete control coefficients.

[0021] The low-power pulse duty cycle is obtained by subtracting the component parameter from the discrete control coefficient.

[0022] Preferably, determining the effective duty cycle of the three-phase bridge arm based on the discrete control rule and the duty cycle of the three-phase bridge arm includes:

[0023] Each of the three-phase output voltage values ​​is compared with each of the reference voltage values;

[0024] If the three-phase output voltage value is less than the reference voltage value, then the high-power pulse duty cycle is taken as the effective duty cycle of the three-phase bridge arm.

[0025] If the three-phase output voltage value is greater than or equal to the reference voltage value, then the low-power pulse duty cycle is taken as the effective duty cycle of the three-phase bridge arm.

[0026] Preferably, the step of processing the zero-sequence component according to the differential feedforward algorithm to obtain the effective duty cycle of the four bridge arms includes:

[0027] Obtain the inductance parameters, capacitance parameters, time period between the current period and the next period, first-order difference operator, and second-order difference operator of the four bridge arms;

[0028] The first-order difference value is determined based on the relationship between the first-order operator, the zero-sequence component output current value, the input DC voltage value, the inductance parameter, the filter coefficient, and the time period.

[0029] The second-order difference value is determined based on the relationship between the second-order operator, the zero-sequence component output voltage value, the input DC voltage value, the inductor parameter, the capacitor parameter, the filter coefficient, and the time period.

[0030] The effective duty cycle of the four bridge arms is obtained by adding the first-order difference value and the second-order difference value.

[0031] Preferably, the step of generating corresponding control signals based on each effective duty cycle includes:

[0032] The corresponding control signal is obtained by processing each effective duty cycle using DPWM.

[0033] Preferably, each of the output voltage reference values ​​is a three-phase balanced sinusoidal value of the three-phase bridge arm.

[0034] To solve the above-mentioned technical problems, the present invention also provides a control device for output voltage imbalance of a three-phase four-arm full-bridge inverter, comprising:

[0035] The acquisition module is used to acquire the reference values ​​of each output voltage, the input DC voltage value, each three-phase output voltage value, and each three-phase output current value of the three-phase four-arm full-bridge inverter in the current cycle.

[0036] The first determining module is used to determine the zero-sequence component and the three-phase bridge arm duty cycle of the next cycle according to the corresponding relationship between each of the output voltage reference values, the input DC voltage value, each of the three-phase output voltage values, and each of the three-phase output current values.

[0037] The second determining module is used to determine the effective duty cycle of the three-phase bridge arm according to the discrete control rules and the duty cycle of the three-phase bridge arm, and to process the zero-sequence component according to the differential feedforward algorithm to obtain the effective duty cycle of the four-phase bridge arm.

[0038] The generation module is used to generate corresponding control signals based on each effective duty cycle in order to control the power devices of the three-phase four-arm full-bridge inverter to suppress imbalance.

[0039] To solve the above-mentioned technical problems, the present invention also provides a control device for output voltage imbalance of a three-phase four-arm full-bridge inverter, comprising:

[0040] Memory, used to store computer programs;

[0041] A processor is used to execute the computer program to implement the steps of the control method for output voltage imbalance of a three-phase four-arm full-bridge inverter as described above.

[0042] To address the aforementioned technical problems, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the control method for output voltage imbalance of a three-phase four-arm full-bridge inverter as described above.

[0043] This invention provides a control method for output voltage imbalance in a three-phase four-arm full-bridge inverter. Based on the correspondence between each output voltage reference value, the input DC voltage value, each three-phase output voltage value, and each three-phase output current value, the three-phase discrete duty cycle (three-phase arm duty cycle) for the next cycle is determined. This allows for the acquisition of an effective duty cycle to control the switching devices of the three-phase arms, thereby achieving the goal of suppressing negative sequence imbalance. By determining the zero-sequence component based on the correspondence between each output voltage reference value, the input DC voltage value, each three-phase output voltage value, and each three-phase output current value, and then calculating the duty cycle of the fourth-phase arm switching device using a differential feedforward algorithm, the neutral current of the inverter is controlled, thus suppressing the zero-sequence imbalance of the inverter output voltage. This method can achieve three-phase load voltage balance control under unbalanced three-phase load conditions. The control method does not require a load voltage positive and negative sequence component separation algorithm, can be implemented in a stationary coordinate system, and the implementation process is relatively simple, making it valuable for practical applications.

[0044] In addition, the present invention also provides a control device and medium for output voltage imbalance of a three-phase four-arm full-bridge inverter, which has the same beneficial effects as the above-described control method for output voltage imbalance of a three-phase four-arm full-bridge inverter. Attached Figure Description

[0045] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 A flowchart of a method for controlling output voltage imbalance in a three-phase four-arm full-bridge inverter provided in an embodiment of the present invention;

[0047] Figure 2 A schematic diagram of the structure of a three-phase four-arm full-bridge inverter provided in an embodiment of the present invention;

[0048] Figure 3 A schematic diagram of a zero-sequence voltage and current differential feedforward algorithm provided in an embodiment of the present invention;

[0049] Figure 4 A structural diagram of a control device for output voltage imbalance of a three-phase four-arm full-bridge inverter provided in an embodiment of the present invention;

[0050] Figure 5 A structural diagram of another control device for output voltage imbalance of a three-phase four-arm full-bridge inverter provided in an embodiment of the present invention;

[0051] Figure 6A steady-state time-domain simulation waveform of the three-phase output voltage under unbalanced load conditions (phase a and phase b operating with one phase missing) is provided for an embodiment of the present invention.

[0052] Figure 7 A steady-state time-domain simulation waveform of the three-phase output current under unbalanced load conditions (phase a and phase b operating with one phase missing) is provided for an embodiment of the present invention.

[0053] Figure 8 A steady-state time-domain simulation waveform of the z-arm current under unbalanced load conditions (phase a and phase b are operating with one phase missing) is provided for an embodiment of the present invention.

[0054] Figure 9 A steady-state time-domain simulation waveform of the zero-sequence component of the three-phase output current under unbalanced load conditions (phase a and phase b are operating with one phase missing) is provided for an embodiment of the present invention.

[0055] Figure 10 A steady-state time-domain simulation waveform of the zero-sequence component of the three-phase output voltage under unbalanced load conditions (phase a and phase b are operating with one phase missing) is provided for an embodiment of the present invention.

[0056] Figure 11 A steady-state time-domain simulation waveform of the three-phase output voltage under unbalanced load conditions (phase a is operating with one phase missing) is provided for an embodiment of the present invention.

[0057] Figure 12 A steady-state time-domain simulation waveform of the three-phase output current under unbalanced load conditions (phase a is operating with one phase missing) is provided for an embodiment of the present invention.

[0058] Figure 13 A steady-state time-domain simulation waveform of the z-arm current under unbalanced load conditions (phase a is operating with one phase missing) is provided for an embodiment of the present invention.

[0059] Figure 14 A steady-state time-domain simulation waveform of the zero-sequence component of the three-phase output current under unbalanced load conditions (phase a is operating with one phase missing) is provided for an embodiment of the present invention.

[0060] Figure 15 The steady-state time-domain simulation waveform of the zero-sequence component of the three-phase output voltage under unbalanced load conditions (phase a is operating with one phase missing) is provided for an embodiment of the present invention. Detailed Implementation

[0061] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0062] The core of this invention is to provide a method, device, and medium for controlling the output voltage imbalance of a three-phase four-arm full-bridge inverter. This method can achieve three-phase load voltage balance control under unbalanced three-phase load conditions. The control method does not require a load voltage positive and negative sequence component separation algorithm, can be implemented in a stationary coordinate system, and the implementation process is relatively simple, thus having certain application value.

[0063] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0064] Understandably, to achieve the goal of suppressing the output voltage imbalance of a three-phase four-arm full-bridge inverter, there are two main suppression methods: negative-sequence imbalance suppression and zero-sequence imbalance suppression. Current research on negative-sequence output voltage imbalance suppression mainly focuses on synchronous rotating coordinate systems. This involves decomposing the inverter output voltage into positive, negative, and zero-sequence components using the symmetrical component method, and then performing sequential control based on linear control methods (such as PI control) within the synchronous rotating coordinate system to achieve the negative-sequence imbalance suppression target. However, the specific implementation of the positive and negative sequence component decomposition algorithm is the main challenge of this control method. Currently, the positive and negative sequence symmetrical component decomposition algorithm for output voltage is mainly implemented using first-order all-pass filters, conventional integration methods, and positive and negative sequence separation methods based on reduced-order generalized integrators, increasing the complexity of the control system and the difficulty of its software implementation.

[0065] Load imbalance control methods for three-phase four-arm full-bridge inverters based on a stationary coordinate system often employ linear controllers (such as proportional resonant controllers and Quasi-PR controllers). However, the imbalance suppression effect of linear controllers is limited. Furthermore, researchers both domestically and internationally have used finite set model predictive control (MMDC) to achieve load imbalance control for three-phase four-arm full-bridge inverters. However, MMDC suffers from drawbacks such as requiring high-precision modeling of the control system, large computational load, high software cost, and implementation difficulties, limiting its application in practical engineering and thus its value in the power industry.

[0066] Current research on output voltage zero-sequence imbalance suppression methods mainly focuses on virtual synchronous rotating coordinate systems. This involves constructing a virtual positive-sequence current form from three zero-sequence currents with the same phase amplitude through phase shifting, and then converting it to a DC form in the virtual synchronous rotating coordinate system. Utilizing the zero-steady-state error tracking capability of the proportional-integral (PI) controller, a good zero-sequence imbalance suppression target can be achieved. However, this method requires virtual synchronous rotating coordinate transformation and the construction of a virtual positive-sequence form for the zero-sequence component, resulting in significant computational complexity and high software costs. Output voltage zero-sequence imbalance suppression methods based on stationary coordinate systems are mainly implemented using linear controllers (such as proportional resonant controllers and Quasi-PR controllers). These controllers achieve good output voltage zero-sequence imbalance suppression by leveraging their high gain at the resonant frequency. However, proportional resonant controllers suffer from the drawback of being affected by output voltage frequency deviations, and the Quasi-PR controller's control loop design and parameter tuning process are complex, increasing the difficulty of software implementation and limiting its industrial application to some extent.

[0067] The embodiments of the present invention are mainly based on the above-mentioned technical problems, and provide a method for controlling the output voltage imbalance of a three-phase four-arm full-bridge inverter. Figure 1 A flowchart illustrating a method for controlling output voltage imbalance in a three-phase four-arm full-bridge inverter, as provided in an embodiment of the present invention, is shown below. Figure 1 As shown, the method includes:

[0068] S11: Obtain the reference values ​​of each output voltage, input DC voltage, each three-phase output voltage, and each three-phase output current of the three-phase four-arm full-bridge inverter for the current cycle;

[0069] S12: Determine the zero-sequence component and three-phase bridge arm duty cycle of the next cycle according to the corresponding relationship of each output voltage reference value, input DC voltage value, each three-phase output voltage value, and each three-phase output current value.

[0070] S13: Determine the effective duty cycle of the three-phase bridge arm according to the discrete control rules and the duty cycle of the three-phase bridge arm, and process the zero-sequence component according to the differential feedforward algorithm to obtain the effective duty cycle of the four-phase bridge arm;

[0071] S14: Generate corresponding control signals based on each effective duty cycle to control the power devices of the three-phase four-arm full-bridge inverter to suppress imbalance.

[0072] Figure 2 This is a schematic diagram of the structure of a three-phase four-arm full-bridge inverter provided in an embodiment of the present invention, as shown below. Figure 2As shown, in addition to the inverter itself, the inverter device also includes a discrete controller, which includes: an output voltage and current sampling and analog-to-digital conversion module, a PxH and PxL pulse duty cycle calculation module, a PxH and PxL pulse duty cycle selection module, a load voltage and current zero-sequence component calculation module, a zero-sequence voltage and current differential feedforward algorithm module, and a DPWM drive module.

[0073] This function retrieves the parameters for the current cycle of a three-phase, four-arm full-bridge inverter. The current cycle can be the switching cycle (sampling cycle and control cycle), and the number of switching cycles is not limited; it can be a specific time period. The parameters are the reference values ​​for each output voltage, where each output voltage reference is the three-phase output voltage reference value u. a * (k), u b * (k), u c * (k); The input DC voltage value is obtained at the beginning of the k-th switching cycle through a sampling and analog-to-digital conversion module, which yields the digital signal u of the input DC voltage of the three-phase four-arm full-bridge inverter. dc (k); The value of each three-phase output voltage is a digital signal u of the three-phase output voltage. a (k), u b (k), u c (k); the value of each three-phase output current is the digital signal i of the three-phase output current. a (k), i b (k), i c (k).

[0074] As one embodiment, the reference value for each output voltage is the three-phase balanced sinusoidal value of the three-phase bridge arm.

[0075] Specifically, the output voltage reference values ​​have the same frequency, the same amplitude, and a phase difference of 120°.

[0076] After obtaining all parameters, step S12 proceeds to determine the zero-sequence component and three-phase bridge arm duty cycle for the next cycle based on the corresponding relationships between the output voltage reference values, input DC voltage values, three-phase output voltage values, and three-phase output current values. It is understood that the correspondence between parameters does not involve every single parameter; it can be data determined by the correspondence between two or three of the four parameters, or data determined by the correspondence between values ​​of a specific parameter. There are no restrictions here; the settings can be tailored to the actual situation.

[0077] As one embodiment, the zero-sequence component and three-phase bridge arm duty cycle of the next cycle are determined based on the correspondence between each output voltage reference value, input DC voltage value, each three-phase output voltage value, and each three-phase output current value, including:

[0078] The duty cycle of the three-phase bridge arm in the next cycle is determined based on the relationship between the reference values ​​of each output voltage, the input DC voltage value, and the three-phase output current value.

[0079] The zero-sequence component output voltage value is obtained by processing the three-phase output voltage values.

[0080] The zero-sequence component output current value is obtained by processing the three-phase output current values.

[0081] Specifically, the effective output of the three-phase bridge arm duty cycle junction determines the average voltage output to the motor. In other words, by adjusting the duty cycle, the output voltage can be adjusted. In digital circuits, the duty cycle is directly related to the pulse width, and the pulse width resolution directly affects the control accuracy to achieve the suppression target.

[0082] The duty cycle of the three-phase bridge arm is determined by the relationship between the reference values ​​of each output voltage, the input DC voltage, and the three-phase output current values ​​for the current cycle. Correspondingly, the duty cycle of the three-phase bridge arm includes duty cycles for high-power pulses and duty cycles for low-power pulses, which are not limited here. Regardless of the type of duty cycle, it can be obtained from the above parameters.

[0083] The zero-sequence output voltage value is obtained by processing the sum of the three-phase output voltage values, and the zero-sequence output current value is obtained by processing the sum of the three-phase output current values. The specific formulas are as follows:

[0084] u z (k)=∑u x (k)=u a (k)+u b (k)+u c (k)

[0085] i z (k)=∑i x (k)=i a (k)+i b (k)+i c (k)

[0086] Among them, u z (k) represents the zero-sequence component output voltage value, i z (k) represents the zero-sequence component output current value.

[0087] In step S13, the effective duty cycle is obtained according to its respective duty cycle. The method for obtaining the effective duty cycle is different for three-phase bridge arms and four-phase bridge arms. In the process of determining the effective duty cycle of three-phase bridge arms, it is determined by discrete control rules and the corresponding duty cycle. In the process of determining the effective duty cycle of four-phase bridge arms, it is determined by differential feedforward algorithm and the corresponding zero-sequence component.

[0088] In discrete control rules, the discrete control method is formulated by following the given changes in the duty cycle signal through feedback. The target voltage or target current output is achieved by controlling the duty cycle. The differential feedforward algorithm obtains the effective duty cycle by adjusting the zero-sequence component to cause changes in the duty cycle.

[0089] It should be noted that the effective duty cycle of the three-phase bridge arm generates a corresponding control signal to suppress load imbalance, while the effective duty cycle of the four-phase bridge arm generates a corresponding control signal to suppress zero-sequence voltage imbalance. As one embodiment, the control signal generated according to each effective duty cycle includes:

[0090] The corresponding control signals are obtained by processing each effective duty cycle using DPWM.

[0091] Specifically, Digital Pulse Width Modulation (DPWM) is a variant of SVPWM technology used to reduce inverter switching losses. The effective duty cycle of the three phases is generated via DPWM to produce control signals for the three-phase bridge arms of the inverter, controlling... Figure 2 The power devices Sap,n,Sbp,n, and Scp,n in the inverter are used to suppress load imbalance in the inverter output voltage. The effective duty cycle of the four bridge arms (z-arms) is used to generate control signals for the z-arms of the inverter via DPWM, controlling... Figure 2 The power device Szp,n in the inverter realizes the function of suppressing the zero-sequence imbalance of the inverter output voltage.

[0092] This invention provides a method for controlling output voltage imbalance in a three-phase four-arm full-bridge inverter. The method involves determining the three-phase discrete duty cycle (three-phase arm duty cycle) for the next cycle based on the correspondence between each output voltage reference value, the input DC voltage value, each three-phase output voltage value, and each three-phase output current value. This allows for obtaining an effective duty cycle to control the switching devices of the three-phase arms, thereby achieving the goal of suppressing negative sequence imbalance. The zero-sequence component is determined based on the correspondence between each output voltage reference value, the input DC voltage value, each three-phase output voltage value, and each three-phase output current value. Then, the duty cycle of the fourth-phase arm switching device is calculated using a differential feedforward algorithm to control the inverter's neutral current, thereby suppressing the zero-sequence imbalance of the inverter's output voltage. This method can achieve three-phase load voltage balance control under unbalanced three-phase load conditions. The control method does not require a load voltage positive and negative sequence component separation algorithm, can be implemented in a stationary coordinate system, and the implementation process is relatively simple, making it valuable for practical applications.

[0093] Based on the above embodiments, the three-phase bridge arm duty cycle includes a high-power pulse duty cycle and a low-power pulse duty cycle. The three-phase bridge arm duty cycle for the next cycle is determined according to the relationship between each output voltage reference value, the input DC voltage value, and each three-phase output current value, including:

[0094] Obtain the filtering parameters of the three-phase bridge arm, the angular frequency value of the three-phase output current, and the discrete control coefficients;

[0095] The first component of the three-phase bridge arm is determined based on the relationship between each output voltage reference value and the input DC voltage value.

[0096] The second component of the three-phase bridge arm is determined based on the relationship between the filter parameters, angular frequency value, and the output current value of each three phase.

[0097] The first component and the second component are added together to obtain the component parameters;

[0098] The high-power pulse duty cycle is obtained by adding the component parameters to the discrete control coefficients.

[0099] The low-power pulse duty cycle is obtained by subtracting the component parameters from the discrete control coefficients.

[0100] Specifically, the filter parameters L of the three-phase bridge arms, the angular frequency ω of the three-phase output current, and the discrete control coefficients are obtained. Δk .

[0101] The first component is determined by the relationship between each output voltage reference value and the input DC voltage value, as shown in the following formula:

[0102]

[0103] Among them, u a * (k), u b * (k), u c * (k) is the output voltage reference value, u dc (k) represents the input DC voltage value;

[0104] The second component is determined by the relationship between the filter parameters, the angular frequency value, and the output current values ​​of each of the three phases, as shown in the following formula:

[0105]

[0106] Where L is the filter parameter, i a (k), i b (k), i c (k) represents the corresponding three-phase output current value, u dc(k) represents the input DC voltage value, and ω represents the angular frequency value of the three-phase output voltage or current.

[0107] Adding the first and second components in the above formula yields the component parameters. Adding the component parameters to the discrete control coefficients yields the high-power pulse duty cycle D. aH (k+1),D bH (k+1),D cH (k+1), the specific formula is as follows:

[0108]

[0109] in, Δk These are the discrete control coefficients in discrete control methods.

[0110] The low-power pulse duty cycle D is obtained by subtracting the component parameters from the discrete control coefficients. aL (k+1),D bL (k+1),D cL (k+1), the specific formula is as follows:

[0111]

[0112] Based on the above embodiments, the effective duty cycle of the three-phase bridge arm is determined according to the discrete control rules and the duty cycle of the three-phase bridge arm, including:

[0113] Each of the three-phase output voltage values ​​is compared with its respective reference voltage value;

[0114] If the three-phase output voltage value is less than the reference voltage value, the high-power pulse duty cycle will be used as the effective duty cycle of the three-phase bridge arm.

[0115] If the three-phase output voltage value is greater than or equal to the reference voltage value, then the low-power pulse duty cycle is taken as the effective duty cycle of the three-phase bridge arm.

[0116] Specifically, the three-phase output voltage values ​​u a (k), u b (k), u c (k) is related to each reference voltage value u. a * (k), u b * (k), u c * (k) A comparison is made. If the three-phase output voltage value is less than the corresponding reference voltage value, the high-power pulse duty cycle is used as the effective duty cycle of the three-phase bridge arm; otherwise, the low-power pulse duty cycle is used as the effective duty cycle of the three-phase bridge arm. For example, the sampling value u of the output voltage of phase a. a (k) is less than its reference value u a *When (k), the duty cycle selector selects the high-power pulse duty cycle D. aH (k+1) represents the effective duty cycle D of the (k+1)th sampling period (the next period). a (k+1), otherwise, select a low-power pulse duty cycle D. aL (k+1) represents the effective duty cycle D of the (k+1)th sampling period. a (k+1); The discrete control rules for phases b and c are similar to those for phase a. Based on the discrete control rules, the effective duty cycle D of the three-phase bridge arm is obtained. a (k+1),D b (k+1),D c (k+1).

[0117] The process for determining the effective duty cycle of the three bridge arms provided in this embodiment of the invention facilitates subsequent control of the switching devices of the three bridge arms to achieve the goal of suppressing negative sequence imbalance.

[0118] Based on the above embodiments, corresponding to the effective duty cycle process of the four bridge arms (z-arm), step S13, which processes the zero-sequence component according to the differential feedforward algorithm to obtain the effective duty cycle of the four bridge arms, includes:

[0119] Obtain the inductance parameters, capacitance parameters, time period of the current cycle and the next cycle, first-order difference operator and second-order difference operator of the four bridge arms;

[0120] The first-order difference value is determined based on the relationship between the first-order operator, the zero-sequence component output current value, the input DC voltage value, the inductor parameters, the filter coefficient, and the time period.

[0121] The second-order difference value is determined based on the relationship between the second-order operator, the zero-sequence component output voltage value, the input DC voltage value, the inductor parameters, the capacitor parameters, the filter coefficient, and the time period.

[0122] The effective duty cycle of the four bridge arms is obtained by adding the first-order difference value and the second-order difference value.

[0123] Specifically, Figure 3 A schematic diagram of a zero-sequence voltage and current differential feedforward algorithm provided in an embodiment of the present invention is shown below. Figure 3 As shown, the effective duty cycle D of the four bridge arms is obtained by using the zero-sequence component output voltage value and the zero-sequence component output current value according to this algorithm. z (k+1) to generate the corresponding control signal G zp,n (k+1).

[0124] Obtain the inductance parameter L of the four bridge arms z Capacitor parameter C, time period T between the current period and the next period s First-order difference operator ▽, second-order difference operator ▽ 2It should be noted that the time period T s Unlike the sampling period k+1, which is a matter of order, the time period in this embodiment is the time span corresponding to two sampling periods.

[0125] The first-order difference value is determined by the relationship between the first-order operator, the zero-sequence component output current value, the input DC voltage value, the inductor parameters, the filter coefficient, and the time period. The specific formula is as follows:

[0126]

[0127] Among them, i z (k) represents the zero-sequence component output current value, u dc L is the input DC voltage value, and L is the filter parameter; z T represents the inductance parameters of the four bridge arms. s ∠ represents the time period between the current period and the next period, and ▽ represents the first-order difference operator.

[0128] The second-order difference value is determined by the relationship between the second-order operator, the zero-sequence component output voltage value, the input DC voltage value, the inductor parameters, the capacitor parameters, the filter coefficient, and the time period. The specific formula is as follows:

[0129]

[0130] Among them, u z (k) represents the zero-sequence component output voltage value, u dc L is the input DC voltage value, and L is the filter parameter; z Here are the inductance parameters for the four bridge arms, C is the capacitance parameter, and T is the capacitance parameter. s The time period between the current cycle and the next cycle, ▽ 2 It is a second-order difference operator.

[0131] The effective duty cycle of the four bridge arms is obtained by adding the first-order difference value and the second-order difference value, as shown in the following formula:

[0132]

[0133] in, The first difference value, It is the second-order difference value.

[0134] The process for determining the effective duty cycle of the four bridge arms provided in this embodiment of the invention facilitates the subsequent control of the switching devices of the four bridge arms to achieve the goal of zero-sequence imbalance suppression.

[0135] The foregoing has described in detail various embodiments of the control method for output voltage imbalance in a three-phase four-arm full-bridge inverter. Based on this, the present invention also discloses a control device for output voltage imbalance in a three-phase four-arm full-bridge inverter corresponding to the above method. Figure 4 This is a structural diagram of a control device for output voltage imbalance in a three-phase four-arm full-bridge inverter, provided as an embodiment of the present invention. Figure 4 As shown, the control device for output voltage imbalance of a three-phase four-arm full-bridge inverter includes:

[0136] The acquisition module 11 is used to acquire the reference values ​​of each output voltage, the input DC voltage value, each three-phase output voltage value, and each three-phase output current value of the three-phase four-arm full-bridge inverter in the current cycle.

[0137] The first determining module 12 is used to determine the zero-sequence component and the duty cycle of the three-phase bridge arm in the next cycle according to the corresponding relationship between each output voltage reference value, the input DC voltage value, each three-phase output voltage value, and each three-phase output current value.

[0138] The second determining module 13 is used to determine the effective duty cycle of the three-phase bridge arm according to the discrete control rules and the duty cycle of the three-phase bridge arm, and to process the zero-sequence component according to the differential feedforward algorithm to obtain the effective duty cycle of the four-phase bridge arm.

[0139] The generation module 14 is used to generate corresponding control signals according to each effective duty cycle so as to control the power devices of the three-phase four-arm full-bridge inverter to suppress imbalance.

[0140] Since the embodiments of the device part correspond to the embodiments described above, please refer to the embodiments described in the method part for the embodiments of the device part, and will not be repeated here.

[0141] For an introduction to the control device for output voltage imbalance of a three-phase four-arm full-bridge inverter provided by the present invention, please refer to the above method embodiment. The present invention will not be described in detail here, but it has the same beneficial effects as the above-mentioned control method for output voltage imbalance of a three-phase four-arm full-bridge inverter.

[0142] Figure 5 A structural diagram of another control device for output voltage imbalance of a three-phase four-arm full-bridge inverter provided in an embodiment of the present invention is shown below. Figure 5 As shown, the device includes:

[0143] Memory 21 is used to store computer programs;

[0144] Processor 22 is used to execute computer programs to implement steps of a control method for output voltage imbalance of a three-phase four-arm full-bridge inverter.

[0145] The processor 22 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 22 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 22 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 22 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 22 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0146] The memory 21 may include one or more computer-readable storage media, which may be non-transitory. The memory 21 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 21 is used to store at least the following computer program 211, which, after being loaded and executed by the processor 22, is capable of implementing the relevant steps of the control method for the output voltage imbalance of a three-phase four-arm full-bridge inverter disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 21 may also include an operating system 212 and data 213, etc., and the storage method may be temporary storage or permanent storage. The operating system 212 may include Windows, Unix, Linux, etc. The data 213 may include, but is not limited to, the data involved in the control method for the output voltage imbalance of a three-phase four-arm full-bridge inverter, etc.

[0147] In some embodiments, the control device for the output voltage imbalance of a three-phase four-arm full-bridge inverter may further include a display screen 23, an input / output interface 24, a communication interface 25, a power supply 26, and a communication bus 27.

[0148] Those skilled in the field can understand, Figure 5 The structure shown does not constitute a limitation on the control device for output voltage imbalance of a three-phase four-arm full-bridge inverter and may include more or fewer components than shown.

[0149] The processor 22 implements the control method for output voltage imbalance of the three-phase four-arm full-bridge inverter provided in any of the above embodiments by calling the instructions stored in the memory 21.

[0150] For an introduction to another control device for the output voltage imbalance of a three-phase four-arm full-bridge inverter provided by the present invention, please refer to the above method embodiment. The present invention will not be described in detail here, but it has the same beneficial effects as the above-described control method for the output voltage imbalance of a three-phase four-arm full-bridge inverter.

[0151] Furthermore, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by processor 22, implements the steps of the control method for output voltage imbalance of a three-phase four-arm full-bridge inverter as described above.

[0152] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0153] For an introduction to the computer-readable storage medium provided by the present invention, please refer to the above method embodiments. The present invention will not be described in detail here, but it has the same beneficial effects as the above-described method for controlling the output voltage imbalance of a three-phase four-arm full-bridge inverter.

[0154] As one example, Figure 6 This invention provides a steady-state time-domain simulation waveform of the three-phase output voltage under unbalanced load conditions (phase a and phase b operating with one or more phases missing), as shown in the embodiment of the invention. Figure 7 A steady-state time-domain simulation waveform of the three-phase output current under unbalanced load conditions (phase a and phase b operating with one phase missing) is provided for an embodiment of the present invention, as shown below. Figure 6 , 7 As shown, in i a (k) Normal, i b (k) and i cWhen (k) is 0, load problems occur. The three-phase output voltage imbalance is suppressed by the control method of the three-phase four-arm full-bridge inverter output voltage imbalance of the present invention.

[0155] Figure 8 This invention provides a steady-state time-domain simulation waveform of the z-arm current under unbalanced load conditions (phase a and phase b operating with one or more phases missing) as an embodiment of the invention. Figure 9 This invention provides a steady-state time-domain simulation waveform of the zero-sequence component of the three-phase output current under unbalanced load conditions (phase a and phase b operating with one phase missing). Figure 10 A steady-state time-domain simulation waveform of the zero-sequence component of the three-phase output voltage under unbalanced load conditions (phase a and phase b operating with one phase missing) is provided as an embodiment of the present invention. Figure 8-10 As shown, the z-arm exhibits a zero-sequence component. Figure 8 , Figure 10 The output voltage imbalance control method of the three-phase four-arm full-bridge inverter of the present invention suppresses the output voltage imbalance.

[0156] Figure 11 This invention provides a steady-state time-domain simulation waveform of the three-phase output voltage under unbalanced load conditions (phase a is operating with one phase missing) according to an embodiment of the invention. Figure 12 The steady-state time-domain simulation waveform of the three-phase output current under unbalanced load conditions (phase a is operating with one phase missing) is provided in an embodiment of the present invention, as shown below. Figure 11 , 12 As shown, the i-th phase of the three-phase bridge arm c (k) being 0 leads to load imbalance. The output voltage imbalance of the three-phase four-arm full-bridge inverter of the present invention is used to suppress the output voltage imbalance.

[0157] Figure 13 This is a steady-state time-domain simulation waveform of the z-arm current under unbalanced load conditions (phase a is operating with one phase missing) provided in an embodiment of the present invention. Figure 14 This invention provides a steady-state time-domain simulation waveform of the zero-sequence component of the three-phase output current under unbalanced load conditions (phase a is operating with one phase missing) in an embodiment of the invention. Figure 15 A steady-state time-domain simulation waveform of the zero-sequence component of the three-phase output voltage under unbalanced load conditions (phase a is operating with one phase missing) is provided for an embodiment of the present invention, as shown in the figure. Figure 13-15 As shown, the z-arm exhibits a zero-sequence component. Figure 13 , Figure 15 The output voltage imbalance control method of the three-phase four-arm full-bridge inverter of the present invention suppresses the output voltage imbalance.

[0158] The above verification process demonstrates the feasibility of the control method for output voltage imbalance of the three-phase four-arm full-bridge inverter provided in this embodiment.

[0159] The foregoing has provided a detailed description of the control method, device, and medium for output voltage imbalance in a three-phase four-arm full-bridge inverter provided by this invention. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from the principles of the invention, and these improvements and modifications also fall within the protection scope of the claims of this invention.

[0160] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for controlling output voltage imbalance in a three-phase four-arm full-bridge inverter, characterized in that, include: Obtain the reference values ​​of each output voltage, the input DC voltage, each three-phase output voltage, and each three-phase output current of the three-phase four-arm full-bridge inverter for the current cycle; The zero-sequence component and the duty cycle of the three-phase bridge arm are determined according to the corresponding relationship between the output voltage reference value, the input DC voltage value, the three-phase output voltage value, and the three-phase output current value for the next cycle. The effective duty cycle of the three-phase bridge arm is determined according to the discrete control rules and the duty cycle of the three-phase bridge arm, and the effective duty cycle of the four-phase bridge arm is obtained by processing the zero-sequence component according to the differential feedforward algorithm. The corresponding control signal is generated according to each effective duty cycle in order to control the power devices of the three-phase four-arm full-bridge inverter to suppress imbalance. Correspondingly, the step of processing the zero-sequence component using the differential feedforward algorithm to obtain the effective duty cycle of the four bridge arms includes: Obtain the inductance parameters, capacitance parameters, time period between the current period and the next period, first-order difference operator, and second-order difference operator of the four bridge arms; The first-order difference value is determined based on the relationship between the first-order difference operator, the zero-sequence component output current value, the input DC voltage value, the inductance parameters, the filter parameters, and the time period. The second-order difference value is determined based on the relationship between the second-order difference operator, the zero-sequence component output voltage value, the input DC voltage value, the inductor parameter, the capacitor parameter, the filter parameter, and the time period. The effective duty cycle of the four bridge arms is obtained by adding the first-order difference value and the second-order difference value.

2. The method for controlling output voltage imbalance in a three-phase four-arm full-bridge inverter according to claim 1, characterized in that, The step of determining the zero-sequence component and three-phase bridge arm duty cycle of the next cycle based on the corresponding relationships of each of the output voltage reference values, the input DC voltage value, each of the three-phase output voltage values, and each of the three-phase output current values ​​includes: The duty cycle of the three-phase bridge arm in the next current cycle is determined based on the relationship between the output voltage reference value, the input DC voltage value, and the three-phase output current value. The zero-sequence component output voltage value is obtained by processing the three-phase output voltage values ​​described above. The zero-sequence component output current value is obtained by processing the three-phase output current values.

3. The method for controlling output voltage imbalance in a three-phase four-arm full-bridge inverter according to claim 2, characterized in that, The three-phase bridge arm duty cycle includes a high-power pulse duty cycle and a low-power pulse duty cycle. Determining the three-phase bridge arm duty cycle for the next cycle based on the relationship between each output voltage reference value, the input DC voltage value, and each three-phase output current value includes: Obtain the filtering parameters of the three-phase bridge arm, the angular frequency value of the three-phase output current, and the discrete control coefficient; The first component of the three-phase bridge arm is determined based on the relationship between each of the output voltage reference values ​​and the input DC voltage values; The second component of the three-phase bridge arm is determined based on the relationship between the filter parameters, the angular frequency value, and each of the three-phase output current values. The first component and the second component are added together to obtain the component parameters; The high-power pulse duty cycle is obtained by adding the component parameters to the discrete control coefficients. The low-power pulse duty cycle is obtained by subtracting the component parameter from the discrete control coefficient.

4. The method for controlling output voltage imbalance in a three-phase four-arm full-bridge inverter according to claim 3, characterized in that, The determination of the effective duty cycle of the three-phase bridge arm based on the discrete control rules and the duty cycle of the three-phase bridge arm includes: Each of the three-phase output voltage values ​​is compared with its respective output voltage reference value; If the three-phase output voltage value is less than the output voltage reference value, then the high-power pulse duty cycle is taken as the effective duty cycle of the three-phase bridge arm. If the three-phase output voltage value is greater than or equal to the output voltage reference value, then the low-power pulse duty cycle is taken as the effective duty cycle of the three-phase bridge arm.

5. The method for controlling output voltage imbalance in a three-phase four-arm full-bridge inverter according to any one of claims 1 to 4, characterized in that, The generation of corresponding control signals based on each effective duty cycle includes: The corresponding control signal is obtained by processing each effective duty cycle using DPWM.

6. The method for controlling output voltage imbalance in a three-phase four-arm full-bridge inverter according to claim 5, characterized in that, The reference value for each output voltage is the three-phase balanced sinusoidal value of the three-phase bridge arm.

7. A control device for output voltage imbalance in a three-phase four-arm full-bridge inverter, characterized in that, include: The acquisition module is used to acquire the reference values ​​of each output voltage, the input DC voltage value, each three-phase output voltage value, and each three-phase output current value of the three-phase four-arm full-bridge inverter in the current cycle. The first determining module is used to determine the zero-sequence component and the three-phase bridge arm duty cycle of the next cycle according to the corresponding relationship between each of the output voltage reference values, the input DC voltage value, each of the three-phase output voltage values, and each of the three-phase output current values. The second determining module is used to determine the effective duty cycle of the three-phase bridge arm according to the discrete control rules and the duty cycle of the three-phase bridge arm, and to process the zero-sequence component according to the differential feedforward algorithm to obtain the effective duty cycle of the four-phase bridge arm. The generation module is used to generate corresponding control signals according to each effective duty cycle so as to control the power devices of the three-phase four-arm full-bridge inverter to suppress imbalance. Correspondingly, the step of processing the zero-sequence component using the differential feedforward algorithm to obtain the effective duty cycle of the four bridge arms includes: Obtain the inductance parameters, capacitance parameters, time period between the current period and the next period, first-order difference operator, and second-order difference operator of the four bridge arms; The first-order difference value is determined based on the relationship between the first-order difference operator, the zero-sequence component output current value, the input DC voltage value, the inductance parameters, the filter parameters, and the time period. The second-order difference value is determined based on the relationship between the second-order difference operator, the zero-sequence component output voltage value, the input DC voltage value, the inductor parameter, the capacitor parameter, the filter parameter, and the time period. The effective duty cycle of the four bridge arms is obtained by adding the first-order difference value and the second-order difference value.

8. A control device for output voltage imbalance in a three-phase four-arm full-bridge inverter, characterized in that, include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the steps of the control method for output voltage imbalance of a three-phase four-arm full-bridge inverter as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the control method for output voltage imbalance of a three-phase four-arm full-bridge inverter as described in any one of claims 1 to 6.

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