An energy storage dormancy awakening system and method in an off-grid state

Abstract

The present invention discloses an energy storage hibernation wake-up system and method in an off-grid state, comprising a first manual starter, a second manual starter, a BMS wake-up circuit, and a main control board wake-up circuit; the BMS wake-up circuit is respectively connected to the power output of a DC / DC converter and the power input of a BMS, and has two wake-up enable terminals, respectively connected to the first manual starter and the signal output of the BMS; the main control board wake-up circuit is respectively connected to the power output of the DC / DC converter and the power input of the main control board, and has two wake-up enable terminals, respectively connected to the second manual starter and the signal output of the main control board. The present invention can manually wake up the system through the manual starter and achieve self-maintenance of wake-up by relying on its own signal output. When the SOC of the energy storage system is too low, the system automatically powers off and goes into hibernation, achieving intelligent power on / off and hibernation without the need for operation and maintenance personnel, avoiding battery undervoltage hibernation, and reducing system maintenance costs.

Description

Technical Field

[0001] The present invention relates to the technical field of energy storage system dormancy and awakening technology, and in particular to an energy storage dormancy and awakening system and method in an off-grid state. Background Art

[0002] Existing home energy storage systems consist of a battery pack, photovoltaic panels, a PCS, a DC / DC converter (DC-DC converter), a control board, and electrical components. The DC / DC converter is powered by the battery pack, outputting 24V to the main control board and the battery management system (BMS). After receiving the system startup signal, the main control board sends a wake-up signal to the BMS to apply high voltage. Meanwhile, photovoltaic power generation can reversely charge the battery pack through the PCS. However, during extended periods of off-grid operation and without external photovoltaic or wind power generation, the home energy storage system can deplete its stored energy and enter an undervoltage sleep state. However, the excessive static power consumption of a home energy storage system in this undervoltage sleep state causes the battery cells to continuously lose power, leading to irreversible damage to the lithium battery and increasing system maintenance costs. Furthermore, systems that enter full sleep mode require on-site operations and maintenance personnel to restart the system, further increasing system maintenance costs. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide an energy storage sleep and wake-up system and method in an off-grid state, intelligently control the power on and off and sleep of the system, and reduce the maintenance cost of the system.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] An energy storage dormancy wake-up system in an off-grid state includes a first manual starter, a second manual starter, a BMS wake-up circuit, and a main control board wake-up circuit;

[0006] The BMS wake-up circuit is connected to the power supply output terminal of the DCDC and the power supply input terminal of the BMS respectively. The BMS wake-up circuit has two wake-up enable terminals, which are respectively connected to the first manual starter and the signal output terminal of the BMS;

[0007] The main control board wake-up circuit is respectively connected to the power supply output terminal of the DCDC and the power supply input terminal of the main control board. The main control board wake-up circuit has two wake-up enable terminals, which are respectively connected to the second manual starting component and the signal output terminal of the main control board;

[0008] The BMS wake-up circuit is used to connect the power supply output end of the DCDC and the power supply input end of the BMS, the main control board wake-up circuit is used to connect the power supply output end of the DCDC and the power supply input end of the main control board, and the first manual starting component and the second manual starting component are both used to output enable signals.

[0009] In order to solve the above technical problems, another technical solution adopted by the present invention is:

[0010] A method for waking up from energy storage dormancy in an off-grid state, applied to the above-mentioned off-grid energy storage dormancy waking up system, comprises the following steps:

[0011] S1. Outputting an enable signal to a first wake-up enable terminal of a BMS wake-up circuit through a first manual starting component, so that the BMS is awakened and outputs an enable signal to a second wake-up enable terminal of the BMS wake-up circuit;

[0012] S2, outputting an enable signal to a first wake-up enable terminal of a main control board wake-up circuit through a second manual starting component, so that the main control board is awakened and outputs an enable signal to a second wake-up enable terminal of the main control board wake-up circuit;

[0013] S3. When the SOC of the energy storage system is too low, the BMS and the main control board both stop outputting enable signals.

[0014] The beneficial effects of the present invention are: providing an energy storage hibernation and wake-up system and method in an off-grid state, wherein a BMS wake-up circuit and a main control board wake-up circuit are respectively connected to the BMS and the main control board of the energy storage system, which can be manually awakened by a manual starter and realize self-maintenance of wake-up by relying on its own signal output, and automatically power off and hibernate when the SOC of the energy storage system is too low, realizing intelligent power on and off and hibernation without the need for operation and maintenance personnel, avoiding the occurrence of battery undervoltage hibernation, and reducing the maintenance cost of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a flow system block diagram of an energy storage sleep and wake-up system in an off-grid state according to an embodiment of the present invention;

[0016] Figure 2 Schematic diagram of circuit connections of a B and MS wake-up circuit of an energy storage dormancy wake-up system in an off-grid state according to an embodiment of the present invention;

[0017] Figure 3 This is a circuit connection diagram of a main control board wake-up circuit of an energy storage dormant wake-up system in an off-grid state according to an embodiment of the present invention;

[0018] Figure 4 This is a circuit connection diagram of a clock wake-up circuit of an energy storage dormancy wake-up system in an off-grid state according to an embodiment of the present invention;

[0019] Figure 5 This is a schematic diagram of the steps of an energy storage dormancy awakening method in an off-grid state according to the present invention.

[0020] Description of labels:

[0021] 1. First manual starter; 2. Second manual starter; 3. BMS wake-up circuit; 4. Main control board wake-up circuit; 5. Clock wake-up circuit; 6. Independent power supply;

[0022] C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor;

[0023] D1, first diode; D2, second diode; D3, third diode; D4, fourth diode; D5, fifth diode;

[0024] Q1, first transistor; Q2, second transistor; Q3, third transistor; Q4, fourth transistor;

[0025] T1, first MOS tube; T2, second MOS tube; T3, third MOS tube;

[0026] R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; R8, eighth resistor; R9, ninth resistor; R10, tenth resistor; R11, eleventh resistor; R12, twelfth resistor; R13, thirteenth resistor; R14, fourteenth resistor;

[0027] U1, clock chip;

[0028] ZY1, passive crystal oscillator. DETAILED DESCRIPTION

[0029] To illustrate the technical content, achieved objectives and effects of the present invention in detail, the following description is given in conjunction with the embodiments and accompanying drawings.

[0030] Please refer to Figures 1 to 4 , an energy storage dormancy wake-up system in an off-grid state, comprising a first manual starter 1, a second manual starter 2, a BMS wake-up circuit 3, and a main control board wake-up circuit 4;

[0031] The BMS wake-up circuit 3 is connected to the power supply output terminal of the DCDC and the power supply input terminal of the BMS respectively. The BMS wake-up circuit 3 has two wake-up enable terminals, which are respectively connected to the first manual starting component 1 and the signal output terminal of the BMS;

[0032] The main control board wake-up circuit 4 is respectively connected to the power supply output end of the DCDC and the power supply input end of the main control board. The main control board wake-up circuit 4 has two wake-up enable ends, which are respectively connected to the second manual starting component 2 and the signal output end of the main control board;

[0033] The BMS wake-up circuit 3 is used to connect the power supply output end of the DCDC and the power supply input end of the BMS, the main control board wake-up circuit 4 is used to connect the power supply output end of the DCDC and the power supply input end of the main control board, and the first manual starting component 1 and the second manual starting component 2 are both used to output enable signals.

[0034] As can be seen from the above description, the beneficial effects of the present invention are as follows: the BMS wake-up circuit 3 and the main control board wake-up circuit 4 are respectively connected to the BMS and the main control board of the energy storage system, which can be manually awakened by a manual starter and realize self-awakening by relying on their own signal output. When the SOC of the energy storage system is too low, it automatically powers off and sleeps, realizing intelligent power-on and power-off and sleep without the need for operation and maintenance personnel, avoiding the occurrence of battery undervoltage sleep, and reducing the maintenance cost of the system.

[0035] Furthermore, it also includes a clock wake-up circuit 5 and an independent power supply 6;

[0036] The independent power supply 6 is connected to the power supply end of the clock wake-up circuit 5, and the clock wake-up circuit 5 is communicatively connected to the main control board;

[0037] The main control board wake-up circuit 4 and the BMS wake-up circuit 3 each have a third wake-up enable terminal;

[0038] The signal output terminal of the clock wake-up circuit 5 is connected to the third wake-up enable terminal of the main control board wake-up circuit 4 , and the third wake-up enable terminal of the BMS wake-up circuit 3 is connected to the signal output terminal of the main control board.

[0039] As can be seen from the above description, a clock wake-up circuit 5 is also provided, which is powered by an independent power supply 6. When the clock arrives, the clock wake-up circuit 5 can automatically wake up the main control board, and the main control board outputs an enable signal to wake up the BMS, realizing automatic power-on wake-up control, which is easy to use.

[0040] Furthermore, the BMS wake-up circuit 3 includes a first MOS transistor T1, a first transistor Q1, a second transistor Q2, a first capacitor C1, a first diode D1, a second diode D2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6;

[0041] The source of the first MOS transistor T1 is connected to the power supply output end of the DCDC and one end of the first resistor R1, the drain of the first MOS transistor T1 is connected to one end of the first capacitor C1 and the power supply input end of the BMS, and the gate of the first MOS transistor T1 is connected to the other end of the first resistor R1 and one end of the second resistor R2;

[0042] The other end of the second resistor R2 is simultaneously connected to the collector of the first transistor Q1 and the collector of the second transistor Q2. The base of the first transistor Q1 is simultaneously connected to one end of the third resistor R3 and one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to the cathode of the first diode D1. The base of the second transistor Q2 is simultaneously connected to one end of the fifth resistor R5 and one end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to the cathode of the second diode D2.

[0043] The anode of the first diode D1 and the anode of the second diode D2 are respectively connected to the first manual starting component 1 and the signal output end of the BMS, and the other end of the first capacitor C1, the emitter of the first transistor Q1, the other end of the third resistor R3, the emitter of the second transistor Q2, and the other end of the fifth resistor R5 are all grounded.

[0044] From the above description, it can be seen that the above is the specific composition of the BMS wake-up circuit 3, which relies on the switching characteristics of components such as MOS tubes and transistors to form a power-on and power-off control loop, and its operation is stable and easy to control.

[0045] Furthermore, the main control board wake-up circuit 4 includes a second MOS transistor T2, a third transistor Q3, a fourth transistor Q4, a second capacitor C2, a third diode D3, a fourth diode D4, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12;

[0046] The source of the second MOS transistor T2 is connected to the power supply output end of the DCDC and one end of the seventh resistor R7, the drain of the second MOS transistor T2 is connected to one end of the second capacitor C2 and the power supply input end of the main control board, and the gate of the second MOS transistor T2 is connected to the other end of the seventh resistor R7 and one end of the eighth resistor R8;

[0047] The other end of the eighth resistor R8 is connected to the collector of the third transistor Q3 and the collector of the fourth transistor Q4. The base of the third transistor Q3 is connected to one end of the ninth resistor R9 and one end of the tenth resistor R10. The other end of the tenth resistor R10 is connected to the cathode of the third diode D3. The base of the fourth transistor Q4 is connected to one end of the eleventh resistor R11 and one end of the twelfth resistor R12. The other end of the twelfth resistor R12 is connected to the cathode of the fourth diode D4.

[0048] The anode of the third diode D3 and the anode of the fourth diode D4 are respectively connected to the second manual starting component 2 and the signal output end of the main control board, and the other end of the second capacitor C2, the emitter of the third transistor Q3, the other end of the ninth resistor R9, the emitter of the fourth transistor Q4 and the other end of the eleventh resistor R11 are all grounded.

[0049] As can be seen from the above description, the above is the specific composition of the main control board wake-up circuit 4, which relies on the switching characteristics of components such as MOS tubes and transistors to form a power-on and power-off control loop, and its operation is stable and easy to control.

[0050] Furthermore, the clock wake-up circuit 5 includes a clock chip U1, a third MOS transistor T3, a thirteenth resistor R13, a fourteenth resistor R14, a third capacitor C3, a fourth capacitor C4 and a passive crystal oscillator ZY1;

[0051] The power supply end of the clock chip U1 is connected to the independent power supply 6, the passive input pin of the clock chip U1 is simultaneously connected to one end of the third capacitor C3 and the first end of the passive crystal oscillator ZY1, and the passive output pin of the clock chip U1 is simultaneously connected to one end of the fourth capacitor C4 and the second end of the passive crystal oscillator ZY1;

[0052] The clock chip U1 is communicatively connected to the main control board, the reset operation pin of the clock chip U1 is connected to the gate of the third MOS transistor T3 through the thirteenth resistor R13, the source of the third MOS transistor T3 is connected to the independent power supply 6 through the fourteenth resistor R14, and the drain of the third MOS transistor T3 is connected to the third wake-up enable terminal of the main control board wake-up circuit 4.

[0053] From the above description, it can be seen that the clock wake-up circuit 5 is mainly composed of the clock chip U1 and its peripheral circuits. The duration of the real-time clock can be set arbitrarily to meet the actual use requirements of the energy storage system, making the automatic power on and off and sleep control more flexible and intelligent.

[0054] Furthermore, the first manual starting element 1 and the second manual starting element 2 are both inching buttons.

[0055] From the above description, it can be seen that the inching button has a built-in reset function, which is simple to operate and easy to use.

[0056] Please refer to Figure 5 A method for waking up from energy storage dormancy in an off-grid state is applied to the above-mentioned off-grid energy storage dormancy waking up system, comprising the following steps:

[0057] S1, outputting an enable signal to the first wake-up enable terminal of the BMS wake-up circuit 3 through the first manual starting component 1, so that the BMS is awakened and outputs an enable signal to the second wake-up enable terminal of the BMS wake-up circuit 3;

[0058] S2, outputting an enable signal to the first wake-up enable terminal of the main control board wake-up circuit 4 through the second manual starting component 2, so that the main control board is awakened and outputs an enable signal to the second wake-up enable terminal of the main control board wake-up circuit 4;

[0059] S3. When the SOC of the energy storage system is too low, the BMS and the main control board both stop outputting enable signals.

[0060] As can be seen from the above description, the beneficial effects of the present invention are as follows: the BMS wake-up circuit 3 and the main control board wake-up circuit 4 are respectively connected to the BMS and the main control board of the energy storage system, which can be manually awakened by a manual starter and realize self-awakening by relying on their own signal output. When the SOC of the energy storage system is too low, it automatically powers off and sleeps, realizing intelligent power-on and power-off and sleep without the need for operation and maintenance personnel, avoiding the occurrence of battery undervoltage sleep, and reducing the maintenance cost of the system.

[0061] Furthermore, it is characterized by further comprising:

[0062] S4, when the energy storage system is operating normally, setting the real-time clock of the clock wake-up circuit 5 through the main control board;

[0063] S5. When the energy storage system is in a dormant state and the real-time clock arrives, the clock wake-up circuit 5 outputs an enable signal to the third wake-up enable terminal of the main control board wake-up circuit 4, and the main control board outputs an enable signal to the third wake-up enable terminal of the BMS wake-up circuit 3.

[0064] As can be seen from the above description, a clock wake-up circuit 5 is also provided, which is powered by an independent power supply 6. When the clock arrives, the clock wake-up circuit 5 can automatically wake up the main control board, and the main control board outputs an enable signal to wake up the BMS, realizing automatic power-on wake-up control, which is easy to use.

[0065] Furthermore, the step S3 further includes:

[0066] If the first manual starting element 1 continues to output for a predetermined time, the BMS stops outputting the enable signal;

[0067] If the second manual starting member 2 continues to output for a time period that reaches the preset time period, the main control board stops outputting the enable signal.

[0068] From the above description, it can be seen that the operation of power-down mode under the manual control system is added to improve the flexibility of use.

[0069] The present invention provides an off-grid energy storage dormancy wake-up system and method, which can be applied to scenarios where energy storage systems are powered on and off. Specific implementation methods are described below:

[0070] Please refer to Figures 1 to 3 , embodiment 1 of the present invention is:

[0071] An energy storage dormancy wake-up system in an off-grid state, such as Figure 1 As shown, it includes a first manual starter 1, a second manual starter 2, a BMS wake-up circuit 3, and a main control board wake-up circuit 4. The BMS wake-up circuit 3 is connected to the power output of the DC-DC converter and the power input of the BMS, and has two wake-up enable terminals, respectively connected to the first manual starter 1 and the signal output of the BMS. The main control board wake-up circuit 4 is connected to the power output of the DC-DC converter and the power input of the main control board, and has two wake-up enable terminals, respectively connected to the second manual starter 2 and the signal output of the main control board. The BMS wake-up circuit 3 is used to connect the power output of the DC-DC converter and the power input of the BMS, and the main control board wake-up circuit 4 is used to connect the power output of the DC-DC converter and the power input of the main control board. The first manual starter 1 and the second manual starter 2 are both used to output enable signals. The first manual starter 1 and the second manual starter 2 are both inching buttons.

[0072] In this embodiment, if Figure 1 As shown, it also includes a clock wake-up circuit 5 and an independent power supply 6; the independent power supply 6 is connected to the power supply end of the clock wake-up circuit 5, and the clock wake-up circuit 5 is communicatively connected to the main control board; the main control board wake-up circuit 4 and the BMS wake-up circuit 3 respectively have a third wake-up enable end; the signal output end of the clock wake-up circuit 5 is connected to the third wake-up enable end of the main control board wake-up circuit 4, and the third wake-up enable end of the BMS wake-up circuit 3 is connected to the signal output end of the main control board.

[0073] In this embodiment, if Figure 2As shown, the BMS wake-up circuit 3 includes a first MOS transistor T1, a first transistor Q1, a second transistor Q2, a first capacitor C1, a first diode D1, a second diode D2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6; the source of the first MOS transistor T1 is simultaneously connected to the power supply output end of the DCDC and one end of the first resistor R1, the drain of the first MOS transistor T1 is simultaneously connected to one end of the first capacitor C1 and the power supply input end of the BMS, the gate of the first MOS transistor T1 is simultaneously connected to the other end of the first resistor R1 and one end of the second resistor R2; the other end of the second resistor R2 is simultaneously connected to the collector of the first transistor Q1 The first transistor Q1 is connected to the collector of the second transistor Q2, the base of the first transistor Q1 is connected to one end of the third resistor R3 and one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to the cathode of the first diode D1, the base of the second transistor Q2 is connected to one end of the fifth resistor R5 and one end of the sixth resistor R6, the other end of the sixth resistor R6 is connected to the cathode of the second diode D2; the anode of the first diode D1 and the anode of the second diode D2 are respectively connected to the first manual starting component 1 and the signal output end of the BMS, the other end of the first capacitor C1, the emitter of the first transistor Q1, the other end of the third resistor R3, the emitter of the second transistor Q2 and the other end of the fifth resistor R5 are all grounded.

[0074] In this embodiment, if Figure 2 As shown, the anode of the first diode D1 and the anode of the second diode D2 serve as two wake-up enable terminals of the BMS wake-up circuit 3 respectively, and the third wake-up enable terminal is provided by the fifth diode D5, whose cathode is connected to the cathode of the first diode D1.

[0075] In this embodiment, if Figure 3As shown, the main control board wake-up circuit 4 includes a second MOS transistor T2, a third transistor Q3, a fourth transistor Q4, a second capacitor C2, a third diode D3, a fourth diode D4, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12; the source of the second MOS transistor T2 is simultaneously connected to the power supply output end of the DCDC and one end of the seventh resistor R7, the drain of the second MOS transistor T2 is simultaneously connected to one end of the second capacitor C2 and the power supply input end of the main control board, the gate of the second MOS transistor T2 is simultaneously connected to the other end of the seventh resistor R7 and one end of the eighth resistor R8; the other end of the eighth resistor R8 is simultaneously connected to the collector of the third transistor Q3 and the fourth The collector of the transistor Q4 is connected, the base of the third transistor Q3 is connected to one end of the ninth resistor R9 and one end of the tenth resistor R10, the other end of the tenth resistor R10 is connected to the cathode of the third diode D3, the base of the fourth transistor Q4 is connected to one end of the eleventh resistor R11 and one end of the twelfth resistor R12, the other end of the twelfth resistor R12 is connected to the cathode of the fourth diode D4; the anode of the third diode D3 and the anode of the fourth diode D4 are connected to the second manual starting component 2 and the signal output end of the main control board, respectively; the other end of the second capacitor C2, the emitter of the third transistor Q3, the other end of the ninth resistor R9, the emitter of the fourth transistor Q4, and the other end of the eleventh resistor R11 are all grounded.

[0076] In this embodiment, if Figure 3 As shown, the anode of the third diode D3 and the anode of the fourth diode D4 serve as two wake-up enable terminals of the main control board wake-up circuit 4 respectively, and the third wake-up enable terminal of the main control board wake-up circuit 4 is provided by a contact point drawn out from the cathode of the fourth diode D4.

[0077] Please refer to Figure 4 , the second embodiment of the present invention is:

[0078] An energy storage sleep and wake-up system in an off-grid state, based on the first embodiment, as Figure 4As shown, the clock wake-up circuit 5 includes a clock chip U1, a third MOS transistor T3, a thirteenth resistor R13, a fourteenth resistor R14, a third capacitor C3, a fourth capacitor C4, and a passive crystal oscillator ZY1. The power supply terminal of the clock chip U1 is connected to the independent power supply 6. The passive input pin of the clock chip U1 is simultaneously connected to one end of the third capacitor C3 and the first end of the passive crystal oscillator ZY1. The passive output pin of the clock chip U1 is simultaneously connected to one end of the fourth capacitor C4 and the second end of the passive crystal oscillator ZY1. The clock chip U1 is in communication with the main control board. The reset operation pin of the clock chip U1 is connected to the gate of the third MOS transistor T3 via the thirteenth resistor R13. The source of the third MOS transistor T3 is connected to the independent power supply 6 via the fourteenth resistor R14. The drain of the third MOS transistor T3 is connected to the third wake-up enable terminal of the main control board wake-up circuit 4. The independent power supply 6 can be a button battery.

[0079] Please refer to Figure 2 and Figure 3 as well as Figure 5 , the third embodiment of the present invention is:

[0080] A method for waking up from energy storage dormancy in an off-grid state, applied to an off-grid energy storage dormancy waking up system of embodiment 1 or 2, comprises the following steps:

[0081] S1, outputting an enable signal to the first wake-up enable terminal of the BMS wake-up circuit 3 through the first manual starting component 1, so that the BMS is awakened and outputs an enable signal to the second wake-up enable terminal of the BMS wake-up circuit 3;

[0082] S2, outputting an enable signal to the first wake-up enable terminal of the main control board wake-up circuit 4 through the second manual starting component 2, so that the main control board is awakened and outputs an enable signal to the second wake-up enable terminal of the main control board wake-up circuit 4;

[0083] In this embodiment, combined with Figure 2 and Figure 3 As shown, the first manual trigger 1 transmits a clock signal to ED_Ignition of the BMS wake-up circuit 3, causing the BMS to start operating and set PSU_Keep_alive high. At this point, even if an external user releases the first manual trigger 1, the BMS can still maintain power and operation. S3: When the energy storage system's SOC is too low, both the BMS and the main control board stop outputting enable signals. The operation of the main control board wake-up circuit 4 is similar and will not be further described.

[0084] In this embodiment, step S3 further includes:

[0085] If the first manual starting element 1 continues to output for a preset time, the BMS stops outputting the enable signal;

[0086] If the second manual starting member 2 continues to output for a predetermined time, the main control board stops outputting the enable signal.

[0087] In this embodiment, when the BMS detects that ED_Ignition has been set high for longer than a preset time or detects that the energy storage battery system SOC is too low, the BMS PSU_Keep_alive is set low to enter sleep mode. Even if the 24V power supply is still connected, the BMS consumes no power. The operation of the main control board wake-up circuit 4 is similar and will not be repeated here. The preset time range is 3-5 seconds, preferably 4 seconds.

[0088] S4. When the energy storage system is operating normally, the real-time clock of the clock wake-up circuit 5 is set by the main control board;

[0089] In this embodiment, the real-time clock serves as a time signal. The clock chip U1 can communicate with the main control board through SPI to set the timeout overflow time. Specifically, the current time can be compared with the local light time, and the timing time can be written into the real-time clock before entering power-off sleep mode.

[0090] S5. When the energy storage system is in sleep mode and the real-time clock arrives, the clock wake-up circuit 5 outputs an enable signal to the third wake-up enable terminal of the main control board wake-up circuit 4, and the main control board outputs an enable signal to the third wake-up enable terminal of the BMS wake-up circuit 3.

[0091] In this embodiment, with the clock wake-up circuit 5 being put into use, the main control board and the BMS have both manual and automatic power-on and power-off control processes.

[0092] In this embodiment, if Figure 3 As shown, the real-time clock can also be designed to output a high-level 24V+ from the PV on the PCS photovoltaic side. The PV needs to be designed with a low-voltage prohibition output wake-up signal to ensure the effectiveness of photovoltaic charging. When the 24V+ signal is connected to the fourth wake-up enable terminal (ED_KL15) of the main control board, the battery system can be automatically woken up for charging when photovoltaic power is present.

[0093] In summary, the present invention provides an energy storage hibernation and wake-up system and method in an off-grid state. The BMS wake-up circuit and the main control board wake-up circuit are respectively connected to the BMS and the main control board of the energy storage system. Manual wake-up can be performed through a manual starter and the wake-up self-maintenance is achieved by relying on its own signal output. When the SOC of the energy storage system is too low, it automatically powers off and goes into hibernation. A clock wake-up point circuit is also provided, which has automatic power-on and power-off and hibernation control and adjustable control time, realizing intelligent power-on and power-off and hibernation without the need for operation and maintenance personnel, avoiding the occurrence of battery undervoltage hibernation, and reducing the maintenance cost of the system.

[0094] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's description and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An energy storage dormancy wake-up system in an off-grid state, characterized in that: It includes a first manual starter, a second manual starter, a BMS wake-up circuit, and a main control board wake-up circuit; The BMS wake-up circuit is connected to the power supply output terminal of the DCDC and the power supply input terminal of the BMS respectively. The BMS wake-up circuit has two wake-up enable terminals, which are respectively connected to the first manual starter and the signal output terminal of the BMS; The main control board wake-up circuit is respectively connected to the power supply output terminal of the DCDC and the power supply input terminal of the main control board. The main control board wake-up circuit has two wake-up enable terminals, which are respectively connected to the second manual starting component and the signal output terminal of the main control board; The BMS wake-up circuit is used to connect the power supply output end of the DCDC and the power supply input end of the BMS, the main control board wake-up circuit is used to connect the power supply output end of the DCDC and the power supply input end of the main control board, and the first manual starting component and the second manual starting component are both used to output an enable signal; It also includes a clock wake-up circuit and an independent power supply; The independent power supply is connected to the power supply end of the clock wake-up circuit, and the clock wake-up circuit is communicatively connected to the main control board; The main control board wake-up circuit and the BMS wake-up circuit each have a third wake-up enable terminal; The signal output terminal of the clock wake-up circuit is connected to the third wake-up enable terminal of the main control board wake-up circuit, and the third wake-up enable terminal of the BMS wake-up circuit is connected to the signal output terminal of the main control board; The main control board wake-up circuit is used to perform the following steps: S1. Outputting an enable signal to a first wake-up enable terminal of a BMS wake-up circuit through a first manual starting component, so that the BMS is awakened and outputs an enable signal to a second wake-up enable terminal of the BMS wake-up circuit; S2, outputting an enable signal to a first wake-up enable terminal of a main control board wake-up circuit through a second manual starting component, so that the main control board is awakened and outputs an enable signal to a second wake-up enable terminal of the main control board wake-up circuit; S3. When the SOC of the energy storage sleep wake-up system is too low, the BMS and the main control board both stop outputting enable signals; S4, when the energy storage dormancy wake-up system is operating normally, the real-time clock of the clock wake-up circuit is set by the main control board; S5. When the energy storage dormancy wake-up system is in a dormant state and the real-time clock arrives, the clock wake-up circuit outputs an enable signal to the third wake-up enable terminal of the main control board wake-up circuit, and the main control board outputs an enable signal to the third wake-up enable terminal of the BMS wake-up circuit.

2. The off-grid energy storage dormancy and wake-up system according to claim 1, characterized in that: The BMS wake-up circuit includes a first MOS transistor, a first transistor, a second transistor, a first capacitor, a first diode, a second diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor; The source of the first MOS transistor is connected to the power supply output terminal of the DCDC and one end of the first resistor at the same time, the drain of the first MOS transistor is connected to one end of the first capacitor and the power supply input terminal of the BMS at the same time, and the gate of the first MOS transistor is connected to the other end of the first resistor and one end of the second resistor at the same time; The other end of the second resistor is connected to the collector of the first transistor and the collector of the second transistor at the same time, the base of the first transistor is connected to one end of the third resistor and one end of the fourth resistor at the same time, the other end of the fourth resistor is connected to the cathode of the first diode, the base of the second transistor is connected to one end of the fifth resistor and one end of the sixth resistor at the same time, and the other end of the sixth resistor is connected to the cathode of the second diode; The anode of the first diode and the anode of the second diode are respectively connected to the first manual starting component and the signal output end of the BMS, and the other end of the first capacitor, the emitter of the first transistor, the other end of the third resistor, the emitter of the second transistor and the other end of the fifth resistor are all grounded.

3. The off-grid energy storage dormancy and wake-up system according to claim 1, characterized in that: The main control board wake-up circuit includes a second MOS transistor, a third transistor, a fourth transistor, a second capacitor, a third diode, a fourth diode, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor and a twelfth resistor; The source of the second MOS transistor is connected to the power supply output end of the DCDC and one end of the seventh resistor at the same time, the drain of the second MOS transistor is connected to one end of the second capacitor and the power supply input end of the main control board at the same time, and the gate of the second MOS transistor is connected to the other end of the seventh resistor and one end of the eighth resistor at the same time; The other end of the eighth resistor is connected to the collector of the third transistor and the collector of the fourth transistor simultaneously, the base of the third transistor is connected to one end of the ninth resistor and one end of the tenth resistor simultaneously, the other end of the tenth resistor is connected to the cathode of the third diode, the base of the fourth transistor is connected to one end of the eleventh resistor and one end of the twelfth resistor simultaneously, and the other end of the twelfth resistor is connected to the cathode of the fourth diode; The anode of the third diode and the anode of the fourth diode are respectively connected to the second manual starting component and the signal output end of the main control board, and the other end of the second capacitor, the emitter of the third transistor, the other end of the ninth resistor, the emitter of the fourth transistor and the other end of the eleventh resistor are all grounded.

4. The off-grid energy storage dormancy and wake-up system according to claim 1, characterized in that: The clock wake-up circuit includes a clock chip, a third MOS tube, a thirteenth resistor, a fourteenth resistor, a third capacitor, a fourth capacitor and a passive crystal oscillator; The power supply end of the clock chip is connected to the independent power supply, the passive input pin of the clock chip is simultaneously connected to one end of the third capacitor and the first end of the passive crystal oscillator, and the passive output pin of the clock chip is simultaneously connected to one end of the fourth capacitor and the second end of the passive crystal oscillator; The clock chip is communicatively connected to the main control board, the reset operation pin of the clock chip is connected to the gate of the third MOS tube through the thirteenth resistor, the source of the third MOS tube is connected to the independent power supply through the fourteenth resistor, and the drain of the third MOS tube is connected to the third wake-up enable terminal of the main control board wake-up circuit.

5. The off-grid energy storage dormancy and wake-up system according to claim 1, characterized in that: The first manual starting member and the second manual starting member are both inching buttons.

6. The off-grid energy storage dormancy and wake-up system according to claim 1, characterized in that: The step S3 further includes: If the first manual starting element continues to output for a predetermined time, the BMS stops outputting the enable signal; If the second manual starting element continues to output for a time period that reaches the preset time period, the main control board stops outputting the enable signal.

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