Methods for forming semiconductor structures and semiconductor structures

Abstract

This disclosure provides a method for forming a semiconductor structure and the semiconductor structure itself. The method includes: providing an initial structure, including a substrate and a dielectric layer; forming a conductive trench, the bottom surface of which is a first distance from a second side surface of the substrate; forming a conductive via extending from the top surface of the dielectric layer to the second side surface of the substrate; forming a conductive pillar filling the conductive via; forming an inductor structure filling the conductive trench, wherein the projection of the inductor structure onto the substrate is configured as a spiral structure surrounding the center of the inductor, with the projection of the conductive pillar onto the substrate as the inductor center; and forming an inductor lead-out structure. By forming an inductor structure surrounding the conductive pillar, this disclosure allows the inductor structure to sense the current flowing through the conductive pillar and generate inductance, eliminating the need to integrate passive devices into the semiconductor structure and further reducing the size of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure and a semiconductor structure. Background Technology

[0002] Integrated circuit (IC) packaging technology is a technique that interconnects multiple chips through through silicon vias (TSVs). This involves forming vertically interconnected TSV structures on multiple chips and then using a redistribution layer (RDL) to achieve electrical interconnection between the different chips.

[0003] Existing through-silicon via (TSV) technology typically integrates passive devices (IPDs) on semiconductor substrates. IPDs combine resistors, capacitors, and inductors into a single chip. However, as the integration density of integrated circuits continues to increase and the size of integrated circuits decreases, the feature size of IPDs also decreases. This reduction in size leads to a decrease in the quality factor of the inductors within IPDs, making it difficult for the inductance generated by IPDs to meet the application requirements of integrated circuits. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a method for forming a semiconductor structure and the semiconductor structure itself.

[0006] A first aspect of this disclosure provides a method for forming a semiconductor structure, the method comprising:

[0007] An initial structure is provided, the initial structure including a substrate and a dielectric layer disposed on the substrate, the dielectric layer being disposed on a first side of the substrate, and the bottom surface of the dielectric layer being connected to the first side surface of the substrate;

[0008] A conductive trench is formed, the conductive trench extending from the top of the dielectric layer to the second side of the substrate, the conductive trench exposing a portion of the dielectric layer and a portion of the substrate, and the bottom surface of the conductive trench being a first distance from the second side of the substrate;

[0009] A conductive hole is formed, the conductive hole extending from the top surface of the dielectric layer to the second side surface of the substrate;

[0010] A conductive pillar is formed, and the conductive pillar fills the conductive hole;

[0011] An inductor structure is formed, the inductor structure filling the conductive trench, wherein the projection of the inductor structure on the substrate is configured as a spiral structure around the inductor center with the projection of the conductive pillar on the substrate as the inductor center;

[0012] An inductor lead-out structure is formed, which covers the conductive pillars and the inductor structure exposed on the top surface of the dielectric layer.

[0013] According to some embodiments of this disclosure, forming a conductive trench includes:

[0014] A first mask layer is formed on the top surface of the dielectric layer, the first mask layer including a first pattern, the first pattern exposing a portion of the top surface of the dielectric layer;

[0015] The dielectric layer and a portion of the substrate exposed by the first pattern are removed to form the conductive trench.

[0016] According to some embodiments of this disclosure, forming a conductive hole includes:

[0017] The first mask layer further includes a second pattern that exposes a portion of the top surface of the dielectric layer, wherein the projection of the first pattern onto the substrate is configured as a spiral pattern with the projection of the second pattern onto the substrate as the spiral center and surrounding the spiral center;

[0018] Remove the dielectric layer and a portion of the substrate exposed by the second pattern to form an initial conductive via.

[0019] The substrate is removed according to the initial conductive hole to form the conductive hole.

[0020] According to some embodiments of this disclosure, the step of removing a portion of the substrate according to the initial conductive hole to form the conductive hole includes:

[0021] A shielding layer is formed, which covers the conductive trench and the top surface of the dielectric layer;

[0022] The substrate exposed by the initial conductive hole is removed to form the conductive hole.

[0023] According to some embodiments of this disclosure, forming a conductive hole includes:

[0024] A second mask layer is formed on the second side of the substrate. The second mask layer includes a third pattern that exposes a portion of the second side of the substrate. The projection of the first pattern on the substrate is configured as a spiral pattern with the projection of the third pattern on the substrate as the spiral center and arranged around the spiral center.

[0025] Remove the substrate and dielectric layer exposed by the third pattern to form a conductive hole.

[0026] According to some embodiments of this disclosure, the spiral pattern is configured to include multiple ring patterns, which are arranged sequentially outward around the spiral center.

[0027] According to some embodiments of this disclosure, the spiral structure includes a starting end near the center of the inductor and a terminating end away from the center of the inductor, and the spiral structure is a ring structure formed by extending radially outward from the starting end around the center of the inductor to the terminating end.

[0028] According to some embodiments of this disclosure, the formation of the inductor lead structure includes:

[0029] A first metal pad is formed, the first metal pad is disposed on the top surface of the dielectric layer, and the first metal pad covers the conductive pillar exposed on the top surface of the dielectric layer;

[0030] A second metal pad is formed, the second metal pad is disposed on the top surface of the dielectric layer, and the second metal pad covers the inductor structure exposed on the top surface of the dielectric layer;

[0031] A first inductor lead is formed, which covers a portion of the top surface of the second metal pad;

[0032] A second inductor lead is formed, which covers a portion of the top surface of the second metal pad.

[0033] According to some embodiments of this disclosure, the projection of the first inductor lead on the substrate is located at the starting end of the spiral structure;

[0034] The projection of the second inductor lead onto the substrate is located at the terminating end of the spiral structure.

[0035] A second aspect of this disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0036] Substrate, the substrate including a first side and a second side;

[0037] A dielectric layer is disposed on a first side of the substrate, and the bottom surface of the dielectric layer is connected to the first side surface of the substrate;

[0038] A conductive trench extends from the top of the dielectric layer to a second side surface of the substrate, the conductive trench exposing a portion of the dielectric layer and a portion of the substrate, and the bottom surface of the conductive trench is a first distance from the second side surface of the substrate.

[0039] A conductive via extending from the top surface of the dielectric layer to a second side surface of the substrate;

[0040] Conductive pillars, wherein the conductive pillars are filled with conductive holes;

[0041] An inductor structure that fills the conductive trench, wherein the projection of the inductor structure on the substrate is configured as a spiral structure with the projection of the conductive pillar on the substrate as the inductor center and surrounding the inductor center;

[0042] An inductor lead-out structure that covers the conductive pillars and the inductor structure exposed on the top surface of the dielectric layer.

[0043] According to some embodiments of this disclosure, the spiral structure includes a plurality of spiral portions connected sequentially in a clockwise or counterclockwise direction, and the distance between the plurality of spiral portions and the center of the inductor gradually increases according to the connection order.

[0044] According to some embodiments of this disclosure, the spiral structure includes a starting end near the center of the inductor and a terminating end away from the center of the inductor, the spiral structure radially outward from the starting end around the center of the inductor and extending to the terminating end.

[0045] According to some embodiments of this disclosure, the distance between the starting end of the spiral structure and the center of the inductor is a first distance;

[0046] According to the connection sequence, the distance between the plurality of spiral portions and the center of the inductor increases in a first distance step.

[0047] According to some embodiments of this disclosure, the inductor lead-out structure further includes:

[0048] A first metal pad is disposed on the top surface of the dielectric layer, and the first metal pad covers the conductive pillar exposed on the top surface of the dielectric layer;

[0049] A second metal pad is disposed on the top surface of the dielectric layer, and the second metal pad covers the inductor structure exposed on the top surface of the dielectric layer.

[0050] The first inductor lead is disposed on the second metal pad;

[0051] The second inductor lead is disposed on the second metal pad.

[0052] According to some embodiments of this disclosure, the projection of the first inductor lead on the substrate is located at the starting end of the spiral structure;

[0053] The projection of the second inductor lead onto the substrate is located at the terminating end of the spiral structure.

[0054] In the semiconductor structure formation method and semiconductor structure provided in this disclosure, by forming an inductor structure surrounding a conductive pillar and an inductor lead-out structure connected to the inductor structure, when current flows through the conductive pillar, the inductor structure senses the current in the conductive pillar and generates inductance. There is no need to integrate passive devices in the semiconductor structure, which can further reduce the size of the semiconductor structure.

[0055] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0056] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0057] Figure 1 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment.

[0058] Figure 2 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment.

[0059] Figure 3 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment.

[0060] Figure 4 This is a flowchart illustrating the formation of an inductor lead structure in a method for forming a semiconductor structure according to an exemplary embodiment.

[0061] Figure 5 This is a schematic diagram illustrating the formation of a first mask layer on an initial structure in a method for forming a semiconductor structure according to an exemplary embodiment;

[0062] Figure 6This is a schematic projection of the first and second patterns formed in a semiconductor structure formation method according to an exemplary embodiment, showing the formation of the first and second patterns on a substrate.

[0063] Figure 7 This is a schematic diagram illustrating the formation of conductive trenches and initial conductive holes in a method for forming a semiconductor structure according to an exemplary embodiment;

[0064] Figure 8 This is a schematic diagram of a shielding layer in a method for forming a semiconductor structure according to an exemplary embodiment;

[0065] Figure 9 This is a schematic diagram illustrating the formation of a conductive hole in a method for forming a semiconductor structure according to an exemplary embodiment;

[0066] Figure 10 This is a schematic diagram illustrating the formation of a first mask layer on an initial structure in a method for forming a semiconductor structure according to an exemplary embodiment;

[0067] Figure 11 This is a schematic diagram illustrating the formation of conductive trenches in a method for forming a semiconductor structure according to an exemplary embodiment;

[0068] Figure 12 This is a schematic diagram illustrating the formation of a second mask layer on an initial structure in a method for forming a semiconductor structure according to an exemplary embodiment;

[0069] Figure 13 This is a schematic projection of the first and third patterns formed in a semiconductor structure formation method according to an exemplary embodiment, showing the formation of these patterns on a substrate.

[0070] Figure 14 This is a schematic diagram illustrating the formation of a conductive hole in a method for forming a semiconductor structure according to an exemplary embodiment;

[0071] Figure 15 This is a schematic diagram illustrating the formation of a first barrier layer and a second barrier layer in a method for forming a semiconductor structure according to an exemplary embodiment;

[0072] Figure 16 This is a schematic diagram illustrating the formation of conductive pillars and inductor structures in a method for forming a semiconductor structure according to an exemplary embodiment;

[0073] Figure 17 This is a schematic projection of conductive pillars and inductor structures formed on a substrate in a method for forming a semiconductor structure according to an exemplary embodiment.

[0074] Figure 18This is a schematic diagram illustrating the formation of a first metal pad and a second metal pad in a method for forming a semiconductor structure according to an exemplary embodiment;

[0075] Figure 19 This is a schematic diagram illustrating the formation of a first inductor lead and a second inductor lead in a method for forming a semiconductor structure according to an exemplary embodiment;

[0076] Figure 20 This is a schematic diagram illustrating the formation of a redistribution layer in a method for forming a semiconductor structure according to an exemplary embodiment.

[0077] Figure label:

[0078] 110. Initial structure; 110. Substrate; 120. Dielectric layer; 130. Isolation layer; 140. Conductive trench; 150. Conductive via; 151. Initial conductive via; 160. First mask layer; 161a. First pattern; 162a. Second pattern; 170. Masking layer; 180. Second mask layer; 181a. Third pattern;

[0079] 210, Conductive post; 211, First shielding layer; 212, First conductive layer; 220, Inductor structure; 221, Second shielding layer; 222, Second conductive layer; 220a, Helical structure; 2200a, Helical portion; 2201, Starting end of helical structure; 2202, Terminating end of helical structure;

[0080] 300. Inductor lead-out structure; 310. First metal pad; 320. Second metal pad; 331. First inductor lead-out section; 332. Second inductor lead-out section;

[0081] 400. Redistribution layer;

[0082] L1, first spacing; L2, first distance. Detailed Implementation

[0083] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0084] This disclosure provides a method for forming a semiconductor structure in exemplary embodiments, such as... Figure 1 As shown, Figure 1A flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 5-20 The diagram below illustrates the various stages of a semiconductor structure formation process. Figures 5-20 The methods for forming semiconductor structures are introduced.

[0085] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0086] like Figure 1 As shown, an exemplary embodiment of this disclosure provides a method for forming a semiconductor structure, comprising the following steps:

[0087] Step S110: Provide an initial structure, the initial structure including a substrate and a dielectric layer disposed on the substrate, the dielectric layer being disposed on a first side of the substrate, and the bottom surface of the dielectric layer being connected to the first side surface of the substrate.

[0088] like Figure 5 As shown, substrate 110 includes a semiconductor material, and the semiconductor material layer can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carb compounds. For example, substrate 110 can be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0089] The dielectric layer 120 may include a dielectric material. For example, the dielectric layer 120 may include silicon oxide.

[0090] In this embodiment, an isolation layer 130 may also be provided between the substrate 110 and the dielectric layer 120. The isolation layer 130 is used to prevent direct contact between the substrate 110 and the dielectric layer 120. The isolation layer 130 may include an insulating material; for example, the isolation layer 130 may include insulating materials such as silicon nitride and silicon oxide.

[0091] Step S120: Form a conductive trench. The conductive trench extends from the top of the dielectric layer to the second side of the substrate. The conductive trench exposes part of the dielectric layer and part of the substrate, and the bottom surface of the conductive trench is a first distance from the second side of the substrate.

[0092] like Figure 7 As shown, refer to Figure 5The conductive trench 140 can be formed by etching away part of the dielectric layer 120 and part of the substrate 110 using a dry etching or wet etching process. The conductive trench 140 extends from the top of the dielectric layer 120 to the second side surface of the substrate 110, and the bottom surface of the conductive trench 140 is a first distance L1 from the second side surface of the substrate 110.

[0093] For example, the initial structure 100 has a thickness of 3 μm to 10 μm, the dielectric layer 120 has a thickness of 0.05 μm to 0.3 μm, the conductive trench 140 has a depth of 1 μm to 10 μm, and the first distance L1 between the bottom surface of the conductive trench 140 and the second side surface of the substrate 110 is greater than 1 μm.

[0094] Step S130: Form a conductive hole extending from the top surface of the dielectric layer to the second side surface of the substrate.

[0095] like Figure 9 As shown, refer to Figure 7 The conductive via 150 can be formed by etching away a portion of the dielectric layer 120 and a portion of the substrate 110, and the conductive via 150 penetrates the initial structure 100. In this embodiment, the conductive via 150 is disposed in the middle of the conductive trench 140 and is surrounded by the conductive trench 140. The projection of the conductive trench 140 onto the substrate 110 is a spiral pattern centered on the projection of the conductive via 150 onto the substrate 110.

[0096] Step S140: Form conductive pillars, which fill conductive holes.

[0097] Forming the conductive pillar 210 includes: such as Figure 15 As shown, refer to Figure 9 Atomic layer deposition (ALD) can be used to deposit tantalum (Ta) or tantalum compounds to form a first barrier layer 211, which covers the sidewalls of the conductive via 150. In this embodiment, the material of the first barrier layer 211 is tantalum (Ta). Figure 16 As shown, refer to Figure 15 Conductive metal is deposited through an electroplating process, and the conductive metal fills the conductive holes 150 to form a first conductive layer 212. The first barrier layer 211 and the first conductive layer 212 form a conductive pillar 210. In this embodiment, the conductive metal can be copper or a copper compound.

[0098] Step S150: Form an inductor structure, the inductor structure fills conductive trenches, wherein the projection of the inductor structure on the substrate is set as a spiral structure with the projection of the conductive pillar on the substrate as the inductor center and surrounding the inductor center.

[0099] like Figure 15 , Figure 16As shown, the process of forming the inductor structure 220 is roughly the same as the process of forming the conductive pillar 210. Tantalum or tantalum compounds are deposited to form a second barrier layer 221 covering the conductive trench 140. Conductive metal is then deposited through an electroplating process to fill the conductive trench 140, forming a second conductive layer 222. The second barrier layer 221 and the second conductive layer 222 together form the inductor structure 220. In this embodiment, the conductive metal can be copper or copper compounds. Figure 17 As shown, in this embodiment, the projection of the inductor structure 220 on the substrate 110 is set as a spiral structure 220a surrounding the inductor center with the projection of the conductive pillar 210 on the substrate 110 as the inductor center.

[0100] Step S160: Form an inductor lead-out structure, which covers the conductive pillars and inductor structure exposed on the top surface of the dielectric layer.

[0101] Reference Figure 18 , Figure 19 As shown, the inductor lead structure 300 includes at least a first inductor lead 331 and a second inductor lead 332 connected to the inductor structure 220. The inductor structure 220 is connected to an external terminal through the first inductor lead 331 and the second inductor lead 332, so that when current flows through the conductive post 210, the inductor structure 220 is affected by the induced current and can generate inductance.

[0102] The semiconductor structure formation method of this embodiment forms an embedded inductor device within the semiconductor structure by forming an inductor structure surrounding a conductive pillar and an inductor lead-out structure connected to the inductor structure. The conductive pillar serves as the magnetic core, and the inductor structure acts as a winding coil surrounding the conductive pillar. In this embodiment, the conductive pillar of the semiconductor structure not only serves as a silicon through-hole structure for interconnection but also as the magnetic core of the inductor device. When the conductive pillar forms an electrical connection with other interconnect structures, current flows through it, and the inductor structure senses this current to generate inductance. The semiconductor structure formed in this embodiment can generate inductance when energized, meeting the inductance requirements without integrating passive devices within the semiconductor structure, thus further reducing the size of the semiconductor structure.

[0103] This disclosure provides a method for forming a semiconductor structure in exemplary embodiments, such as... Figure 2 As shown, Figure 2 A flowchart of a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure is shown.

[0104] like Figure 2 As shown, an exemplary embodiment of this disclosure provides a method for forming a semiconductor structure, comprising the following steps:

[0105] Step S210: Provide an initial structure, the initial structure including a substrate and a dielectric layer disposed on the substrate, the dielectric layer being disposed on a first side of the substrate, and the bottom surface of the dielectric layer being connected to the first side surface of the substrate.

[0106] Step S220: A first mask layer is formed on the top surface of the dielectric layer. The first mask layer includes a first pattern and a second pattern.

[0107] like Figure 5 As shown, the first mask layer 160 includes both a first pattern 161a and a second pattern 162a. The first pattern 161a exposes a portion of the top surface of the dielectric layer 120, and the second pattern 162a exposes a portion of the top surface of the dielectric layer 120. Wherein, as... Figure 6 As shown, the projection of the first pattern 161a onto the substrate 110 is configured as a spiral pattern with the projection of the second pattern 162a onto the substrate 110 as the spiral center, and arranged around the spiral center. In this embodiment, the spiral pattern formed by the projection of the first pattern 161a is configured to include multiple ring patterns, which are arranged sequentially outward around the spiral center.

[0108] Step S230: Remove a portion of the initial structure according to the first pattern and the second pattern to form conductive trenches and initial conductive holes.

[0109] like Figure 7 As shown, refer to Figure 5 , Figure 6 The dielectric layer 120 and substrate 110 exposed by the first pattern 161a and the second pattern 162a are removed by dry or wet etching processes to a predetermined depth, forming conductive trenches 140 and initial conductive holes 151. The conductive trenches 140 are arranged around the initial conductive holes 151 with the initial conductive holes 151 as the center, and the bottom surfaces of the conductive trenches 140 and the initial conductive holes 151 are a first distance L1 from the second side surface of the substrate 110.

[0110] Step S240: Remove the substrate exposed by the initial conductive hole to form a conductive hole.

[0111] like Figure 8 As shown, refer to Figure 7 A shielding layer 170 is formed, which covers the top surface of the conductive trench 140 and the dielectric layer 120. In this embodiment, the material of the shielding layer 170 is a photoresist. Then, the substrate 110 exposed by the initial conductive hole 151 is removed by a photolithography process to form a conductive hole 150 that penetrates the initial structure 100.

[0112] Step S250: Form conductive pillars, which fill conductive holes.

[0113] Step S260: Form an inductor structure, the inductor structure fills conductive trenches, wherein the projection of the inductor structure on the substrate is set as a spiral structure with the projection of the conductive pillar on the substrate as the inductor center and surrounding the inductor center.

[0114] Step S270: Form an inductor lead-out structure, which covers the conductive pillars and inductor structure exposed on the top surface of the dielectric layer.

[0115] The method of forming step S210 in this embodiment is the same as the implementation method of step S110 in the above embodiment. The implementation methods of steps S250-S270 are the same as those of steps S140-S160 in the above embodiment, and will not be repeated here.

[0116] The semiconductor structure formed in this embodiment, such as Figure 16 As shown, refer to Figure 17 The inductor structure 220 is disposed around the conductive post 210. The projection of the inductor structure 220 onto the substrate 110 is configured such that the projection of the conductive post 210 onto the substrate 110 is the inductor center, and a spiral structure 220a surrounds the inductor center. In this embodiment, the spiral structure 220a is a spiral ring structure that surrounds the inductor center and moves away from the inductor center in the radial direction.

[0117] like Figure 17 As shown, the spiral structure 220a formed by the projection of the inductor structure 220 onto the substrate 110 includes a starting end 2201 near the center of the inductor and a terminating end 2202 away from the center of the inductor. The spiral structure 220a is a spiral ring structure extending radially outward from the starting end 2201 around the center of the inductor to the terminating end 2202. Figure 18 As shown, refer to Figure 19 The inductor structure 220 surrounds the conductive post 210 multiple times. The inductor structure can be connected to an external terminal through the inductor lead-out structure 300. When the conductive post 210 is energized, the inductor structure 220 is affected by the current flowing in the conductive post 210 and generates inductance.

[0118] In this embodiment, when forming the semiconductor structure, a first pattern and a second pattern are patterned on a first mask layer. The projection of the first pattern onto the substrate is set as a spiral pattern with the projection of the second pattern onto the substrate as the spiral center and arranged around the spiral center. This only requires patterning on the first mask layer. Figure 1 Furthermore, both the first and second patterns are designed on the top surface of the medium layer, which reduces the difficulty of design and ensures high design accuracy.

[0119] This disclosure provides a method for forming a semiconductor structure in exemplary embodiments, such as... Figure 3 As shown, Figure 3A flowchart of a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure is shown.

[0120] like Figure 3 As shown, an exemplary embodiment of this disclosure provides a method for forming a semiconductor structure, comprising the following steps:

[0121] Step S310: Provide an initial structure, the initial structure including a substrate and a dielectric layer disposed on the substrate, the dielectric layer being disposed on a first side of the substrate, and the bottom surface of the dielectric layer being connected to the first side surface of the substrate.

[0122] Step S320: A first mask layer is formed on the top surface of the dielectric layer, the first mask layer including a first pattern.

[0123] like Figure 10 As shown, a first mask layer 160 is formed on the initial structure 100. The first mask layer 160 covers the top surface of the dielectric layer 120. The first mask layer 160 includes a first pattern 161a, as shown in the figure. Figure 13 The projection of the first pattern 161a onto the substrate 110 is a spiral pattern.

[0124] Step S330: Remove part of the initial structure according to the first pattern to form a conductive trench.

[0125] like Figure 11 As shown, refer to Figure 10 A conductive trench 140 is formed in the initial structure 100, and the bottom surface of the conductive trench 140 is a first distance L1 from the second side surface of the substrate. The implementation method for forming the conductive trench 140 is the same as the implementation method for forming the conductive trench 140 in step S230 of the above embodiments.

[0126] Step S340: A second mask layer is formed on the second side of the substrate. The second mask layer includes a third pattern that exposes a portion of the second side of the substrate.

[0127] like Figure 12 As shown, refer to Figure 11 A second mask layer 180 is formed, covering the second side surface of the substrate 100. The second mask layer 180 is patterned according to the projection of the conductive trench 140 onto the substrate 110, forming a third pattern 181a on the second mask layer 180. The third pattern 181a exposes a portion of the second side surface of the substrate 110. In this embodiment, the projection image of the conductive trench 140 onto the substrate 110 is obtained by illumination, and the third pattern 181a is patterned according to the projection of the conductive trench 140 onto the substrate 110, as shown below. Figure 13 As shown, the projection of the third pattern 181a onto the substrate 110 is set as the spiral center of the projection of the conductive trench 140 onto the substrate 110. Figure 13 As shown, the spiral pattern formed by the projection of the first pattern 161a onto the substrate 110 is configured to include multiple ring patterns, which are arranged sequentially outward around the spiral center.

[0128] Step S350: Remove the substrate and dielectric layer exposed by the third pattern to form a conductive hole.

[0129] like Figure 14 As shown, refer to Figure 12 , Figure 13 The substrate 110 exposed by the third pattern 181a is removed by dry etching or wet etching process, and the third pattern 181a is transferred to the dielectric layer 120. Then, the dielectric layer 120 is etched according to the third pattern 181a to form a conductive hole 150 penetrating the initial structure 110. The conductive hole 150 is located at the center of the conductive trench 140, and the conductive trench 140 spirals around the conductive hole 150 with the conductive hole 150 as the center and in a direction away from the conductive hole 150.

[0130] Step S360: Form conductive pillars, which fill conductive holes.

[0131] Step S370: Form an inductor structure, the inductor structure fills conductive trenches, wherein the projection of the inductor structure on the substrate is set as a spiral structure with the projection of the conductive pillar on the substrate as the inductor center and surrounding the inductor center.

[0132] Step S380: Form an inductor lead-out structure, which covers the conductive pillars and inductor structure exposed on the top surface of the dielectric layer.

[0133] The method of forming step S310 in this embodiment is the same as the implementation method of step S210 in the above embodiment. The implementation methods of steps S360-S380 are the same as those of steps S250-S270 in the above embodiment, and will not be repeated here.

[0134] In this embodiment, when forming a semiconductor structure, a first pattern is patterned on a first mask layer, and an initial structure is etched from the top of the dielectric layer to the bottom of the substrate according to the first pattern to form a conductive trench. Then, a second mask layer is formed on the second side of the substrate, and a third pattern is patterned on the second mask layer according to the projection pattern of the conductive trench on the substrate. A conductive hole is formed according to the third pattern. There is no need to form a masking layer to block the conductive trench, which reduces the steps of forming and removing the masking layer and further simplifies the semiconductor structure formation process.

[0135] According to an exemplary embodiment of this disclosure, this embodiment is a further explanation of step S380 in the above embodiment.

[0136] like Figure 4 As shown, the inductor lead-out structure includes:

[0137] Step S381: Form a first metal pad, the first metal pad is disposed on the top surface of the dielectric layer, and the first metal pad covers the conductive pillars exposed on the top surface of the dielectric layer.

[0138] Step S382: Form a second metal pad, which is disposed on the top surface of the dielectric layer and covers the inductor structure exposed on the top surface of the dielectric layer.

[0139] Steps S381 and S382 can be performed simultaneously. A dielectric material is deposited on the top surface of the dielectric layer 120 to form an auxiliary layer. The auxiliary layer is patterned using photolithography and dry or wet etching processes to form an auxiliary pattern. The projection of the auxiliary pattern onto the substrate 110 coincides with the projections of the conductive pillars 210 and the inductor structure 220 onto the substrate 110. Conductive metal is deposited to fill the auxiliary pattern, forming the first metal pad 310 and the second metal pad 320. Then, the auxiliary layer is removed. Figure 18 As shown, the first metal pad 310 covers the conductive pillar 210 exposed on the top surface of the dielectric layer 120, and the second metal pad 320 covers the inductor structure 220 exposed on the top surface of the dielectric layer 120. In other embodiments of this application, the first metal pad 310 and the second metal pad 320 may also be formed separately.

[0140] Step S383: Form a first inductor lead-out portion, which covers part of the top surface of the second metal pad.

[0141] Step S384: Form a second inductor lead-out portion, which covers part of the top surface of the second metal pad.

[0142] Steps S383 and S384 can be performed simultaneously, such as... Figure 19 As shown, a first inductor lead 331 and a second inductor lead 332 are formed on the top surface of the second metal pad 320 by tin plating. In this embodiment, refer to... Figure 17 The projection of the first inductor lead 331 onto the substrate 110 is located at the starting end 2201 of the spiral structure 220a; the projection of the second inductor lead 332 onto the substrate 110 is located at the ending end 2202 of the spiral structure 220a. In other embodiments of this application, the first inductor lead 331 and the second inductor lead 332 may also be formed separately.

[0143] In this embodiment, the first inductor lead is located at the end of the inductor structure closest to the conductive post, and the second inductor lead is located at the end of the inductor structure furthest from the conductive post. The first and second inductor leads are arranged opposite to each other. The semiconductor structure formed in this embodiment can be connected to an external terminal through the first and second inductor leads to form a complete inductor device.

[0144] According to an exemplary embodiment of this disclosure, most of the content of this embodiment is the same as that of the above embodiments, except that, as Figure 3 As shown, the method for forming the semiconductor structure in this embodiment further includes:

[0145] Step S390: Form a redistribution layer, the redistribution layer is disposed on the second side of the substrate, and the redistribution layer covers the conductive pillars exposed on the second side of the substrate.

[0146] In this embodiment, forming the redistribution layer 400 includes: forming an insulating layer on the second side of the substrate 110; patterning the insulating layer using an exposure process, a development process, and a dry etching or wet etching process; forming a redistribution pattern in the insulating layer, wherein the redistribution pattern exposes a portion of the second side of the substrate 110; and forming the redistribution layer 400 according to the redistribution pattern, such as... Figure 20 As shown, the redistribution layer 400 covers the conductive pillars 210 exposed on the second side of the substrate 110.

[0147] In this embodiment, a redistribution layer electrically connected to the conductive pillars is formed on the second side of the substrate of the semiconductor structure. The position of the interconnection contacts of the semiconductor structure is changed by the redistribution layer, so that the semiconductor structure can be adapted to different packaging forms.

[0148] This disclosure provides a semiconductor structure in exemplary embodiments, such as... Figure 20 As shown, refer to Figure 14The semiconductor structure includes: a substrate 110, a dielectric layer 120 connected to the substrate 110, a conductive trench 140 disposed in the dielectric layer 120 and the substrate 110, and a conductive via 150. The substrate 110 includes a first side and a second side. The dielectric layer 120 is disposed on the first side of the substrate 110, and the bottom surface of the dielectric layer 120 is connected to the first side surface of the substrate 110. The conductive trench 140 extends from the top surface of the dielectric layer 120 to the second side surface of the substrate 110, exposing a portion of the dielectric layer 120 and a portion of the substrate 110. The bottom surface of the conductive trench 140 is a first distance L1 from the second side surface of the substrate 110. The conductive via 150 extends from the top surface of the dielectric layer 120 to the second side surface of the substrate 110. The semiconductor structure also includes a conductive pillar 210 filling the conductive via 150, an inductor structure 220 filling the conductive trench 140, and an inductor lead-out structure 300 covering the conductive pillar 210 and the inductor structure 220 exposed on the top surface of the dielectric layer 120. Wherein, as... Figure 17 As shown, the projection of the inductor structure 220 on the substrate 110 is configured as a spiral structure 220a surrounding the inductor center with the projection of the conductive pillar 210 on the substrate 110 as the inductor center.

[0149] In this embodiment of the semiconductor structure, an inductor structure 220 is provided around the conductive pillar 210 in a spiral manner, and an inductor lead-out structure 300 connected to the inductor structure 220 is also provided on the top surface of the dielectric layer 120. The conductive pillar 210, the inductor structure 220 and the inductor lead-out structure 300 together form an inductor device with the conductive pillar 210 as the magnetic core and the inductor structure 220 as the winding coil surrounding the conductive pillar 210.

[0150] In this embodiment, the conductive pillar 210 in the semiconductor structure serves not only as a silicon through-hole structure for interconnection but also as the magnetic core of an inductor. When the conductive pillar 210 forms an electrical connection with other interconnect structures, current flows through it, and the inductor structure 220 senses this current to generate inductance. This embodiment eliminates the need for passively integrated inductors in the semiconductor structure, further reducing its size.

[0151] According to an exemplary embodiment of this disclosure, most of the content of this embodiment is the same as that of the above embodiments, except that, as Figure 17 As shown, the spiral structure 220a includes a plurality of spiral portions 2200a connected sequentially in a clockwise or counterclockwise direction, and the distance between the plurality of spiral portions 2200a and the center of the inductor gradually increases according to the connection order.

[0152] The spiral structure 2200a is a ring structure that surrounds the center of the inductor in a predetermined shape, either clockwise or counterclockwise. Exemplarily, the spiral structure 2200a can be rectangular or circular around the center of the inductor in a clockwise or counterclockwise direction. In this embodiment, the spiral structure 2200a is a ring structure that is rectangular around the center of the inductor in a counterclockwise direction. The inductor structure 220 includes a multi-turn structure surrounding the outer periphery of the conductive post 210. When current flows through the conductive post 210, each turn of the inductor structure 220 around the conductive post 210 corresponds to one turn of a coil around the conductive post 210. The inductor structure 220 and the conductive post 210 form an inductor device with the conductive post 210 as the magnetic core and the inductor structure 220 as an inductor coil surrounding the magnetic core. The inductor structure 220 generates inductance due to the induced current in the magnetic core.

[0153] According to an exemplary embodiment of this disclosure, most of the content of this embodiment is the same as that of the above embodiments, except that, as Figure 17 As shown, the spiral structure 220a includes a starting end 2201 near the center of the inductor and a ending end 2202 away from the center of the inductor. The spiral structure 220a is configured to radially outward from the starting end 2201 around the center of the inductor and extend to the ending end.

[0154] In this embodiment, the distance between the starting end 2201 of the spiral structure 220a and the center of the inductor is a first distance L2; according to the connection sequence, the distance between the multiple spiral parts 220a and the center of the inductor increases stepwise with the first distance L2.

[0155] In this embodiment, the first distance L2 is 0.2um to 1um. For example, the first distance L2 can be 0.3um, 0.4um, 0.5um, 0.6um, 0.7um, 0.8um or 0.9um.

[0156] In this embodiment, the spacing between the coils of the inductor structure 220 and the minimum distance between the inductor structure 220 and the conductive post 210 are set to 0.2um to 1um, which is smaller than the spacing rules for the current design of silicon through-hole structures, so that when the conductive post 210 is energized, the inductor structure 220 generates a larger inductance under the influence of the current of the conductive post 210.

[0157] According to an exemplary embodiment of this disclosure, most of the content of this embodiment is the same as that of the above embodiments, except that, as Figure 20 As shown, refer to Figure 18 , Figure 19The inductor lead structure 300 includes: a first metal pad 310 and a second metal pad 320 disposed on the top surface of the dielectric layer 120, and a first inductor lead 331 and a second inductor lead 332 disposed on the second metal pad 320. The first metal pad 310 covers the conductive pillars 210 exposed on the top surface of the dielectric layer 120, and the second metal pad 320 covers the inductor structure 220 exposed on the top surface of the dielectric layer 120.

[0158] In this embodiment, the projection of the first inductor lead-out portion 331 on the substrate 110 is located within the projection range of the starting end 2201 of the spiral structure 220a on the substrate 110; the projection of the second inductor lead-out portion 332 on the substrate is located within the projection range of the ending end of the spiral structure 220a on the substrate 110.

[0159] The semiconductor structure provided in this application uses a conductive post 210 as a magnetic core and an inductor structure 220 spirally surrounding the outer periphery of the conductive post. When the conductive post 210 is energized, the inductor structure 220 can generate inductance by inducing current in the conductive post 210. The semiconductor structure of this embodiment does not need to integrate passive devices to provide inductance, which can further reduce the size of the semiconductor structure.

[0160] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0161] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0162] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0163] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0164] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0165] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0166] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method for forming the semiconductor structure includes: An initial structure is provided, the initial structure including a substrate and a dielectric layer disposed on the substrate, the dielectric layer being disposed on a first side of the substrate, and the bottom surface of the dielectric layer being connected to the first side surface of the substrate; A conductive trench is formed, the conductive trench extending from the top of the dielectric layer to the second side of the substrate, the conductive trench exposing a portion of the dielectric layer and a portion of the substrate, and the bottom surface of the conductive trench being a first distance from the second side of the substrate; A conductive hole is formed, the conductive hole extending from the top surface of the dielectric layer to the second side surface of the substrate; A conductive pillar is formed, and the conductive pillar fills the conductive hole; An inductor structure is formed, the inductor structure filling the conductive trench, wherein the projection of the inductor structure on the substrate is configured as a spiral structure around the inductor center with the projection of the conductive pillar on the substrate as the inductor center; An inductor lead-out structure is formed, which covers the conductive pillars and the inductor structure exposed on the top surface of the dielectric layer; The conductive pillars are used for interconnecting silicon through-hole structures, and the minimum distance between the inductor structure and the conductive pillars is less than the spacing designed for the silicon through-hole structure.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The formation of the conductive trench includes: A first mask layer is formed on the top surface of the dielectric layer, the first mask layer including a first pattern, the first pattern exposing a portion of the top surface of the dielectric layer; The dielectric layer and a portion of the substrate exposed by the first pattern are removed to form the conductive trench.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The formation of the conductive hole includes: The first mask layer further includes a second pattern that exposes a portion of the top surface of the dielectric layer, wherein the projection of the first pattern onto the substrate is configured as a spiral pattern with the projection of the second pattern onto the substrate as the spiral center and surrounding the spiral center; Remove the dielectric layer and a portion of the substrate exposed by the second pattern to form an initial conductive via. The substrate is removed according to the initial conductive hole to form the conductive hole.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, The step of removing a portion of the substrate according to the initial conductive hole to form the conductive hole includes: forming a shielding layer that covers the conductive trench and the top surface of the dielectric layer; and removing the substrate exposed by the initial conductive hole to form the conductive hole.

5. The method for forming a semiconductor structure according to claim 2, characterized in that, The formation of the conductive hole includes: A second mask layer is formed on the second side of the substrate. The second mask layer includes a third pattern that exposes a portion of the second side of the substrate. The projection of the first pattern onto the substrate is configured as a spiral pattern with the projection of the third pattern onto the substrate as the spiral center and surrounding the spiral center. Remove the substrate and dielectric layer exposed by the third pattern to form a conductive hole.

6. The method for forming a semiconductor structure according to claim 4 or 5, characterized in that, The spiral pattern is configured to include multiple ring patterns, which are arranged sequentially outwards around the center of the spiral.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, The spiral structure includes a starting end near the center of the inductor and a terminating end away from the center of the inductor. The spiral structure is a ring structure that extends radially outward from the starting end around the center of the inductor to the terminating end.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, The inductor lead-out structure includes: A first metal pad is formed, the first metal pad is disposed on the top surface of the dielectric layer, and the first metal pad covers the conductive pillar exposed on the top surface of the dielectric layer; A second metal pad is formed, the second metal pad is disposed on the top surface of the dielectric layer, and the second metal pad covers the inductor structure exposed on the top surface of the dielectric layer; A first inductor lead is formed, which covers a portion of the top surface of the second metal pad; A second inductor lead is formed, which covers a portion of the top surface of the second metal pad.

9. The method for forming a semiconductor structure according to claim 8, characterized in that, The projection of the first inductor lead onto the substrate is located at the starting end of the spiral structure; The projection of the second inductor lead onto the substrate is located at the terminating end of the spiral structure.

10. A semiconductor structure, characterized in that, The semiconductor structure includes: Substrate, the substrate including a first side and a second side; A dielectric layer is disposed on a first side of the substrate, and the bottom surface of the dielectric layer is connected to the first side surface of the substrate; A conductive trench extends from the top of the dielectric layer to a second side surface of the substrate, the conductive trench exposing a portion of the dielectric layer and a portion of the substrate, and the bottom surface of the conductive trench is a first distance from the second side surface of the substrate; A conductive via extending from the top surface of the dielectric layer to a second side surface of the substrate; a conductive pillar filling the conductive via; An inductor structure that fills the conductive trench, wherein the projection of the inductor structure on the substrate is configured as a spiral structure with the projection of the conductive pillar on the substrate as the inductor center and surrounding the inductor center; An inductor lead-out structure, the inductor lead-out structure covering the conductive pillars and the inductor structure exposed on the top surface of the dielectric layer; The conductive pillars are used for interconnecting silicon through-hole structures, and the minimum distance between the inductor structure and the conductive pillars is less than the spacing designed for the silicon through-hole structure.

11. The semiconductor structure according to claim 10, characterized in that, The spiral structure includes multiple spiral sections connected sequentially in a clockwise or counterclockwise direction, and the distance between the multiple spiral sections and the center of the inductor gradually increases according to the connection order.

12. The semiconductor structure according to claim 11, characterized in that, The spiral structure includes a starting end near the center of the inductor and a terminating end away from the center of the inductor. The spiral structure extends radially outward from the starting end around the center of the inductor and to the terminating end.

13. The semiconductor structure according to claim 12, characterized in that, The distance between the starting end of the spiral structure and the center of the inductor is a first distance; According to the connection sequence, the distance between the plurality of spiral portions and the center of the inductor increases in a first distance step.

14. The semiconductor structure according to claim 12, characterized in that, The inductor lead-out structure includes: A first metal pad is disposed on the top surface of the dielectric layer, and the first metal pad covers the conductive pillar exposed on the top surface of the dielectric layer; A second metal pad is disposed on the top surface of the dielectric layer, and the second metal pad covers the inductor structure exposed on the top surface of the dielectric layer. The first inductor lead is disposed on the second metal pad; The second inductor lead is disposed on the second metal pad.

15. The semiconductor structure according to claim 14, characterized in that, The projection of the first inductor lead onto the substrate is located at the starting end of the spiral structure; The projection of the second inductor lead onto the substrate is located at the terminating end of the spiral structure.

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