Semiconductor device and power conversion device

Abstract

A semiconductor device is provided that reduces the number of connected low-voltage elements in a cascode-type high-voltage element formed by connecting multiple low-voltage elements in series, while being able to form a high-voltage element with a desired withstand voltage without being limited by the withstand voltage of the gate oxide film of the low-voltage element. In a semiconductor device formed by connecting a first semiconductor element and one or more second semiconductor elements in series, the first semiconductor element and the second semiconductor element each have a control signal output terminal between the source and drain terminals or between the emitter and collector terminals, and the gate terminal of the second semiconductor element is connected to the control signal output terminal of the first or second semiconductor element connected in series adjacent to the source or emitter side of the second semiconductor element.

Description

Technical Field

[0001] The present invention relates to the structure of a semiconductor device, and more particularly to a technique effectively applicable to a cascode-type high-voltage device constructed by connecting a plurality of low-voltage devices in series. Background Art

[0002] In the development of power semiconductor devices such as power transistors and power diodes, a key challenge is to manufacture devices that have high withstand voltage, low on-resistance, and minimal switching loss.

[0003] Power transistors are typically arranged between a body region and a drain region and have a drift region that is doped at a lower concentration than the drain region. The on-resistance of conventional power transistors depends on the length of the drift region in the direction of current flow and the doping concentration of the drift region. Shortening the drift region or increasing its doping concentration reduces the on-resistance.

[0004] However, when the length of the drift region is shortened or the doping concentration of the drift region is increased, there is a problem that the withstand voltage of the device is reduced.

[0005] As a method for reducing the on-resistance of a power transistor with a predetermined withstand voltage, it is well known to provide a technology of providing a complementarily doped compensation region in the drift region, or to provide a field plate that is dielectrically insulated from the drift region, for example, connected to the gate or source terminal of the transistor, in the drift region.

[0006] In these types of power transistors, the compensation region, or field plate, partially compensates for the dopant charge in the drift region when the device is in the off state. This allows for higher doping concentrations in the drift region, reducing on-resistance without reducing the withstand voltage. However, these devices tend to increase their output capacitance.

[0007] As background technology in this technical field, there is a technology such as Patent Document 1. Patent Document 1 discloses a "semiconductor element that increases withstand voltage and reduces output capacitance by autonomously controlling a plurality of power transistors using a cascode connection."

[0008] The technology of Patent Document 1 not only has advantages in terms of power transistor performance, such as improved withstand voltage, reduced on-resistance, and reduced switching loss, but also has the advantage of ease of design, such as the ability to vary the withstand voltage by varying the number of cascode connection stages.

[0009] Prior art literature

[0010] Patent Document 1: U.S. Patent Application Publication No. 2012 / 0175635 Summary of the Invention

[0011] However, in the technology disclosed in the above-mentioned patent document 1, since a common source and common gate connection is used to connect the gate electrode to the source electrode of the next level, the withstand voltage of the power transistor after the second level is limited by the withstand voltage of the gate oxide film, and the withstand voltage is usually limited to about 20V.

[0012] To achieve a high withstand voltage, the number of cascode connected stages needs to be increased. However, as the number of stages increases, the number of contacts connecting power transistors increases, which increases parasitic resistance and reduces gate reliability.

[0013] For example, if the gate of even one of the power transistors connected in series is damaged, all the power transistors upstream of the power transistor with the damaged gate become uncontrollable. Therefore, the probability of failure increases as the number of series stages increases.

[0014] Therefore, in order to achieve both high breakdown voltage and gate reliability, it is important to be able to freely design the number of series-connected power transistors of the second and subsequent stages for a certain target breakdown voltage.

[0015] That is, a semiconductor device is required in which the withstand voltage of the power transistors in the second and subsequent stages is not limited by the withstand voltage of the gate oxide film.

[0016] Therefore, the object of the present invention is to provide a semiconductor device and a power conversion device using the semiconductor device that can form a high-voltage element with a desired withstand voltage without being limited by the withstand voltage of the gate oxide film of the low-voltage element in a cascode type high-voltage element formed by connecting multiple low-voltage elements in series, while reducing the number of connected low-voltage elements.

[0017] In order to solve the above-mentioned problems, the present invention is a semiconductor device formed by connecting a first semiconductor element and one or more second semiconductor elements in series, characterized in that the first semiconductor element and the second semiconductor element have a control signal output terminal between the source terminal and the drain terminal or between the emitter terminal and the collector terminal, and the gate terminal of the second semiconductor element is connected to the control signal output terminal of the first semiconductor element or the second semiconductor element connected in series adjacent to the source or emitter side of the second semiconductor element.

[0018] According to the present invention, it is possible to realize a semiconductor device in which a high-voltage element of the cascode type is formed by connecting a plurality of low-voltage elements in series, while reducing the number of connected low-voltage elements and being able to form a high-voltage element with a desired withstand voltage without being limited by the withstand voltage of the gate oxide film of the low-voltage element.

[0019] Other problems, structures, and effects than those described above will become apparent from the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1A It is a diagram showing the cross-sectional structure of the semiconductor device according to the first embodiment of the present invention.

[0021] Figure 1B This is a diagram showing a connection structure between a control signal output electrode of a first-stage MOSFET and a gate electrode of a second-stage MOSFET.

[0022] Figure 1C This is a circuit diagram of a low-voltage element constituting the semiconductor device according to the first embodiment of the present invention.

[0023] Figure 2 This is a circuit diagram showing the structure of a semiconductor device according to the first embodiment of the present invention.

[0024] Figure 3A It is a diagram showing simulation calculation results of voltages between terminals according to the first embodiment of the present invention.

[0025] Figure 3B 1 is a diagram showing simulation calculation results of the potential distribution in the cross section of the semiconductor device according to the first embodiment of the present invention.

[0026] Figure 3C 1 is a diagram showing simulation calculation results of the potential distribution in the cross section of the semiconductor device according to the first embodiment of the present invention.

[0027] Figure 4A It shows Figure 1C FIG. 1 is a diagram of a modified example of .

[0028] Figure 4B It shows Figure 2 FIG. 1 is a diagram of a modified example of .

[0029] Figure 5 This is a circuit diagram showing the structure of a semiconductor device according to a second embodiment of the present invention.

[0030] Figure 6 This is a circuit diagram showing the structure of a semiconductor device according to a third embodiment of the present invention. DETAILED DESCRIPTION

[0031] Hereinafter, embodiments of the present invention will be described using the accompanying drawings. In the drawings, the same components are denoted by the same reference numerals, and detailed descriptions of the overlapping components will be omitted.

[0032] Example 1

[0033] Reference Figures 1A to 4B, a semiconductor device according to a first embodiment of the present invention is described. Figures 1A to 3C In the example of using a horizontal MOSFET as a low voltage element constituting a semiconductor device, Figure 4A as well as Figure 4B , an example using an IGBT (Insulated Gate Bipolar Transistor) is shown as a modified example thereof.

[0034] Figure 1A 1 is a diagram showing the cross-sectional structure of the semiconductor device of this embodiment. Figure 1A As shown, an n-type semiconductor substrate 3 serving as a drift region is formed on a supporting substrate 1 via an embedded oxide film 2, a p-type base region 4 is selectively formed in a portion of the n-type semiconductor substrate 3, an n-type source region 5 is formed in a portion of a surface layer of the p-type base region 4, and a p-type contact region 6 is formed adjacent to the n-type source region 5.

[0035] An n-type drain region 7 is selectively formed in a portion of the surface layer of the n-type semiconductor substrate 3 where the p-type base region 4 is not formed. Furthermore, a gate electrode 10 connected to a gate terminal (not shown) is provided on the surface of a channel region 8 in the surface layer of the p-type base region 4 via a gate oxide film 9.

[0036] A source electrode 11 is provided, contacting both the surfaces of the n-type source region 5 and the p-type contact region 6. A drain electrode 12 is provided on the surface of the n-type drain region 7 and connected to the source and drain terminals (not shown). A control signal output electrode 13 is formed on a portion of the surface of the n-type semiconductor substrate (drift region) 3 between the p-type base region 4 and the n-type drain region 7 and connected to a control signal output terminal (not shown). Furthermore, a portion of the surface of the n-type semiconductor substrate 3 is covered with a dielectric 14 for electrical insulation.

[0037] The semiconductor device of this embodiment is as follows Figure 1A As shown, a control signal output electrode 13 is provided in a portion of the surface of the n-type semiconductor substrate (drift region) 3 between the p-type base region 4 and the n-type drain region 7. The potential of the control signal output terminal can be adjusted within the range from the potential of the source terminal to the potential of the drain terminal by utilizing the position at which the control signal output electrode 13 is provided.

[0038] Figure 1B This is a diagram showing a connection structure between a control signal output electrode of a first-stage MOSFET and a gate electrode of a second-stage MOSFET in the semiconductor device of this embodiment.

[0039] The semiconductor device of this embodiment is as follows Figure 1B As shown, the n-type semiconductor substrate (drift region) 3 embedded in the oxide film 2 is separated into a first-stage MOSFET region (on the left side of the isolation region 15) and a second-stage MOSFET region (on the right side of the isolation region 15) by the isolation region 15. Furthermore, the control signal output electrode 13 of the first-stage MOSFET and the gate electrode 10 of the second-stage MOSFET are electrically connected.

[0040] Figure 1C This is a circuit diagram of low-voltage elements constituting the semiconductor device of this embodiment. Figure 1C The source terminal 16, drain terminal 17, gate terminal 18, and control signal output terminal 19 are equivalent to Figure 1A The source electrode 11, the drain electrode 12, the gate electrode 10, and the control signal output electrode 13 are respectively connected to the source terminal, the drain terminal, the gate terminal, and the control signal output terminal.

[0041] like Figure 1C As shown, the low voltage element (horizontal MOSFET) constituting the semiconductor device of this embodiment is characterized in that a control signal output terminal 19 is added compared to the circuit structure of a conventional horizontal MOSFET.

[0042] Figure 2 1 is a circuit diagram showing the structure of the semiconductor device of this embodiment. By connecting the drain terminals 17 and source terminals 16 of the horizontal MOSFETs 21, 22, and 23 provided with the control signal output electrode 13, the three horizontal MOSFETs 21, 22, and 23 are connected in series. Figure 2 For simplicity, only the horizontal MOSFETs 21 , 22 , and 23 are shown in FIG. 1 , but the number of the horizontal MOSFETs connected in series is not limited thereto, and it is apparent that the number of series connections can be arbitrarily changed.

[0043] In addition, the second and subsequent stages of the series connection ( Figure 2 The horizontal MOSFETs 22 and 23) are depletion-type MOSFETs whose gate voltage threshold is a negative voltage, but the first stage ( Figure 2 The horizontal MOSFET 21) is not necessarily a depletion type, but can also be an enhancement type MOSFET with a positive gate voltage threshold.

[0044] The gate terminal 18 and source terminal 16 of the horizontal MOSFET 21 are connected to a gate drive circuit (not shown). In addition, the gate terminals 18 of the second and subsequent horizontal MOSFETs 22 and 23 connected in series are connected to the control signal output terminal 19 of the horizontal MOSFET connected to the source side of the horizontal MOSFET.

[0045] Next, the operation of the semiconductor device of this embodiment will be described. For example, Figure 2 The three horizontal MOSFETs connected in series are connected to the power supply via a load. When the horizontal MOSFET 21 changes from the off state to the on state through the gate drive circuit, the voltage from the source terminal 16 to the drain terminal 17 of the horizontal MOSFET 21 and the voltage from the control signal output terminal 19 to the drain terminal 17 (the voltage based on the control signal output terminal 19) will decrease.

[0046] Since the voltage from the control signal output terminal 19 to the drain terminal 17 of the horizontal MOSFET 21 is equal to the voltage from the gate terminal 18 to the source terminal 16 of the horizontal MOSFET 22 (the voltage with respect to the gate terminal 18), the voltage from the source terminal 16 to the gate terminal 18 of the horizontal MOSFET 22 (the voltage with respect to the source terminal 16) rises, and when the negative gate threshold voltage is exceeded, the horizontal MOSFET 22 becomes conductive, and the voltage from the source terminal 16 to the drain terminal 17 of the horizontal MOSFET 22 and the voltage from the control signal output terminal 19 to the drain terminal 17 decrease.

[0047] Figure 3A The relationship between the voltage between the source terminal 16 and the drain terminal 17 and the voltage between the source terminal 16 and the control signal output terminal 19 obtained by simulation is shown. Figure 3A The horizontal axis represents the source-drain voltage Vds, and the vertical axis represents the drain (D) and control signal output (CSO) voltages with respect to the source.

[0048] The voltage from the drain terminal 17 to the control signal output terminal 19 of the horizontal MOSFET 21 is applied from the source terminal 16 to the gate terminal 18 as the gate voltage Vgs of the subsequent horizontal MOSFET 22 .

[0049] like Figure 3A As shown, in the horizontal MOSFET 21, in the region where the voltage Vds from the source terminal 16 to the drain terminal 17 is relatively small, the voltage of the drain (D) is roughly consistent with the voltage of the control signal output (CSO), and the voltage from the drain terminal 17 to the control signal output terminal 19 (the gate voltage Vgs applied to the subsequent horizontal MOSFET 22) is very small. However, when the voltage Vds from the source terminal 16 to the drain terminal 17 increases to a certain extent, the absolute value of the difference between the voltage of the drain (D) and the voltage of the control signal output (CSO) increases, and the sign of the voltage (Vgs) from the drain terminal 17 to the control signal output terminal 19 becomes negative and the absolute value increases. This is because, in Figure 1AIn the embodiment, if the voltage between the source electrode 11 and the drain electrode 12 does not increase to a certain extent, the depletion layer will not extend to the position of the control signal output electrode 13 .

[0050] As an example, in Figure 3B The figure shows the potential distribution in the horizontal MOSFET when the voltage from the source to the drain of the horizontal MOSFET with a withstand voltage of 600V is 200V. Figure 3C : shows the potential distribution in the horizontal MOSFET when the voltage from source to drain is 400V.

[0051] exist Figure 3B In the case of , the depletion layer does not extend to the control signal output (CSO), and the control signal output (CSO) and the drain (D) are at approximately the same potential. Figure 3C In the circuit, since the depletion layer extends to the control signal output (CSO), a potential difference is generated between the control signal output (CSO) and the drain (D), turning off the gate of the subsequent lateral MOSFET.

[0052] From the above, it can be seen that the absolute value of the voltage from the drain of the previous stage to the control signal output applied as the gate voltage of the subsequent stage becomes smaller than the absolute value of the voltage from the source to the drain of the previous stage and the subsequent stage (equal to the absolute value of the gate voltage of the subsequent stage in the case of a general cascode connection in which the gate of the subsequent stage is connected to the source of the previous stage). Therefore, compared with the case of a general cascode connection, the voltage stress applied to the gate oxide film of the horizontal MOSFET of the subsequent stage can be reduced.

[0053] As described above, when the horizontal MOSFET 21 is switched from the on state to the off state by the gate drive circuit, the voltage between the source terminal 16 and the drain terminal 17 of the horizontal MOSFET 21 and the voltage between the control signal output terminal 19 and the drain terminal 17 increase.

[0054] Therefore, the voltage from the source terminal 16 to the gate terminal 18 of the horizontal MOSFET 22 decreases, and when it is lower than the negative gate threshold voltage, the horizontal MOSFET 22 becomes cut off, and the voltage from the source terminal 16 to the drain terminal 17 of the horizontal MOSFET 22 and the voltage from the control signal output terminal 19 to the drain terminal 17 will increase.

[0055] The above-mentioned operation is carried out in a chain from the front-stage lateral MOSFET to the rear-stage lateral MOSFET. Therefore, if the horizontal MOSFET 21 is turned off, all the horizontal MOSFETs after the second stage connected in series will be turned off, which can prevent the application of voltage. In addition, the horizontal MOSFET of the first stage is the horizontal MOSFET arranged at the front stage. Figure 2In FIG, the horizontal MOSFET 21 is the first stage, the horizontal MOSFET 22 is the second stage, and the horizontal MOSFET 23 is the third stage.

[0056] Conversely, when the horizontal MOSFET 21 is turned on, all the horizontal MOSFETs 22 and 23 connected in series in the second and subsequent stages are turned on, and current can flow through the load.

[0057] In addition, a load is connected in parallel to the above-mentioned horizontal MOSFETs connected in series. When the current flowing in the load is caused to flow back from the source side to the drain side, the potential of the source becomes higher than the potential of the drain. Therefore, all the horizontal MOSFETs after the second stage connected in series become conductive and can flow back through the channel region 8.

[0058] In addition, regarding the horizontal MOSFET 21, when the gate is in the on state, a return current can flow through the channel region 8 in the same way as the horizontal MOSFET connected in series, but when the gate is in the off state, a return current can also flow through the built-in diode formed by the p-type contact region 6, the p-type base region 4 and the n-type semiconductor substrate 3.

[0059] As described above, the plurality of lateral MOSFETs connected in series can be controlled to be turned on and off by a single gate, and thus can be handled in the same manner as a single power transistor in a conventional power electronic device circuit.

[0060] Modification

[0061] use Figure 4A as well as Figure 4B A modification of the semiconductor device of the embodiment described above will be described. Figure 4A 、 Figure 4B They are Figure 1C 、 Figure 2 The above description uses a horizontal MOSFET as an example, but a HEMT (High Electron Mobility Transistor) using materials such as gallium nitride (GaN) may also be used, in which an IGBT and a diode are connected in reverse to a series-connected low-voltage element.

[0062] Figure 4A FIG. 1 is a circuit diagram of a low-voltage element constituting a semiconductor device according to a modified example. Figure 4A As shown, the low-voltage element (lateral IGBT) constituting the semiconductor device of the modification is characterized in that a control signal output terminal 19 is added compared to the circuit structure of the conventional lateral IGBT.

[0063] Figure 4B: is a circuit diagram showing the structure of a semiconductor device according to a modified example. Figure 2 The difference is that the power transistor of the first stage is not the horizontal MOSFET 21 but a horizontal IGBT 41 having a control signal output terminal 19 , and the characteristic is that a diode 42 is connected in antiparallel to the horizontal IGBT 41 .

[0064] exist Figure 4B In the structure, the lateral IGBT 41 is different from the lateral MOSFET 21 and does not conduct in the reverse direction, so a diode 42 is provided for backflow.

[0065] Although not shown in the figure, when HEMT using materials such as gallium nitride (GaN) is applied, it is possible to utilize Figure 2 The same circuit structure operates through synchronous rectification. When synchronous rectification is not used, the return current operation is required. Figure 4B Similarly, a diode is connected in antiparallel to the transistor of the first stage.

[0066] As described above, the semiconductor device of this embodiment is a semiconductor device formed by connecting a first semiconductor element (horizontal MOSFET21, horizontal IGBT41) and one or more second semiconductor elements (horizontal MOSFET22, 23) in series, and the first semiconductor element (horizontal MOSFET21, horizontal IGBT41) and the second semiconductor element (horizontal MOSFET22, 23) have a control signal output terminal 19 between the source terminal 16 and the drain terminal 17 or between the emitter terminal 24 and the collector terminal 25, and the gate terminal 18 of the second semiconductor element (horizontal MOSFET22, 23) is connected to the control signal output terminal 19 of the first semiconductor element (horizontal MOSFET21, horizontal IGBT41) or the second semiconductor element (horizontal MOSFET22, 23) connected in series adjacent to the source or emitter side of the second semiconductor element (horizontal MOSFET22, 23).

[0067] In addition, the gate terminal 18 and the source terminal 16 of the first semiconductor element (horizontal MOSFET21, horizontal IGBT41) are connected to the gate drive circuit. According to the drive signal from the gate drive circuit to the gate terminal 18 of the first semiconductor element (horizontal MOSFET21, horizontal IGBT41), the on / off control of all the semiconductor elements of the first semiconductor element (horizontal MOSFET21, horizontal IGBT41) and the second semiconductor element (horizontal MOSFET22, 23) can be performed.

[0068] According to this embodiment, in a cascode-type high-voltage element constructed by connecting multiple low-voltage elements in series, the provision of a control signal output electrode 13 makes it difficult to apply a voltage to the gates of the second and subsequent stages. This improves the withstand voltage of each low-voltage element and reduces the number of connected low-voltage elements. Furthermore, since it is difficult to apply a voltage to the gates of the second and subsequent stages, the withstand voltage of the high-voltage element can be designed without being limited to the withstand voltage of the gate oxide film of the low-voltage element.

[0069] Example 2

[0070] Reference Figure 5 , describing a semiconductor device according to a second embodiment of the present invention. Figure 5 This is a circuit diagram showing the structure of the semiconductor device of this embodiment, which is different from that of the embodiment 1. Figure 2 quite.

[0071] The semiconductor device of this embodiment is as follows Figure 5 As shown, the characteristic is that resistors 51, 52, 53 are connected in parallel between the source terminals 16 and drain terminals 17 of the horizontal MOSFETs 21, 22, 23 provided with the control signal output terminal 19. Figure 2 same.

[0072] According to this embodiment, if the structure obtained by connecting a resistor in parallel to a horizontal MOSFET is regarded as one element, the resistance in the off state can be adjusted using the resistance of the resistor, so the voltage sharing when the horizontal MOSFETs connected in series are in the off state can be arbitrarily adjusted, which can improve the reliability of the element.

[0073] Example 3

[0074] Reference Figure 6 , describing a semiconductor device according to a third embodiment of the present invention. Figure 6 This is a circuit diagram showing the structure of the semiconductor device of this embodiment, which is different from that of the embodiment 1. Figure 2 quite.

[0075] The semiconductor device of this embodiment is as follows Figure 6 As shown, the characteristic is that constant voltage diodes 61, 62, 63 are connected between the control signal output terminals 19 and the drain terminals 17 of the horizontal MOSFETs 21, 22, 23 provided with the control signal output terminals 19. Figure 2 same.

[0076] According to this embodiment, when the horizontal MOSFET is in the off state, if the voltage from the control signal output terminal 19 to the drain terminal 17 reaches a predetermined voltage, it is clamped by the constant voltage diodes 61, 62, and 63, thereby preventing an excessive voltage from being applied between the gate and the source of the horizontal MOSFET connected in series with the drain side, thereby improving the gate reliability of the horizontal MOSFET.

[0077] Furthermore, as examples of the constant voltage diodes 61 , 62 , and 63 , avalanche diodes and Zener diodes can be used.

[0078] Furthermore, the present invention is not limited to the above-described embodiments but encompasses various variations. For example, the above-described embodiments are provided as examples to facilitate understanding of the present invention and are not intended to necessarily include all of the described structures. Furthermore, a portion of the structure of one embodiment may be replaced with a structure of another embodiment, and a structure of another embodiment may be added to a structure of one embodiment. Furthermore, other structures may be added, deleted, or substituted for a portion of the structure of each embodiment.

[0079] Explanation of symbols

[0080] 1: Support substrate; 2: Embedded oxide film; 3: n-type semiconductor substrate (drift region); 4: p-type base region; 5: n-type source region; 6: p-type contact region; 7: n-type drain region; 8: Channel region; 9: Gate oxide film; 10: Gate electrode; 11: Source electrode; 12: Drain electrode; 13: Control signal output electrode; 14: Dielectric; 15: Element separation region; 16: Source terminal; 17: Drain terminal; 18: Gate terminal; 19: Control signal output terminal; 21, 22, 23: Horizontal MOSFET; 24: Emitter terminal; 25: Collector terminal; 41: Horizontal IGBT; 42: Diode; 51: Resistor; 52: Resistor; 53: Resistor; 61: Constant voltage diode; 62: Constant voltage diode; 63: Constant voltage diode.

Claims

1. A semiconductor device comprising a first semiconductor element and one or more second semiconductor elements connected in series, wherein: The first semiconductor element and the second semiconductor element have a control signal output terminal between a source terminal and a drain terminal or between an emitter terminal and a collector terminal. The gate terminal of the second semiconductor element is connected to a control signal output terminal of the first semiconductor element or the second semiconductor element connected in series adjacent to the source or emitter side of the second semiconductor element.

2. The semiconductor device according to claim 1, wherein The gate terminal and source terminal of the first semiconductor element are connected to a gate drive circuit. Based on the drive signal from the gate drive circuit to the gate terminal of the first semiconductor element, on / off control of all the first semiconductor element and the second semiconductor element can be performed.

3. The semiconductor device according to claim 1, wherein The second semiconductor element is a depletion-type semiconductor element having a gate voltage threshold of a negative voltage.

4. The semiconductor device according to claim 3, wherein The first semiconductor element and the second semiconductor element are lateral MOSFETs.

5. The semiconductor device according to claim 3, wherein At least one of the first semiconductor element and the second semiconductor element is formed of a lateral IGBT and a diode connected in antiparallel to the lateral IGBT.

6. The semiconductor device according to claim 3, wherein At least one of the first semiconductor element and the second semiconductor element is a HEMT.

7. The semiconductor device according to claim 6, wherein: At least one of the first semiconductor element and the second semiconductor element is formed of a HEMT and a diode connected in antiparallel to the HEMT.

8. The semiconductor device according to any one of claims 1 to 7, wherein: A resistor is connected in parallel to at least one of the first semiconductor element and the second semiconductor element.

9. The semiconductor device according to any one of claims 1 to 7, wherein: A diode is connected between the drain terminal or the collector terminal of the first semiconductor element and the second semiconductor element and the control signal output terminal.

10. The semiconductor device according to claim 9, wherein The diode is an avalanche diode or a Zener diode.

11. A power conversion device, characterized in that: The semiconductor device according to any one of claims 1 to 10 is used.

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