Instruction generation method and apparatus, and electronic device

Abstract

Embodiments of the present application provide an instruction generation method, device and electronic equipment. In the method, in the process of generating instructions for a processor test program of a computing device, a related address of an instruction to be generated is acquired. It is determined whether a storage page in which the related address of the instruction to be generated falls is illegal. The storage page includes an instruction page and a data page. In the case that the storage page in which the related address falls is illegal, an adjustment operation is performed on the instruction to be generated, so that the storage page in which the related address of the instruction to be generated falls is legal. After the adjustment operation is completed, the instruction to be generated is generated based on the related address. In this way, the processor test program finally generated can be used to verify the processor more comprehensively, while avoiding the instruction execution conflict caused by the mixed storage of the instruction page and the data page, and thus ensuring that the test program finally generated can be executed smoothly.

Description

TECHNICAL FIELD

[0001] The present application relates to the network technical field, in particular to a kind of instruction generation method, device and electronic equipment. BACKGROUND

[0002] With the development of very large scale integrated circuit technology, more and more functions are integrated on a single processor. In addition, people's requirements for processor functions are more and more complex, and the instruction set of the processor is constantly expanded, the number and type of instructions are greatly increased, and the corresponding functions are more complex. In order to meet these changing needs, the design of the processor becomes more and more complex. At present, in order to avoid errors after the processor is put into use, a test program needs to be generated to verify the processor with random instructions based on the test program, and then detect the functional design errors possessed by the processor.

[0003] Among them, the test program can include a randomly generated instruction sequence and the running data (DATA) related to the simulation execution of the instruction (PC) in the instruction sequence on the verification platform (i.e. the processor to be tested). The instructions and data are stored in the form of storage pages, and the storage page used to store the instructions can be referred to as an instruction page, and the storage page used to store the data can be referred to as a data page. In the prior art, in the generation process of the test program, in order to avoid conflicts during instruction execution, the instruction page and the data page are directly stored in two independent spaces by using the boundary mechanism (memBound). In this way, the verification of the processor is not sufficient, and the verification effect is poor. SUMMARY

[0004] In view of the above problems, the present application embodiment is proposed to provide an instruction generation method to overcome the above problems or at least partially solve the above problems.

[0005] Correspondingly, the present application embodiment also provides an instruction generation device, an electronic device and a storage medium to ensure the implementation and application of the above method.

[0006] In order to solve the above problems, the present application embodiment discloses an instruction generation method, the computing device has a processor and a virtual memory, and the instruction page and the data page are mixedly stored in the virtual memory. The method comprises:

[0007] In the process of generating instructions for the test program of the processor of the computing device, the related address of the instruction to be generated is obtained;

[0008] Determine whether the storage page in which the related address of the instruction to be generated falls is illegal; the storage page includes the instruction page and the data page;

[0009] In a case where the storage page where the relevant address falls is illegal, performing an adjustment operation on the instruction to be generated to make the storage page where the relevant address of the instruction to be generated falls legal;

[0010] After completing the adjustment operation, the to-be-generated instruction is generated based on the relevant address.

[0011] An embodiment of the present invention further discloses an instruction generation device, wherein the computing device comprises a processor and a virtual memory, wherein instruction pages and data pages are mixedly stored in the virtual memory, and the device comprises:

[0012] an acquisition module, configured to acquire, during a process of generating instructions for a processor test program of a computing device, a relevant address of an instruction to be generated;

[0013] a determination module, configured to determine whether a storage page where a related address of the instruction to be generated falls is illegal; the storage page includes the instruction page and the data page;

[0014] an adjustment module, configured to, when the storage page where the relevant address falls is illegal, perform an adjustment operation on the instruction to be generated so as to make the storage page where the relevant address of the instruction to be generated falls legal;

[0015] A generating module is used to generate the instruction to be generated based on the relevant address after completing the adjustment operation.

[0016] An embodiment of the present invention also discloses an electronic device comprising a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors, wherein the one or more programs include instructions for implementing the steps in the above method.

[0017] An embodiment of the present invention further discloses a readable storage medium. When instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute one or more methods described in the embodiment of the present invention.

[0018] The embodiments of the present invention include the following advantages:

[0019] In an embodiment of the present invention, during the process of generating instructions for a processor test program of a computing device, the relevant address of the instruction to be generated is obtained. A determination is made as to whether the storage page in which the relevant address of the instruction to be generated falls is illegal; the storage page includes an instruction page and a data page. If the storage page in which the relevant address falls is illegal, an adjustment operation is performed on the instruction to be generated to make the storage page in which the relevant address of the instruction to be generated falls legal. After the adjustment operation is completed, the instruction to be generated is generated based on the relevant address. In an embodiment of the present invention, by mixing the instruction page and the data page of the processor test program, the resulting processor test program can, to a certain extent, more comprehensively verify the processor, thereby improving the verification effect. Furthermore, if the storage page in which the relevant address falls is illegal, an adjustment operation is performed on the instruction to be generated to make the storage page in which the relevant address of the instruction to be generated falls legal. Only after the adjustment operation is completed is the instruction to be generated generated based on the relevant address. In this way, while achieving mixed storage, instruction execution conflicts caused by the mixed storage of instruction pages and data pages can be avoided, thereby ensuring that the resulting test program can be successfully executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a flowchart of steps of an embodiment of an instruction generation method of the present invention;

[0021] Figure 2 This is a schematic diagram of an instruction generation process provided by an embodiment of the present invention;

[0022] Figure 3 This is another schematic diagram of an instruction generation process provided by an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram of a jump instruction processing method provided by an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram of a memory access instruction provided by an embodiment of the present invention;

[0025] Figure 6 This is a schematic diagram of instruction generation under hybrid storage provided by an embodiment of the present invention;

[0026] Figure 7 It is a structural block diagram of an embodiment of an instruction generation device of the present invention;

[0027] Figure 8 The figure is a structural block diagram of an electronic device for generating instructions according to an exemplary embodiment. DETAILED DESCRIPTION

[0028] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] Reference Figure 1 , shows a flowchart of an embodiment of an instruction generation method of the present invention. The method can be applied to an electronic device, wherein the computing device has a processor and a virtual memory, and instruction pages and data pages are mixed and stored in the virtual memory. The method may specifically include the following steps:

[0030] Step 101: In the process of generating instructions for a processor test program of a computing device, obtain relevant addresses of the instructions to be generated.

[0031] Step 102: Determine whether the storage page where the relevant address of the instruction to be generated falls is illegal; the storage page includes the instruction page and the data page.

[0032] Step 103: When the storage page where the relevant address falls is illegal, perform an adjustment operation on the instruction to be generated to make the storage page where the relevant address of the instruction to be generated falls legal.

[0033] With respect to the above steps 101 to 103, in an embodiment of the present invention, the instruction page may be a storage page for storing instructions in the processor test program, and the data page may be a storage page for storing data in the processor test program. The data may be the operation required for the execution of the instruction, for example, the data may be the data required for the operation of the memory access instruction. The instruction page and the data page may both be virtual pages, that is, the addresses on the instruction page and the data page are virtual addresses. Since the operating system performs mapping from the virtual address space to the physical address space (conversion from virtual address to physical address) in units of pages, the mixed storage of the address of the instruction and the address of the data in the embodiment of the present invention is embodied in the form of mixed storage of the instruction page and the data page. The mixed storage of the instruction page and the data page can be understood as the instruction page and the data page appearing in the same storage space, the next page of the instruction page can be the data page, and the next page of the data page can be the instruction page.

[0034] The instruction to be generated may be a random instruction that is currently required to be generated during the generation of the processor test program. Exemplarily, the relevant address of the instruction to be generated may be obtained from pre-set information. The relevant address may be an address related to the instruction to be generated, for example, the instruction address of the instruction to be generated itself, the target address of the instruction to be generated, the next instruction address, and the like. The instruction address may be the storage address of the instruction, and the instruction address is used to indicate at which address the instruction is stored. In an embodiment of the present invention, since instruction pages and data pages are mixed and stored, an illegal address may occur, that is, the storage page where the relevant address of the instruction to be generated falls is illegal, which may cause a conflict when subsequent instructions are executed, resulting in an error. Accordingly, in an embodiment of the present invention, whether the storage page where the relevant address of the instruction to be generated falls is illegal is detected during the generation process, and if the storage page where the relevant address falls is illegal, an adjustment operation is performed on the instruction to be generated so that the storage page where the relevant address of the instruction to be generated falls is legal, thereby avoiding conflicts while achieving mixed storage.

[0035] Exemplarily, the fact that the storage page where the relevant address falls is illegal may indicate that the address required to be accessed for the memory access operation of the memory access instruction falls on the instruction page, or that the target address of the jump instruction falls on the data page, or that the address of the next instruction of the sequentially executed instruction falls on the data page. That is, the memory access operation on the instruction page and the read instruction behavior on the data page are both considered illegal. Accordingly, in the case of different instruction types, the types of relevant addresses involved in the judgment may be different. In the case where the relevant address is an instruction address, if it falls on the data page, it can be determined that the storage page it falls on is illegal. In the case where the relevant address is the target address of the memory access instruction, if it falls on the instruction page, it can be determined that the storage page it falls on is illegal. In the case where the relevant address is the target address of the memory access instruction, if it falls on the instruction page, it can be determined that the storage page it falls on is illegal. In the case where the relevant address is the target address of the jump instruction, if it falls on the data page, it can be determined that the storage page it falls on is illegal.

[0036] It should be noted that, in an embodiment of the present invention, the boundary mechanism can be removed, thereby preventing data pages and instruction pages from being independently stored in different spaces. Specifically, the operation of removing the boundary mechanism can be performed before step 101. Specifically, the pre-set boundary address can be removed. For example, when the instruction page is only allowed to appear in an address space less than 10, and the data page is only allowed to appear in an address space greater than 10, then "10" is the boundary address. When there is no restriction of "10", that is, after removing the pre-set boundary address, there can be no obvious boundary between the locations where the data page and the instruction page appear, that is, mixed storage of the two is achieved.

[0037] Step 104: After completing the adjustment operation, generate the instruction to be generated based on the relevant address.

[0038] Since the storage page where the relevant address of the instruction to be generated falls after the adjustment operation is completed is legal, that is, there is no conflict. Therefore, after the adjustment operation is completed, the instruction to be generated is generated based on the relevant address, which can ensure that the generated instruction can be executed normally to a certain extent, and then ensure that the processor test program finally generated can be executed normally, avoiding the problem of error during execution. It should be noted that after the instruction to be generated is generated, the next instruction to be generated can be generated. When the preset end condition is reached, the generation is stopped. At this time, the instruction sequence composed of the instructions to be generated and the data operated by the instructions to be generated can constitute the processor test program. Among them, the preset end condition can be set according to actual needs. For example, the preset end condition can be that the number of instructions generated reaches a preset number threshold, the generation time reaches a preset time threshold, and so on.

[0039] In summary, the instruction generation method provided in an embodiment of the present invention obtains the relevant address of the instruction to be generated during the process of generating instructions for a processor test program of a computing device. A determination is made as to whether the storage page in which the relevant address of the instruction to be generated falls is illegal; storage pages include instruction pages and data pages. If the storage page in which the relevant address falls is illegal, an adjustment operation is performed on the instruction to be generated to ensure that the storage page in which the relevant address of the instruction to be generated falls is legal. After the adjustment operation is completed, the instruction to be generated is generated based on the relevant address. In an embodiment of the present invention, by mixing the instruction pages and data pages of the processor test program, the resulting processor test program can, to a certain extent, more comprehensively verify the processor. Furthermore, if the storage page in which the relevant address falls is illegal, an adjustment operation is performed on the instruction to be generated to ensure that the storage page in which the relevant address of the instruction to be generated falls is legal. Only after the adjustment operation is completed is the instruction to be generated generated based on the relevant address. In this way, while achieving mixed storage, instruction execution conflicts caused by the mixed storage of instruction pages and data pages can be avoided, thereby ensuring that the resulting test program can be successfully executed.

[0040] Optionally, the operation of determining whether the storage page where the relevant address of the instruction to be generated falls is illegal may specifically include:

[0041] Step 1021 : When the instruction address of the instruction to be generated falls within a data page, directly determine that the relevant address falls within an illegal page.

[0042] Step 1022: When the instruction address of the instruction to be generated does not fall into the data page and the instruction to be generated is a jump instruction, and when the target address of the jump instruction falls into the data page, determine that the storage page where the relevant address falls is illegal; when the target address of the jump instruction does not fall into the data page, determine that the storage page where the relevant address falls is legal.

[0043] Step 1023: When the instruction address of the instruction to be generated does not fall into the data page and the instruction to be generated is a sequential execution instruction, if a preset situation is reached, it is determined that the storage page where the relevant address of the sequential execution instruction falls is illegal; the preset situation is that the next instruction address of the sequential execution instruction falls into the data page, or the sequential execution instruction is a memory access instruction and the target address of the memory access instruction falls into the instruction page; otherwise, it is determined that the storage page where the relevant address falls is legal.

[0044] In an embodiment of the present invention, the instruction type can be used to characterize the type of instruction currently to be generated. Exemplarily, the instruction type may include jump instructions and sequential execution instructions. Sequential execution instructions may include memory access instructions and non-memory access instructions (e.g., addition instructions, clear instructions, etc.). The instruction type of the instruction to be generated can be specified based on actual needs. Exemplarily, the total number of instructions to be generated, the type of each instruction, the opcode, the data to be operated on, the instruction address, the target address, etc. can be pre-set. Accordingly, the instruction type of the instruction to be generated can be determined from pre-set information. Alternatively, the instruction type of the instruction to be generated can be determined by the test program generator. Exemplarily, the instruction type of the instruction currently to be generated can be randomly selected by the test program generator for this generation operation. Accordingly, when generating a particular instruction, the test program generator may first record the instruction page where the instruction is located (i.e., the storage page where the instruction address of the instruction is located), if not previously recorded, and then determine the instruction type. For example, the instruction type randomly selected for this generation operation may be determined.

[0045] If the storage page where the instruction address of the instruction to be generated is located is a data page, it can be determined that the instruction address of the instruction to be generated falls on the data page. Accordingly, this will cause the instruction to be read from the data page when the instruction is executed, thereby causing a conflict. Therefore, when the instruction address included in the relevant address falls on the data page, it can be directly determined that the storage page where the relevant address of the instruction to be generated falls is illegal. Among them, the operation of detecting whether the instruction address of the instruction to be generated is legal, that is, detecting whether the instruction address of the instruction to be generated falls on the data page, can be performed by the generator.

[0046] If the storage page where the instruction address of the instruction to be generated is located is an instruction page, it can be determined that the instruction address does not fall into the data page, and it can be further determined whether the storage page where the relevant address falls is illegal based on the instruction type and other addresses included in the relevant address. Among them, whether the storage page in the storage space for storing the test program is a data page or an instruction page can be determined according to actual needs. Exemplarily, when the content written for the first time in the storage page is data, the storage page can be defined as a data page, and when the content written for the first time in the storage page is an instruction, the storage page can be defined as an instruction page. Alternatively, according to actual needs, each storage page in the storage space is designated in advance to specify whether the storage page is a data page or an instruction page.

[0047] In an embodiment of the present invention, if the instruction address in the relevant addresses falls within a data page, the memory page in which the relevant addresses fall is directly determined to be illegal. If the instruction address in the relevant addresses does not fall within a data page, a determination is further made as to whether the memory page in which the relevant addresses fall is illegal based on the instruction type and other addresses included in the relevant addresses. This improves determination efficiency to a certain extent while ensuring accuracy.

[0048] Furthermore, in the case where the instruction type indicates a jump instruction, the other addresses may include a target address. In the case where the instruction type indicates a sequential execution instruction, the other addresses may include a next instruction address (SequenceNextPc, SNP) and a target address. The next instruction address refers to the instruction address of the next instruction to be executed after the instruction to be generated is executed. The sequential execution instruction is a memory access instruction and the target address of the instruction to be generated falls into the instruction page, which may mean that the instruction to be generated is a memory access instruction and its memory access address falls into the instruction page.

[0049] Furthermore, if the instruction type is a jump type, the instruction type indicates that the instruction to be generated is a jump instruction. If the instruction type is a sequential execution type, the instruction type indicates that the instruction to be generated is a sequential execution instruction. Specifically, when the instruction address of the instruction to be generated does not fall into the data page, for a jump instruction, when the instruction to be generated belongs to a jump instruction, the illegal behavior that will cause a conflict is that the target address of the jump instruction falls on the data page. Therefore, in this case, it can be determined that the storage page where the relevant address of the instruction to be generated falls is illegal. Otherwise, it can be determined that the storage page where the relevant address of the instruction to be generated falls is legal. For non-jump instructions (i.e., sequential execution instructions), since sequential execution instructions cannot control the execution direction of the program, when this instruction is exactly at the boundary between an instruction page and a certain instruction page, the next instruction address will fall on the data page. When the instruction to be generated belongs to a sequential execution instruction, the illegal behavior that will cause a conflict is that the instruction address of the next instruction falls on the data page, or, the instruction address of the next instruction does not fall on the data page but the target address falls on the instruction page. Therefore, in this case, it can be determined that the storage page where the relevant address of the instruction to be generated falls is illegal. Conversely, when the sequentially executed instruction is not a memory access instruction and the instruction address of the next instruction does not fall within a data page, it can be determined that the storage page where the relevant address falls is legal. When the sequentially executed instruction is a memory access instruction, the instruction address of the next instruction does not fall within a data page, and the target address of the memory access instruction falls within a data page, it is determined that the storage page where the relevant address falls is legal. That is, in this embodiment of the present invention, since the instruction page and the data page are no longer stored in two independent spaces, a variety of special illegal situations will be encountered during the generation of the test program. In the case where the target address of the memory access instruction is illegal, the target address of the memory access instruction (across pages) falls on the instruction page. In the case where the target address of the jump instruction is illegal, the target address of the jump instruction falls on the already generated data page. In the case where the SNP of the sequentially executed instruction is illegal, the SNP falls on the already generated data page.

[0050] In the embodiment of the present invention, for different instruction types, the target address and the next instruction address are adaptively determined to determine whether the relevant address falls into an illegal page. This ensures the accuracy of the determination to a certain extent, and minimizes the possibility that the final instruction to be generated may contain illegal pages, which in turn may cause abnormal execution of the instruction.

[0051] In one application scenario of an embodiment of the present invention, the generated test program can be used to perform functional verification on verification objects such as chips and microprocessors. The test program is a functional verification program. Since the processor core of the verification object may have a fast translation cache (Translation Look-aside Buffer, TLB) and support the TLB mechanism, it may also not have a TLB and not support the TLB mechanism. Among them, TLB is also called a page table buffer or a fast table, which is used to store the page table of the most frequently accessed pages in the current processor, which is equivalent to a cache of the operating system page table. The page table can record the correspondence between virtual pages and physical pages. It should be noted that the implementation method given in the above steps 1021 to 1023 can be adopted when the processor supports TLB attribute exceptions or does not support TLB attribute exceptions.

[0052] In one implementation, when the processor supports TLB attribute exceptions, the step of determining whether the storage page where the relevant address of the instruction to be generated falls is illegal may specifically include: setting the data page in the TLB as a non-executable exception and the instruction page as a non-readable and non-writable exception; and when a TLB attribute exception occurs in the instruction to be generated, determining that the storage page where the relevant address falls is illegal.

[0053] Accordingly, the step of performing an adjustment operation on the instruction to be generated may specifically include: generating the instruction to be generated at a legal instruction address when a TLB non-executable exception occurs in the instruction to be generated.

[0054] Specifically, a TLB attribute exception may be performed on the instruction address of the instruction to be generated, so as to control the verification object to skip the instruction to be generated during the execution of the test program and read and execute the instruction from an available address belonging to the instruction page (i.e., a legal instruction address). The instruction to be generated at this time can be generated at the legal instruction address.

[0055] Among them, TLB attributes may include: unreadable, unwritable, invalid, and unexecutable. In an embodiment of the present invention, performing TLB attribute exception processing on the instruction address of the instruction to be generated can specifically refer to setting a non-executable exception at the instruction address. When an exception occurs, the instruction here no longer performs its own function, which is equivalent to the program execution "skipping" the instruction here, thereby avoiding the execution of illegal operations. Specifically, the processor TLB attribute exception mechanism can be used to generate a TLB non-executable exception at the instruction address.

[0056] Specifically, when the processor core supports the TLB mechanism, that is, when the processor core supports TLB attribute exception trap processing, different attributes can be assigned to the instruction page and the data page respectively to control the legal operation range on different pages. Specifically, in an embodiment of the present invention, the data page is assigned an "unexecutable" attribute, so that when the instruction address falls on the data page, the processor core can determine that the instruction address is illegal. The instruction page is assigned "unreadable" and "unwritable" attributes, that is, when the memory access operation falls on the instruction page, the processor core can determine that the operation is not allowed. In these two cases, it can be determined that an exception instruction is encountered.

[0057] Accordingly, when the processor encounters an exception instruction (i.e., an instruction whose instruction address has been subjected to TLB attribute exception processing) during the execution of the instructions in the test program, it will directly fall into the exception handler program and no longer execute the function of the instruction. At the same time, a legal instruction address will be found in the storage space (e.g., memory space) as the instruction fetch address after exception processing. Specifically, the available address belonging to the instruction page can be read as the legal instruction address. The instruction is read based on the instruction fetch address and the read instruction is executed. Among them, the available address belonging to the instruction page can be pre-recorded, and the legal instruction address can be pre-recorded in the embodiment of the present invention as the available address. Accordingly, in the subsequent verification process, the available address can be assigned to the processor core so that the processor core reads the instruction from the available address and executes the read instruction. In this way, it is possible to avoid the execution of instructions to be generated that contain illegal behavior, and thus avoid abnormalities in the execution of instructions, while ensuring that the verification object can obtain and execute the instruction.

[0058] For example, Figure 2 This is a schematic diagram of an instruction generation process provided by an embodiment of the present invention. Figure 2As shown, after instruction generation begins, the instruction address (CurPC) of the current instruction can be determined to be legal. Specifically, the instruction address of the instruction to be generated is determined to fall within a data page. If so, it is determined to be illegal. Accordingly, an exception can be made for the current instruction, and a legal instruction address can be specified (i.e., a legal nextPC is specified). Specifically, a TLB attribute exception is made for the instruction address of the instruction to be generated, and the available address is recorded as a legal instruction address. Instruction generation can then proceed, i.e., the instruction to be generated is generated. Conversely, if it does not fall within a data page, it is determined to be legal, and the instruction can be generated normally at this address. Accordingly, the generator can determine the instruction type (instType) of the current instruction. Different instruction types are handled differently. Specifically, if the current instruction is not a memory access instruction, instruction generation can proceed directly and the instruction can be generated normally. If the current instruction is a memory access instruction, the TLB attributes at the memory access address are used to determine whether an exception has occurred for this memory access instruction, and the instruction can then be generated normally. The memory access address is the target address of the memory access instruction. Specifically, the memory access address of the memory access instruction can be determined to be legal. If the memory access address falls within the data page, the memory access address is determined to be legal, and accordingly, the instruction can be directly generated. If the memory access address falls within the instruction page, the memory access address is determined to be illegal, and accordingly, an exception can be processed for the current instruction before the instruction is generated again.

[0059] Optionally, when the processor does not support TLB, the step of performing an adjustment operation on the instruction to be generated may specifically include:

[0060] Step 1031 : When the instruction address of the instruction to be generated falls within a data page, adjust the instruction address of the instruction to be generated so that the instruction address falls within an instruction page.

[0061] Step 1032: When the instruction address of the instruction to be generated does not fall within the data page and the instruction to be generated is a jump instruction, if the target address of the jump instruction falls within the data page, then reselect a target address falling within the instruction page for the jump instruction from the optional range of the target address of the jump instruction; and adjust the target address of the jump instruction to the reselected target address falling within the instruction page.

[0062] Step 1033: When the instruction address of the instruction to be generated does not fall within the data page and the instruction to be generated is a sequential execution instruction, if the next instruction address of the sequential execution instruction falls within the data page, then the sequential execution instruction is replaced with a jump instruction whose target address falls within the instruction page; if the next instruction address of the sequential execution instruction does not fall within the data page, and the sequential execution instruction is a memory access instruction and the target address of the memory access instruction falls within the instruction page, then reselect a target address that falls within the data page for the memory access instruction from the optional range of the target address of the memory access instruction; and adjust the target address of the memory access instruction to the reselected target address that falls within the data page.

[0063] In an embodiment of the present invention, an address can be reselected from the addresses belonging to the instruction page as the instruction address for the instruction to be generated. In this way, the instruction address of the instruction to be generated can be placed on the instruction page, ensuring that the instruction to be generated can be fetched normally. Furthermore, if the instruction address of the instruction to be generated does not fall on the data page, an adjustment operation can be performed on the instruction to be generated based on the instruction type.

[0064] The target address of a jump instruction may refer to an instruction jump address, that is, the instruction jump address is used to indicate the instruction address to which the jump execution should be directed. If the target address of a jump instruction falls within a data page, and no instruction exists on the data page, an execution exception may occur. Accordingly, in an embodiment of the present invention, by adjusting the target address of the jump instruction to a target address that falls within an instruction page, it is possible to prevent the relevant address of the instruction to be generated from falling within an illegal page, thereby avoiding an execution exception.

[0065] Furthermore, if the address of the next instruction of a sequentially executed instruction falls within a data page, and no instruction exists in the data page, an execution exception may occur. Accordingly, in an embodiment of the present invention, by replacing the sequentially executed instruction with a jump instruction whose target address falls within an instruction page, it is possible to prevent the address of the instruction to be generated from falling within an illegal page, thereby avoiding the execution exception.

[0066] The target address of a memory access instruction represents the instruction memory access address, which is used to indicate the address of the data to be accessed. If the address of the next instruction of a sequentially executed instruction does not fall within a data page, but the sequentially executed instruction is a memory access instruction and the target address of the memory access instruction falls within an instruction page, an execution exception will occur because no data exists in the instruction page. Accordingly, in an embodiment of the present invention, by adjusting the target address of the memory access instruction to a target address that falls within a data page, it is possible to prevent the relevant address of the instruction to be generated from falling within an illegal page, thereby avoiding an execution exception.

[0067] For example, for a jump instruction, the target address of the jump instruction needs to be controlled to fall somewhere on the instruction page. For a non-jump instruction (i.e., a sequential execution instruction), the SNP needs to be controlled to fall on the instruction page. Furthermore, if the non-jump instruction is a memory access instruction, the target address needs to be controlled to fall on a data page. Figure 3 This is another schematic diagram of the instruction generation process provided by an embodiment of the present invention. Figure 3 As shown, for jump instructions, you can choose to select a legal target address for the jump instruction (i.e., select a legal targetPc), and then generate the instruction. For non-jump instructions (i.e., sequential execution instructions), if the next instruction address is illegal, the sequential execution instruction can be replaced with a jump instruction, and a legal target address can be selected for the jump instruction to ensure that the target address of the replaced jump instruction falls into the instruction page. If the next instruction address is legal, you can further determine whether the instruction is a memory access instruction. If so, select a legal target address for the memory access instruction (i.e., select a legal memory access address), and then generate the instruction. If not, you can directly generate the instruction.

[0068] Because the processor does not support the TLB mechanism, it is impossible to skip instructions with illegal behavior through TLB attribute exception processing. Therefore, in the embodiment of the present invention, by replacing the instruction to be generated, or adjusting the address of the instruction to be generated, it is ensured that the target address of the memory access instruction all falls on the data page, and the target address of the jump instruction all falls on the instruction page. This can, to a certain extent, prevent the relevant address of the adjusted instruction to be generated from falling on the illegal page, thereby ensuring the adjustment effect.

[0069] Furthermore, jump instructions can be divided into immediate jump instructions and register jump instructions. The choice of the target address can be controlled by constraining the choice of jump instruction operands. Immediate jump instructions are also called immediate-addressed instructions, Class B jump instructions. Register jump instructions are also called register-addressed instructions, Class J jump instructions. The target address of a Class B jump instruction is (current PC + immediate value), while the target address of a Class J jump instruction is (register value + immediate value). The immediate value is the operand.

[0070] Accordingly, each jump instruction has a selectable target address range, determined by its operands. Specifically, the target address range for a Class B jump instruction can be: "Current PC + Minimum Immediate Value" to "Current PC + Maximum Immediate Value." The target address range for a Class J jump instruction can be: "Register Value + Minimum Immediate Value" to "Register Value + Maximum Immediate Value."

[0071] For Class B jump instructions, since Class B jump instructions will only perform a jump action when the jump condition is met. If the jump condition is not met, no jump action will occur. Therefore. In an embodiment of the present invention, specifically, when the jump condition is met, if the target address of the jump instruction falls into the data page, then a target address that falls into the instruction page is reselected for the jump instruction from the optional range of the target address of the jump instruction. Accordingly, if the jump condition is not met, since no jump action occurs, it is possible to only determine whether the SNP of the jump instruction is legal. If the SNP of the jump instruction falls into the data page, the jump instruction is replaced with a jump instruction whose target address falls into the instruction page. If the SNP of the jump instruction does not fall into the data page, the jump instruction is directly generated. For Class J jump instructions, Class J jump instructions jump unconditionally, that is, a jump action will definitely occur. Therefore, a legal address can be directly selected from the optional range of the target address.

[0072] Furthermore, if all pages within the selectable range are data pages, it is determined that there is no target address within the target address selectable range that falls within an instruction page, and the legal address search fails. It should be noted that if there is a non-attribute page within the selectable range, then the non-attribute page can be directly used as the instruction page, and the target address for the jump instruction can be reselected from it to legally generate the instruction. Among them, the non-attribute page is a page that has never generated instructions or data before, and is neither an instruction page nor a data page.

[0073] Optionally, when reselecting a target address that falls within the instruction page for the jump instruction, if the target address selectable range of the jump instruction does not include a target address that falls within the instruction page, the embodiment of the present invention may further include the following steps:

[0074] Step 21: When the jump instruction is an immediate addressing instruction, replace the jump instruction with a register jump instruction.

[0075] Step 22: When the jump instruction is a register jump instruction and the next instruction address of the jump instruction is legal, the register value in the register jump instruction is reloaded to adjust the target address optional range of the jump instruction, and from the adjusted target address optional range, a target address falling into the instruction page is reselected for the jump instruction.

[0076] Step 23: If the jump instruction is a register jump instruction and the next instruction address of the jump instruction is illegal, replace the jump instruction with an immediate addressing instruction.

[0077] In the embodiment of the present application, if a legal address is not found in step 1032, i.e., there is no target address falling into the instruction page in the target address optional range of the jump instruction, the J-type jump instruction can be directly used to replace the B-type jump instruction, and the generation of the program continues. For example, the J-type jump instruction can be processed as a to-be-generated instruction.

[0078] For the J-type jump instruction, since the target address of the J-type jump instruction is the sum of the register value and the immediate number, the process of searching for a legal address can be continued by replacing a register. The target address optional range can include ranges formed by the register values of different registers. Assuming that there are two available registers, register A and register B, the target address optional range can include: "the register value of register A + the minimum immediate number value" to "the register value of register A + the maximum immediate number value", and "the register value of register B + the minimum immediate number value" to "the register value of register B + the maximum immediate number value". The available registers can be set according to actual needs. The available registers can be one or multiple. For example, the available registers can include the registers available for use as the registers of the jump instruction in the processor.

[0079] If all the registers do not meet the requirement, i.e., even by replacing a register, a target address falling into the instruction page cannot be selected for the jump instruction. Then it can be determined that there is no target address falling into the instruction page in the target address optional range. Accordingly, it can be further determined whether the next instruction address of the jump instruction is legal. If it is legal, i.e., the next instruction address falls into the instruction page. Then the value in a certain register can be changed by inserting other instructions. Since the register value is changed, the target address optional range of the jump instruction is changed. Therefore, a target address falling into the instruction page can be selected for the jump instruction from the adjusted target address optional range, i.e., the J-type jump instruction is generated again. The value of the reloaded register can come from an address on an existing instruction page. In the generation process of the test program, the generator has recorded the instruction pages and data pages generated in the test program generation process. In the process of reloading the register, the appropriate immediate number can be selected from the instruction page according to the recorded page number information and written into the register, so that the value of the reloaded register can come from an address on an existing instruction page. If it is not legal, i.e., the next instruction address falls into the data page, the next instruction address is illegal. Then it can be determined that this position must be a jump instruction, because the jump instruction can be replaced by an immediate number addressing instruction to start the generation of the B-type jump instruction.

[0080] It should be noted that when the same PC address has two situations: a B-type jump instruction is replaced by a J-type jump instruction, and then a J-type jump instruction is replaced by a B-type jump instruction. That is, the instruction to be generated is replaced by a B-type jump instruction, and then replaced by a J-type jump instruction, or the instruction to be generated is replaced by a J-type jump instruction, and then replaced by a B-type jump instruction, then it can be determined that the test program generation has failed. For example, Figure 4 FIG. 1 is a schematic diagram of a jump instruction processing method provided by an embodiment of the present invention. Figure 4 As shown, if a valid address is not found for a Class B jump instruction, a Class J jump instruction may be used for generation. If a valid address is not found for a Class J jump instruction, a Class B jump instruction may be used for generation. Furthermore, the reason why the jump instruction target address is illegal may also be closely related to the actual internal state of the processor.

[0081] In the embodiment of the present invention, by performing register reloading or instruction replacement on the jump instruction, it can be ensured that the generated jump instruction has a legal address, thereby avoiding errors in the subsequent verification process.

[0082] Optionally, in the case of reselecting a target address falling into a data page for the memory access instruction, the embodiment of the present invention may further include:

[0083] Step 31: If the target address optional range of the memory access instruction does not include a target address that falls within the data page, reload the register value in the memory access instruction to adjust the target address optional range of the memory access instruction.

[0084] Step 32: Reselect a target address that falls within the data page for the memory access instruction from the adjusted target address optional range of the memory access instruction.

[0085] In an embodiment of the present invention, memory access instructions can be divided into three categories based on the different methods of calculating the target address: base, base+imm, and base+index. The value of base is the instruction base address, imm is the numerical operand of the instruction, and imm has a certain value range. The value of imm is used by the memory access instruction to calculate the target address. Index is the register operand of the instruction, and the value stored in index is used by the memory access instruction to calculate the target address. In an embodiment of the present invention, the target address can be controlled by constraining the selection of operands for the memory access instruction.

[0086] In order to control the number of data pages of the test program and increase the locality of reference of the memory access address, in the generation process of the test program, a certain register is often fixedly selected as the base register, and the register is only allowed to be modified in certain special cases, for example, in the case of register reloading, that is, the register does not appear as the target register of the instruction in the random generation process of the instruction.

[0087] For the base type memory access instruction, the target address of the memory access instruction is the register value of the base register, and correspondingly, it can be judged whether the register value of the base register as the memory access start address is legal. If the memory access start address is the register value of the base register, the page where the memory access address falls is a data page, which means that it is legal. Otherwise, it means that it is not legal. Correspondingly, in this case, the optional range of the target address of the memory access instruction only includes the memory access address formed by taking the register value of the base register as the memory access start address. If the memory access start address is the register value of the base register, it is not legal, and it can be determined that there is no target address falling into the data page in the optional range of the target address of the memory access instruction. For the base+imm type memory access instruction, the optional range of the target address of the memory access instruction can be: base+imm minimum value~base+imm maximum value.

[0088] If there is no target address falling into the data page in the optional range of the target address of the memory access instruction, that is, no legal memory access address is found. For the base type memory access instruction and the base+imm type memory access instruction, the register reloading mechanism can be directly entered, the required value is written into the base register by inserting the write immediate number instruction, and then the optional range of the target address of the memory access instruction is adjusted. Correspondingly, the target address of the memory access instruction falling into the data page can be selected from the adjusted optional range of the target address of the memory access instruction, that is, the generation of the memory access instruction is reattempted.

[0089] For base+index type memory access instructions, the target address of the memory access instruction is the sum of the register value of the base register and the register value of the index register. It can be determined whether the sum of the register values ​​is legal as the memory access starting address. If the sum of the register values ​​is used as the memory access starting address, and the page where the memory access address falls is a data page, it is legal. Otherwise, it is illegal. Accordingly, in this case, another register can be used as the index register to continue to repeat the process of searching for a legal address. The optional range of the target address of the memory access instruction may include a memory access address formed by taking the sum of the register values ​​of different index registers as the memory access starting address. Assuming that there are two available index registers: index register C and index register D, the optional range of the target address of the memory access instruction may include: a target address formed by taking the sum of the register value of the base register and the index register C as the starting address, and a target address formed by taking the sum of the register value of the base register and the index register D as the starting address. Exemplarily, the available index registers may include registers in the processor that can be used as index registers for memory access instructions.

[0090] If all index registers cannot find a legal address, that is, by replacing the index register, it is impossible to select a target address that falls on the data page for the memory access instruction, then it can be determined that the target address that falls on the data page does not exist in the target address optional range of the memory access instruction. Accordingly, for the base+index type memory access instruction, the register reload mechanism can also be entered, and the required value can be written into the base register by inserting a write immediate instruction, thereby adjusting the target address optional range of the memory access instruction. Accordingly, the target address that falls on the data page can be reselected for the memory access instruction from the adjusted target address optional range of the memory access instruction, that is, the generation of the memory access instruction can be retried. Among them, the register value of the register reload can be derived from the value within the range of a certain data page. During the generation of the test program, the generator has recorded the instruction page and data page generated during the test program generation process. During the process of this register reloading, the appropriate immediate value can be selected from the data page and written into the register based on the recorded page number information, so that the value of the reloaded register is derived from the address on an existing data page.

[0091] For example, Figure 5 is a schematic diagram of a memory access instruction provided by an embodiment of the present invention, such as Figure 5As shown, for memory access instructions, if the target address falls on the instruction page, it is illegal. Therefore, it is necessary to control the target address of the memory access instruction to fall on the instruction page. Memory access instructions are sequentially executed instructions. Therefore, when generating memory access instructions, the SNP of the memory access instruction must be legal. If it is illegal, a jump instruction is used to find a legal instruction page again. In other words, the sequential execution instruction is replaced with a jump instruction whose target address falls on the instruction page, and the jump instruction generation begins.

[0092] If the SNP is legal, an adjustment can be made to attempt to generate a memory access instruction. In the method of the present invention, the target address of the memory access instruction cannot fall on the PC page, so it is necessary to determine whether there is a legal address (whether there is a legal page) within the optional range of the target address of the memory access instruction. It should also be noted that the memory access behavior of the memory access instruction may span pages. Here, spanning pages refers to the phenomenon that the starting address of the target address of the memory access instruction falls on the data page, but because the address of the data read by the memory access instruction has a certain length, it may cross the boundary of this page during the reading process and enter the next adjacent page. In other words, memory access operations are performed on two pages simultaneously. Therefore, in an embodiment of the present invention, if the SNP is legal, it can be determined whether there is a page span. If so, the legitimacy of the two pages before and after the page span (i.e., the two pages where the target address of the memory access instruction falls) is determined. If both pages are data pages, it can be determined to be legal; otherwise, it can be determined to be illegal. It should be noted that in the case of a memory span, if there is a non-attributed page between the two pages where the target address of the memory access instruction falls, the non-attributed page can be directly used as the data page, so that the span between the two pages before and after the page span is legal.

[0093] Furthermore, if a target address that falls within the data page is reselected for the memory access instruction from the target address optional range of the memory access instruction, that is, a legal address is found, then instruction generation can be performed. Otherwise, register reloading can be performed, that is, the value in the register is changed by inserting other instructions. Since the register value is changed, the target address optional range of the memory access instruction is changed. Therefore, the target address that falls within the data page can be reselected for the memory access instruction from the adjusted target address optional range, that is, the memory access instruction can be generated again. Among them, the base register can be reloaded. It should be noted that the reason why the target address of the memory access instruction is illegal is also related to the characteristics of the processor itself (for example, whether aligned access is supported).

[0094] In the embodiment of the present invention, by performing register reloading on the memory access instruction, it can be ensured that the generated memory access instruction has a legal address, thereby avoiding errors in the subsequent verification process.

[0095] The following describes a specific application scenario involved in an embodiment of the present invention. In the field of microprocessors, the functional requirements for microprocessors are becoming increasingly complex. In order to meet these changing needs, the design of processors has become increasingly complex, and the functional verification of processors has become very complex, and the verification cycle is very long, which inevitably affects the development time of the processor. At the same time, it is not uncommon to discover design errors after the processor chip is put on the market. Therefore, the generation of random instruction verification programs, as a relatively important link in the process of microprocessor functional verification, has received widespread attention.

[0096] Figure 6 This is a schematic diagram of instruction generation under hybrid storage provided by an embodiment of the present invention, such as Figure 6 As shown, if it is a jump instruction, a legal address (i.e., a legal target address) can be found for the jump instruction based on the method provided in the above related description to complete the generation of the instruction. If it is a sequential execution instruction, when the SNP is illegal, the current sequential execution instruction can be canceled and the jump instruction generation can be started. When the SNP is legal, if it is a non-memory access instruction, the instruction generation can be completed directly. If it is a memory access instruction, a legal address (i.e., a legal memory access target address) can be found for the memory access instruction based on the method provided in the above related description to complete the generation of the instruction.

[0097] In an embodiment of the present invention, factors affecting the selection of (PC and DATA) addresses may include instruction types, such as jump instruction types and sequential execution instruction types. The present invention performs targeted processing based on instruction types, solving the problem of selecting legal addresses. Furthermore, compared with the prior art, the PC page and the DATA page are directly stored separately and independently. In an embodiment of the present invention, a mixed storage mechanism for instruction pages and data pages in a microprocessor function verification program is provided. In an embodiment of the present invention, conflicts can be avoided when mixed storage is implemented. In the mode of mixed storage of instruction pages and data pages, since there is no obvious spatial barrier between the instruction address and the memory access address, both are allowed to appear in any valid position in the storage space. Compared with spatially isolated storage, there are more factors that affect each other between the two, and the test program generation process becomes more complicated. Therefore, the comprehensiveness of microprocessor function verification can be improved, the coverage of microprocessor function verification can be improved, and the convergence speed of verification coverage can be accelerated.

[0098] It should be noted that for the sake of simplicity, the method embodiments are described as a series of actions. However, those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0099] Reference Figure 7 , shows a structural block diagram of an embodiment of an instruction generation device of the present invention, wherein the computing device has a processor and a virtual memory, and instruction pages and data pages are mixedly stored in the virtual memory, and specifically may include the following modules:

[0100] An acquisition module 201 is configured to acquire, during a process of generating instructions for a processor test program of a computing device, a relevant address of the instruction to be generated;

[0101] A determination module 202 is configured to determine whether a storage page where a related address of the instruction to be generated falls is illegal; the storage page includes the instruction page and the data page;

[0102] An adjustment module 203 is configured to, when the storage page where the relevant address falls is illegal, perform an adjustment operation on the instruction to be generated so as to make the storage page where the relevant address of the instruction to be generated falls legal;

[0103] The generating module 204 is configured to generate the instruction to be generated based on the relevant address after completing the adjustment operation.

[0104] Optionally, the relevant address includes an instruction address; the determining module 202 is specifically configured to:

[0105] When the instruction address of the instruction to be generated falls within a data page, directly determining that the storage page where the relevant address falls is illegal;

[0106] When the instruction address of the instruction to be generated does not fall within a data page and the instruction to be generated is a jump instruction, and when the target address of the jump instruction falls within a data page, determining that the storage page where the relevant address falls is illegal; and when the target address of the jump instruction does not fall within a data page, determining that the storage page where the relevant address falls is legal;

[0107] if the instruction address of the to-be-generated instruction does not fall into the data page and the to-be-generated instruction is a sequential execution instruction, and if a preset condition is reached, determining that the storage page in which the related address falls is illegal; the preset condition is that the next instruction address of the sequential execution instruction falls into the data page, or the sequential execution instruction is a memory access instruction and the target address of the memory access instruction falls into the instruction page;

[0108] Otherwise, determining that the storage page in which the related address falls is legal.

[0109] Optionally, if the processor supports TLB attribute exceptions, the determining module 202 is specifically configured to:

[0110] set the data page in the TLB as an exception of non-executable, and set the instruction page as an exception of non-readable and non-writable;

[0111] if the to-be-generated instruction causes a TLB attribute exception, determining that the storage page in which the related address falls is illegal.

[0112] Optionally, the adjusting module 203 is specifically configured to:

[0113] if the to-be-generated instruction causes a TLB non-executable exception, generating the to-be-generated instruction at a legal instruction address.

[0114] Optionally, if the processor does not support the TLB, the adjusting module 203 is specifically configured to:

[0115] if the instruction address of the to-be-generated instruction falls into the data page, adjusting the instruction address of the to-be-generated instruction so that the instruction address falls into the instruction page;

[0116] if the instruction address of the to-be-generated instruction does not fall into the data page and the to-be-generated instruction is a jump instruction, and if the target address of the jump instruction falls into the data page, from a target address optional range of the jump instruction, reselecting a target address of the jump instruction that falls into the instruction page; and adjusting the target address of the jump instruction to the reselected target address that falls into the instruction page;

[0117] In the case where the instruction address of the instruction to be generated does not fall within the data page and the instruction to be generated is a sequential execution instruction, if the next instruction address of the sequential execution instruction falls within the data page, the sequential execution instruction is replaced with a jump instruction whose target address falls within the instruction page; if the next instruction address of the sequential execution instruction does not fall within the data page, the sequential execution instruction is a memory access instruction and the target address of the memory access instruction falls within the instruction page, then from the optional range of the target address of the memory access instruction, a target address falling within the data page is reselected for the memory access instruction; and the target address of the memory access instruction is adjusted to the reselected target address falling within the data page.

[0118] Optionally, when reselecting a target address falling into an instruction page for the jump instruction, the adjustment module 203 is further specifically configured to:

[0119] If the target address of the jump instruction does not fall within the instruction page in the optional range of the target address, then

[0120] In the case where the jump instruction is an immediate addressing instruction, replacing the jump instruction with a register jump instruction;

[0121] When the jump instruction is a register jump instruction and the next instruction address of the jump instruction is illegal, replacing the jump instruction with an immediate addressing instruction;

[0122] When the jump instruction is a register jump instruction and the next instruction address of the jump instruction is legal, the register value in the register jump instruction is reloaded to adjust the target address optional range of the jump instruction, and from the adjusted target address optional range, a target address falling into the instruction page is reselected for the jump instruction.

[0123] Optionally, when reselecting a target address falling into a data page for the memory access instruction, the adjustment module 203 is further specifically configured to:

[0124] If the target address optional range of the memory access instruction does not include a target address that falls within the data page, reloading the register value in the memory access instruction to adjust the target address optional range of the memory access instruction;

[0125] A target address falling within a data page is reselected for the memory access instruction from the adjusted target address selectable range of the memory access instruction.

[0126] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0127] Figure 84 is a block diagram illustrating a structure of an electronic device for generating instructions according to an exemplary embodiment. For example, the electronic device 400 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0128] Reference Figure 8 , electronic device 400 may include one or more of the following components: a processing component 402 , a memory 404 , a power component 406 , a multimedia component 408 , an audio component 410 , an input / output (I / O) interface 412 , a sensor component 414 , and a communication component 416 .

[0129] The processing component 402 generally controls the overall operation of the electronic device 400, such as operations associated with display, phone calls, data communications, camera operation, and recording operations. The processing component 402 may include one or more processors 420 to execute instructions to perform all or part of the steps of the above-described method. In addition, the processing component 402 may include one or more modules to facilitate interaction between the processing component 402 and other components. For example, the processing component 402 may include a multimedia module to facilitate interaction between the multimedia component 408 and the processing component 402.

[0130] The memory 404 is configured to store various types of data to support operations on the device 400. Examples of such data include instructions for any application or method operating on the electronic device 400, contact data, phone book data, messages, pictures, videos, etc. The memory 404 can be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0131] The power component 404 provides power to the various components of the electronic device 400. The power component 404 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 400.

[0132] The multimedia component 408 includes a screen that provides an output interface between the electronic device 400 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor can not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 408 includes a front camera and / or a rear camera. When the electronic device 400 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each front camera and rear camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0133] The audio component 410 is configured to output and / or input audio signals. For example, the audio component 410 includes a microphone (MIC), which is configured to receive external audio signals when the electronic device 400 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 404 or transmitted via the communication component 416. In some embodiments, the audio component 410 also includes a speaker for outputting audio signals.

[0134] I / O interface 412 provides an interface between processing component 402 and peripheral interface modules, such as a keyboard, click wheel, buttons, etc. These buttons may include but are not limited to: a home button, volume buttons, a start button, and a lock button.

[0135] The sensor assembly 414 includes one or more sensors for providing various aspects of status assessment for the electronic device 400. For example, the sensor assembly 414 can detect the open / closed state of the device 400, the relative positioning of components, such as the display and keypad of the electronic device 400. The sensor assembly 414 can also detect changes in the position of the electronic device 400 or a component of the electronic device 400, the presence or absence of user contact with the electronic device 400, the orientation or acceleration / deceleration of the electronic device 400, and temperature changes of the electronic device 400. The sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 414 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 414 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0136] The communication component 416 is configured to facilitate wired or wireless communication between the electronic device 400 and other devices. The electronic device 400 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 414 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 414 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0137] In an exemplary embodiment, the electronic device 400 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above-described methods.

[0138] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 404 including instructions, and the instructions can be executed by the processor 420 of the electronic device 400 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0139] A non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of a terminal, enables the terminal to execute the method.

[0140] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0141] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatus, or computer program products. Thus, embodiments of the present invention may take the form of a fully hardware embodiment, a fully software embodiment, or an embodiment combining software and hardware. Furthermore, embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0142] The embodiments of the present application are described with reference to the flowchart illustrations and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal devices to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal devices, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0143] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal devices to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0144] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal devices to cause a series of operational steps to be performed on the computer or other programmable terminal devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal devices provide steps for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0145] Although preferred embodiments of the present application have been described, those skilled in the art will be able to make additional modifications and variations to the embodiments without departing from the scope of the present application. Accordingly, the appended claims are intended to cover all such modifications and variations as falling within the scope of the embodiments of the present application.

[0146] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0147] The above is a detailed introduction to an instruction generation method and device, an electronic device, and a storage medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A method for generating an instruction, characterized in that: Applied to a computing device having a processor and a virtual memory, wherein instruction pages and data pages are mixedly stored in the virtual memory, the method comprises: In a process of generating instructions for a processor test program of a computing device, obtaining relevant addresses of the instructions to be generated; the relevant addresses include an instruction address, a target address, and a next instruction address of the instruction to be generated; When the instruction address of the instruction to be generated falls within a data page, directly determining that the storage page where the relevant address falls is illegal; When the instruction address of the instruction to be generated does not fall within a data page and the instruction to be generated is a jump instruction, and when the target address falls within a data page, determining that the storage page where the relevant address falls is illegal; In a case where the instruction address of the instruction to be generated does not fall within a data page and the instruction to be generated is a sequential execution instruction, if a preset condition is met, determining that the storage page where the relevant address falls is illegal; the preset condition is that the next instruction address falls within a data page, or the sequential execution instruction is a memory access instruction and the target address falls within an instruction page; the storage page includes the instruction page and the data page; In a case where the storage page where the relevant address falls is illegal, performing an adjustment operation on the instruction to be generated so as to make the storage page where the relevant address of the instruction to be generated falls legal; After completing the adjustment operation, the to-be-generated instruction is generated based on the relevant address.

2. The method according to claim 1, characterized in that The method further comprises: If the target address does not fall within a data page, determining that the storage page in which the relevant address falls is legal; In the case where the instruction address of the instruction to be generated does not fall within a data page and the instruction to be generated is a sequential execution instruction, if the preset condition is not met, it is determined that the storage page where the relevant address falls is legal.

3. The method according to claim 1, characterized in that In a case where the processor supports TLB attribute exceptions, determining whether the storage page where the relevant address of the instruction to be generated falls is illegal includes: Set the data page in the TLB to a non-executable exception and the instruction page to a non-readable and non-writable exception; When a TLB attribute exception occurs in the instruction to be generated, it is determined that the storage page where the relevant address falls is illegal.

4. The method according to claim 3, characterized in that The performing of an adjustment operation on the instruction to be generated includes: When a TLB non-executable exception occurs in the instruction to be generated, the instruction to be generated is generated at a legal instruction address.

5. The method according to claim 1 or 2, characterized in that In a case where the processor does not support TLB, performing an adjustment operation on the instruction to be generated includes: When the instruction address of the instruction to be generated falls within a data page, adjusting the instruction address of the instruction to be generated so that the instruction address falls within the instruction page; In a case where the instruction address of the instruction to be generated does not fall within the data page and the instruction to be generated is a jump instruction, if the target address of the jump instruction falls within the data page, reselecting a target address that falls within the instruction page for the jump instruction from a selectable range of target addresses of the jump instruction; and adjusting the target address of the jump instruction to the reselected target address that falls within the instruction page; In the case where the instruction address of the instruction to be generated does not fall within the data page and the instruction to be generated is a sequential execution instruction, if the next instruction address of the sequential execution instruction falls within the data page, the sequential execution instruction is replaced with a jump instruction whose target address falls within the instruction page; if the next instruction address of the sequential execution instruction does not fall within the data page, the sequential execution instruction is a memory access instruction and the target address of the memory access instruction falls within the instruction page, then from the optional range of the target address of the memory access instruction, a target address falling within the data page is reselected for the memory access instruction; and the target address of the memory access instruction is adjusted to the reselected target address falling within the data page.

6. The method according to claim 5, characterized in that In the case of reselecting a target address falling into an instruction page for the jump instruction, the method further includes: If the target address of the jump instruction does not fall within the instruction page in the optional range of the target address, then In the case where the jump instruction is an immediate addressing instruction, replacing the jump instruction with a register jump instruction; When the jump instruction is a register jump instruction and the next instruction address of the jump instruction is illegal, replacing the jump instruction with an immediate addressing instruction; When the jump instruction is a register jump instruction and the next instruction address of the jump instruction is legal, the register value in the register jump instruction is reloaded to adjust the target address optional range of the jump instruction, and from the adjusted target address optional range, a target address falling into the instruction page is reselected for the jump instruction.

7. The method according to claim 6, characterized in that In the case of reselecting a target address falling into a data page for the memory access instruction, the method further includes: If the target address optional range of the memory access instruction does not include a target address that falls within the data page, reloading the register value in the memory access instruction to adjust the target address optional range of the memory access instruction; A target address falling within a data page is reselected for the memory access instruction from the adjusted target address selectable range of the memory access instruction.

8. An instruction generating device, characterized in that: Applied to a computing device having a processor and a virtual memory, wherein instruction pages and data pages are mixedly stored in the virtual memory, the apparatus comprises: An acquisition module, configured to acquire, during a process of generating instructions for a processor test program of a computing device, relevant addresses of instructions to be generated; the relevant addresses including an instruction address, a target address, and a next instruction address of the instruction to be generated; a determination module configured to directly determine that the storage page in which the relevant address falls is illegal if the instruction address of the instruction to be generated falls within a data page; determine that the storage page in which the relevant address falls is illegal if the instruction address of the instruction to be generated does not fall within a data page and the instruction to be generated is a jump instruction and the target address falls within a data page; and determine that the storage page in which the relevant address falls is illegal if a preset condition is met if the instruction address of the instruction to be generated does not fall within a data page and the instruction to be generated is a sequential execution instruction; the preset condition is that the next instruction address falls within a data page, or that the sequential execution instruction is a memory access instruction and the target address falls within an instruction page; the storage page includes the instruction page and the data page; an adjustment module, configured to, when the storage page where the relevant address falls is illegal, perform an adjustment operation on the instruction to be generated so as to make the storage page where the relevant address of the instruction to be generated falls legal; A generating module is used to generate the instruction to be generated based on the relevant address after completing the adjustment operation.

9. An electronic device, characterized in that: The device comprises a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors, wherein the one or more programs include instructions for implementing the steps in the method according to any one of claims 1 to 7.

10. A readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method according to any one of method claims 1 to 7.

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