A PHY low-power control module based on DFI

Abstract

The application provides a DFI-based PHY low-power control module, which is connected in parallel between an MC and a PHY, and the circuit comprises a DFI signal analysis unit, a counter, a programmable control unit and an APB interface control unit connected in sequence; the APB interface control unit is connected to an MC register through an APB bus; the DFI signal analysis unit is used for monitoring the read and write data quantity between the MC and the PHY and transmitting the data quantity to the counter, and both the read data and the write data are transmitted to the counter for counting; the counting period of the counter is controlled through the programmable control unit, and the counter transmits the counting value to the programmable control unit; the programmable control unit configures corresponding low-power parameters in the MC according to the transmitted counting value, and the configuration parameters are transmitted to the register of the MC through the APB bus. According to the application, the data transmission quantity in a certain fixed period is used to dynamically adjust the low-power state of the PHY, and the low-power mode of the DDR is realized together with the controller, so that the energy is saved and the efficient data transmission is ensured.

Description

TECHNICAL FIELD

[0001] The application relates to a DFI-based PHY low-power control module and belongs to the technical field of memories. BACKGROUND

[0002] In current many circuit designs, reducing unnecessary energy loss is an important optimization index. With the improvement of user requirements and the continuous development of computers, the memory capacity and frequency of DDR are continuously improved. The power consumption of DDR is also improved. Therefore, the DDR controller provides a series of configurable interfaces for users to enter different low-power states. However, there is a lack of a module that can save power consumption while ensuring efficient data transmission. SUMMARY

[0003] The application aims to provide a DFI-based PHY low-power control module, which can meet the requirements of data reading and writing to the greatest extent on the premise of reducing power consumption.

[0004] In order to achieve the above-mentioned purpose, the application realizes the technical scheme as follows.

[0005] A DFI-based PHY low-power control module is characterized in that a circuit is connected in parallel between an MC and a PHY, the circuit comprises a DFI signal analysis unit, a counter, a programmable control unit and an APB interface control unit which are connected in sequence, and the APB interface control unit is connected to an MC register through an APB bus.

[0006] The DFI signal analysis unit is used for monitoring the number of read and write data dfi_rddata and dfi_wrdata between the MC and the PHY and transmitting the number to the counter, and the read data and the write data are both transmitted to the same counter for counting.

[0007] The counting period of the counter is controlled by the programmable control unit, and the counter transmits the counting value to the programmable control unit.

[0008] The programmable control unit configures corresponding low-power parameters in the MC according to the count value transmitted, the configuration parameters are transmitted to the register of the MC through the APB bus, and then the low-power control of the PHY is realized through the DFI interface; the specific control mode is as follows: when the MC enters the low-power state, if the data amount in the count period is higher than 50% of the data amount in the normal working state, the programmable control unit configures the wake-up time of the PHY to be lower than 256 clock cycles through the APB interface; when the data amount in the count period is lower than 50% of the data amount in the normal working state, the programmable control unit configures the wake-up time of the PHY to be higher than 256 clock cycles through the APB interface; when no read-write data operation is detected in multiple periods, the programmable control unit controls the modules except the DFI analysis unit to enter the low-power state, at this time, the DFI module functions as a flip-flop, and once read-write data appears on the DFI interface again, the whole module is woken up to enter the normal working mode.

[0009] Preferably, the programmable control unit comprises a clock control unit, an MCU, a user interface and a UART serial port; the counter transmits information to the MCU in the programmable control unit, and the MCU screens corresponding low-power parameters according to the data amount information transmitted by the counter: when the value transmitted by the counter is higher than 50% of the data amount in the normal working state, the MCU generates a wake-up time parameter lower than 256 clock cycles; when the value transmitted by the counter is lower than 50% of the data amount in the normal working state, the MCU generates a wake-up time parameter higher than 256 clock cycles, and completes the mapping of the address and data of the MCU to the APB interface control unit, and transmits the mapped low-power configuration parameters to the APB bus through the APB interface control unit, and then transmits the low-power configuration parameters to the register of the MC through the APB bus.

[0010] Preferably, there is signal interaction between the MCU and the clock control unit, the count value of the counter in the count period is transmitted to the clock control unit through a signal line, and the clock control unit dynamically adjusts the running frequency of the MCU according to the size of the count value; when the value transmitted by the counter is lower than 50% of the data amount in the normal working state, when the count value is small, the clock control unit reduces the running frequency of the MCU.

[0011] Preferably, the user interface is used for modifying the related parameters in the MCU; and the UART serial port is used for completing the communication with the upper computer.

[0012] The application has the advantages that the low-power state of the PHY is dynamically adjusted according to the data transmission amount in a fixed period, the low-power mode of the DDR is realized together with the controller (MC), the energy is saved, and the efficient transmission of data is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute a part of this specification, illustrate embodiments of the present application and are used to explain the present application, but do not limit the present application.

[0014] Figure 1 It is a schematic diagram of the structure of the present application.

[0015] Figure 2 It is a schematic diagram of the structure of the programmable control unit of the present application. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0017] A PHY low-power control module based on DFI, which is composed of the following parts: a DFI signal analysis unit, a counter, a programmable control unit (controller), and an APB interface control unit (APB Block).

[0018] The low-power control module adds an additional circuit between the MC and the PHY, which is a DFI signal analysis unit. The DFI signal analysis unit can monitor the number of read and write data (dfi_rddata and dfi_wrdata) between the MC and the PHY and deliver the number to the rear counter. Both the read data and the write data are delivered to the same counter for counting. The counting period of the counter is controlled by the programmable control unit. The counter delivers the counting value to the programmable control unit. The programmable control unit configures the corresponding low-power parameters in the MC according to the delivered counting value. The configuration parameters are delivered to the registers of the MC through the APB bus and then to the PHY through the DFI interface to realize low-power control of the PHY. When the MC enters the low-power state, if the data volume is large in the counting period, the programmable control unit configures a shorter wake-up time for the PHY through the APB interface. When the data volume is small in the counting period, the programmable control unit configures a longer wake-up time for the PHY through the APB interface. When no read and write data operation is detected in multiple periods, the entire low-power module, except the DFI analysis unit, will enter the low-power state under the operation of the programmable control unit. At this time, the DFI module acts as a flip-flop. Once read and write data appear on the DFI interface again, the entire module will be awakened to enter the normal working mode. Setting the low-power mode for the low-power control module itself can maximize the energy consumption of the entire system and avoid the situation that the DDR has entered the low-power mode, but the low-power module is still active, causing unnecessary energy consumption.

[0019] The programmable control unit includes a clock control unit, an MCU, a user interface and a UART serial port. The count value is transmitted from the counter to the MCU in the programmable control unit, the MCU filters out the corresponding low-power parameter according to the value, and then completes the mapping of the address and data of the MCU to the APB interface control unit through internal logic processing. The mapped low-power configuration parameters are transmitted to the APB bus through the APB interface control unit, and then to the register of the MCU. In addition, there is signal interaction between the MCU and the clock control unit. The count value of the counter in the count period is transmitted to the clock control unit through the signal line, and the clock control unit dynamically adjusts the running frequency of the MCU according to the size of the count value. When the count value is small, the clock control unit reduces the running frequency of the MCU to reduce the power consumption of the whole system. In addition, the MCU also has a user interface (User interface), through which the user can modify the relevant parameters in the MCU: modify the low-power configuration parameters, and the specific MCU clock frequency corresponding to different count values. In order to facilitate operation, a UART serial port is additionally added behind the user interface, through which communication with the host computer can be realized, that is, the input of the MCU configuration command and the display of the internal running state of the MCU can be realized directly through the serial port.

[0020] The application is expanded according to the framework of the DFI specification, has applicability, and different DDRs can adopt this configuration. Moreover, the low-power configuration parameters of the DDR are dynamically managed according to the number of data read and write in the period, the power consumption is reduced while the transmission efficiency is improved. The low-power control circuit itself also has a low-power state, avoiding the increase of power consumption caused by the additional low-power control circuit. The application also adds a user interface and a UART serial port to the programmable control unit, facilitating communication with the host computer.

[0021] Finally, it should be noted that: the above only describes the preferred embodiments of the application and is not used to limit the application. Although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some technical features. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the application shall be included in the protection scope of the application.

Claims

1. A low-power PHY control module based on DFI, characterized in that, A circuit is connected in parallel between the MC and the PHY. The circuit includes a DFI signal parsing unit, a counter, a programmable control unit, and an APB interface control unit connected in sequence. The APB interface control unit is connected to the MC register via the APB bus. The DFI signal parsing unit is used to monitor the amount of read data dfi_rddata and write data dfi_wrdata between MC and PHY, and passes it to a counter. Both read data and write data are passed to the same counter for counting. The counting period of the counter is controlled by a programmable control unit, and the counter transmits the count value to the programmable control unit. The programmable control unit (PCU) configures the corresponding low-power parameters in the MC based on the incoming count value. These configuration parameters are transmitted to the MC's registers via the APB bus, and then to the PHY via the DFI interface to achieve low-power control of the PHY. The specific control method is as follows: When the MC enters a low-power state, if the data volume within the counting cycle is higher than 50% of the normal operating data volume, the PCU configures a wake-up time of less than 256 clock cycles for the PHY via the APB interface. When the data volume within the counting cycle is lower than 50% of the normal operating data volume, the PCU configures a wake-up time of more than 256 clock cycles for the PHY via the APB interface. When no read / write operations are detected within multiple cycles, the PCU controls all modules except the DFI signal parsing unit to enter a low-power state. In this state, the DFI signal parsing unit acts as a trigger; once read / write data is detected again on the DFI interface, it wakes up the PHY low-power control module and returns it to normal operating mode.

2. The DFI-based PHY low-power control module according to claim 1, characterized in that, The programmable control unit includes a clock control unit, an MCU, a user interface, and a UART serial port. The counter transmits information to the MCU inside the programmable control unit. The MCU filters the corresponding low-power parameters based on the amount of data transmitted by the counter: when the value transmitted by the counter is higher than 50% of the normal operating data amount, the MCU generates a wake-up time parameter of less than 256 clock cycles; when the value transmitted by the counter is lower than 50% of the normal operating data amount, the MCU generates a wake-up time parameter of more than 256 clock cycles. The MCU completes the address and data mapping from the MCU to the APB interface control unit, and transmits the mapped low-power configuration parameters to the APB bus through the APB interface control unit, and then to the MC's registers through the APB bus.

3. The DFI-based PHY low-power control module according to claim 2, characterized in that, There is signal interaction between the MCU and the clock control unit. During the counting cycle, the counter value is transmitted to the clock control unit through the signal line. The clock control unit dynamically adjusts the operating frequency of the MCU according to the value of the counter. When the value transmitted by the counter is less than 50% of the normal operating data, the clock control unit will reduce the MCU operating frequency.

4. The DFI-based PHY low-power control module according to claim 2, characterized in that, The user interface is used to modify relevant parameters inside the MCU; the UART serial port is used to complete communication with the host computer.

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