CMOS image sensor and method for forming the same

Abstract

A CMOS image sensor and a method for forming the same include: providing a semiconductor substrate; forming a buried channel doped region within the semiconductor substrate; forming a gate on the surface of the semiconductor substrate; forming a lightly doped drain region, the lightly doped drain region being located within the semiconductor substrate on both sides of the gate; forming sidewalls on the sidewall surfaces of the gate to obtain a gate structure; forming a source region and a drain region, the source region and the drain region being located within the semiconductor substrate on both sides of the gate structure; wherein the doping type of the buried channel doped region is consistent with the doping type of the lightly doped drain region, and the doping concentration of the buried channel doped region is less than the doping concentration of the lightly doped drain region; and in a direction parallel to the device channel, the first doped region is larger than the drain region and covers the drain region. The present invention can reduce carrier recombination luminescence and improve the imaging quality of the image sensor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a CMOS image sensor and a method for forming the same. Background Art

[0002] An image sensor is a semiconductor device that converts optical images into electrical signals. Due to the advantages of low power consumption and high signal-to-noise ratio, the complementary metal oxide semiconductor image sensor (CIS) has been widely used in various fields.

[0003] In smaller advanced process nodes, in order to suppress the short channel effect caused by short transistor gate length, methods such as reducing the injection energy and increasing the injection dose are usually adopted to limit the injection range to a position closer to the channel surface and increase the effective dopant concentration.

[0004] However, this method increases the electric field strength, separating and accelerating intrinsically generated carriers within the semiconductor while also activating various defects. In locations with strong electric fields, particularly at the drain junction boundary with a high bias voltage, a large number of carriers are generated and accelerated by the strong electric field. Collision generates more secondary carriers, which recombine with inversion layer carriers in the channel to emit light, affecting the image sensor's imaging performance. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a CMOS image sensor and a method for forming the same, which can reduce carrier recombination luminescence and improve the imaging quality of the image sensor.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a CMOS image sensor, comprising: providing a semiconductor substrate; forming a buried channel doped region in the semiconductor substrate; forming a gate on the surface of the semiconductor substrate; forming a lightly doped drain region, wherein the lightly doped drain region is located in the semiconductor substrate on both sides of the gate; forming sidewalls on the sidewall surfaces of the gate to obtain a gate structure; forming a source region and a drain region, wherein the source region and the drain region are respectively located in the semiconductor substrate on both sides of the gate structure; wherein the doping type of the buried channel doped region is consistent with the doping type of the lightly doped drain region, and the doping concentration of the buried channel doped region is less than the doping concentration of the lightly doped drain region; the buried channel doped region includes a first doped region located in the semiconductor substrate on one side of the drain region, the first doped region has an overlapping area with the lightly doped drain region on one side of the drain region, and the boundary of the first doped region extends to below the gate; and in an extension direction parallel to the device channel, the first doped region is larger than the drain region and covers the drain region.

[0007] Optionally, the ion implantation depth for forming the first doped region is greater than or equal to the ion implantation depth for forming the lightly doped drain region.

[0008] Optionally, the length of the portion of the first doped region extending below the gate does not exceed a first preset proportional length of the gate; wherein the direction of the length is consistent with the extension direction of the device channel.

[0009] Optionally, the first preset ratio used to calculate the first preset ratio length is selected from 1 / 6 to 1 / 3.

[0010] Optionally, the first preset ratio is determined based on the length of the gate and the device turn-on voltage of the CMOS image sensor; wherein, the larger the length of the gate, the smaller the first preset ratio used to calculate the first preset ratio length or remains unchanged; the higher the device turn-on voltage, the larger the first preset ratio length of the gate structure.

[0011] Optionally, in a direction parallel to the surface of the semiconductor substrate and perpendicular to an extension direction of the device channel, the first doped region is larger than the drain region and covers the drain region.

[0012] Optionally, the parameters of the buried channel doping region formation process are selected from one or more of the following: the implanted ions include phosphorus ions; the implantation energy is 10KeV to 50KeV; the implantation dose is 1E12atom / cm 2 to 5E12 atoms / cm 2 .

[0013] Optionally, the buried channel doped region also includes a second doped region located in the semiconductor substrate on one side of the source region, the second doped region has an overlapping area with the lightly doped drain region on one side of the source region, and the boundary of the second doped region extends to below the gate; wherein, in the extension direction parallel to the device channel, the second doped region is larger than the source region and covers the source region.

[0014] Optionally, the second doping region and the first doping region are formed by the same ion implantation process.

[0015] Optionally, the length of the portion of the first doped region extending below the gate does not exceed a second preset proportional length of the gate, and the length of the portion of the second doped region extending below the gate does not exceed a third preset proportional length of the gate; wherein the direction of the length is consistent with the extension direction of the device channel.

[0016] Optionally, the second preset ratio used to calculate the second preset ratio length is selected from 1 / 6 to 1 / 3, and the third preset ratio used to calculate the third preset ratio length is selected from 1 / 6 to 1 / 3.

[0017] Optionally, the second preset ratio is equal to the third preset ratio.

[0018] Optionally, the second preset proportional length is determined based on the length of the gate and the device turn-on voltage of the CMOS image sensor; wherein, the larger the length of the gate, the smaller the second preset proportional length used to calculate the second preset proportional length or remains unchanged, and the smaller the third preset proportional length used to calculate the third preset proportional length or remains unchanged; the higher the device turn-on voltage, the larger the second preset proportional length of the gate structure, and the larger the third preset proportional length of the gate.

[0019] Optionally, in a direction parallel to the surface of the semiconductor substrate and perpendicular to the extension direction of the device channel, the second doped region is larger than the source region and covers the source region.

[0020] To solve the above technical problems, an embodiment of the present invention provides a CMOS image sensor, comprising: a semiconductor substrate; a buried channel doped region, located in the semiconductor substrate; a gate structure, including a gate and a sidewall located on the sidewall surface of the gate, located on the surface of the semiconductor substrate; a lightly doped drain region, located in the semiconductor substrate on both sides of the gate; a source region and a drain region, respectively located in the semiconductor substrate on both sides of the gate structure; wherein the doping type of the buried channel doped region is consistent with the doping type of the lightly doped drain region, and the doping concentration of the buried channel doped region is less than the doping concentration of the lightly doped drain region; the buried channel doped region includes a first doped region located in the semiconductor substrate on one side of the drain region, the first doped region has an overlapping area with the lightly doped drain region on one side of the drain region, and the boundary of the first doped region extends to below the gate; in an extension direction parallel to the device channel, the first doped region is larger than the drain region and covers the drain region.

[0021] Optionally, the ion implantation depth for forming the first doped region is greater than or equal to the ion implantation depth for forming the lightly doped drain region.

[0022] Optionally, the length of the portion of the first doped region extending below the gate does not exceed a first preset proportional length of the gate; wherein the direction of the length is consistent with the extension direction of the device channel.

[0023] Optionally, the first preset ratio is determined based on the length of the gate and the device turn-on voltage of the CMOS image sensor; wherein, the larger the length of the gate, the smaller the first preset ratio used to calculate the first preset ratio length or remains unchanged; the higher the device turn-on voltage, the larger the first preset ratio length of the gate.

[0024] Optionally, the buried channel doped region also includes a second doped region located in the semiconductor substrate on one side of the source region, the second doped region has an overlapping area with the lightly doped drain region on one side of the source region, and the boundary of the second doped region extends to below the gate; wherein, in the extension direction parallel to the device channel, the second doped region is larger than the source region and covers the source region.

[0025] Optionally, the second doping region and the first doping region are formed by the same ion implantation process.

[0026] Optionally, the length of the portion of the first doped region extending below the gate does not exceed a second preset proportional length of the gate, and the length of the portion of the second doped region extending below the gate does not exceed a third preset proportional length of the gate; wherein the direction of the length is consistent with the extension direction of the device channel.

[0027] Optionally, the second preset ratio is determined based on the length of the gate and the device turn-on voltage of the CMOS image sensor; wherein, the larger the length of the gate, the smaller the second preset ratio used to calculate the second preset ratio length is or remains unchanged, and the smaller the third preset ratio used to calculate the third preset ratio length is or remains unchanged; the higher the device turn-on voltage, the larger the second preset ratio length of the gate, and the larger the third preset ratio length of the gate.

[0028] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0029] In an embodiment of the present invention, a buried channel doping region is formed, which has the same doping type as the lightly doped drain region, has an overlapping area and a lower doping concentration, and has a boundary extending to the bottom of the gate. The buried channel doping region is longer than the drain region and covers the drain region. A triple ion implantation concentration gradient of "maximum drain region doping concentration - relatively high lightly doped drain region doping concentration - relatively low buried channel doping region doping concentration - minimum channel well injection doping concentration" can be formed between the drain and the channel center, effectively expanding the drain junction range, significantly reducing the electric field strength at the drain boundary, and thereby reducing the number of secondary carriers at the drain boundary, reducing the probability of carrier radiation recombination, reducing carrier recombination luminescence, and improving the imaging quality of the image sensor.

[0030] Furthermore, the ion implantation depth for forming the first doped region is greater than or equal to the ion implantation depth for forming the lightly doped drain region, so that the first doped region surrounds the lightly doped drain region in depth, and a triple ion implantation concentration gradient can also be formed in the direction perpendicular to the surface of the semiconductor substrate, thereby further reducing carrier recombination luminescence and improving the imaging quality of the image sensor.

[0031] Furthermore, the length of the portion of the first doped region extending below the gate does not exceed a first preset proportional length of the gate, thereby avoiding shortening the effective channel length of the transistor and adversely affecting the power consumption and switching ratio of the device.

[0032] Furthermore, the length of the portion of the first doped region extending below the gate does not exceed a second preset proportional length of the gate, and the length of the portion of the second doped region extending below the gate does not exceed a third preset proportional length of the gate, thereby avoiding shortening the effective channel length of the transistor and avoiding adverse effects on the power consumption and switching ratio of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a schematic diagram of the cross-sectional structure of a CMOS image sensor in the prior art;

[0034] Figure 2 is a flow chart of a method for forming a CMOS image sensor according to an embodiment of the present invention;

[0035] Figures 3 to 5 1 is a schematic diagram of a device cross-sectional structure corresponding to each step in the method for forming the first CMOS image sensor according to an embodiment of the present invention;

[0036] Figure 6 FIG. 1 is a schematic diagram of a cross-sectional structure of a second CMOS image sensor according to an embodiment of the present invention;

[0037] Figure 7 1 is a schematic diagram of a mapping pattern of radiation power and threshold voltage based on different electric field buffer widths in an embodiment of the present invention;

[0038] Figure 8 1 is a schematic diagram of a mapping pattern of radiation power and threshold voltage based on different buried channel doses in an embodiment of the present invention;

[0039] Figure 9 This is a schematic diagram of a mapping pattern of threshold voltage and radiation power based on buffer length and channel length in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] As image sensor requirements increase, along with the demands for faster readout and processing of image signals, the pixel size in sensors is shrinking, and the process nodes used to manufacture image sensors are continuously decreasing. To maintain a certain transistor on / off ratio, advanced small-scale process nodes simultaneously reduce the gate length, gate width, and gate oxide thickness of transistors. This reduction in doping depth and increased doping concentration simultaneously maintains the transistor's threshold voltage. For conventional circuits, this approach ensures similar signal-to-noise ratio performance with smaller transistors, resulting in higher switching speeds.

[0041] In a CIS, each pixel in the sensor has a series of transistors that provide reset, readout, and other functions. The decreasing size of image pixels has forced the design size of these transistors to gradually decrease. Furthermore, image sensors with smaller pixels require larger pixel arrays, which in turn requires greater signal processing capabilities. Therefore, the performance requirements of the sensor's peripheral circuitry also force image sensors to be manufactured using smaller process nodes to improve transistor performance.

[0042] However, using smaller process nodes will bring about problems such as short channel effects.

[0043] Reference Figure 1 , Figure 1 This is a schematic diagram of the cross-sectional structure of a CMOS image sensor in the prior art.

[0044] Specifically, a gate structure 120 is formed on the surface of the semiconductor substrate 100, a source-drain doped region 110 is formed in the semiconductor substrate 100, and then electrodes respectively connected to the gate structure 120, the source, the drain, and a ground electrode are provided to promote carrier movement.

[0045] The inventors of this invention have discovered that measures taken to suppress the short-channel effect often increase the electric field strength, and excessively strong electric fields can exacerbate the problem of carrier recombination and luminescence. Because pixels in image sensors are highly sensitive to light, the presence of luminescent sites in the signal processing circuitry can cause interference during the pixel integration process, masking some of the actual light signal and affecting image quality.

[0046] Specifically, in the process of reducing transistor size, in order to ensure the normal use of the original circuit design, it is necessary to adjust the energy and dose of the transistor well injection and source and drain injection. By reducing the injection energy and increasing the injection dose, the injection range can be limited to a position closer to the channel surface, and the effective dopant concentration can be increased, thereby better suppressing the short channel effect caused by the reduction of transistor gate length and maintaining a certain threshold voltage. The process of suppressing the short channel effect of small-size process nodes can maintain the normal operation of the transistor circuit, but it also brings a stronger electric field strength.

[0047] Furthermore, excessively strong electric fields can exacerbate the problem of carrier recombination and luminescence. Specifically, they separate and accelerate intrinsically generated carriers within the semiconductor, while activating various defects. Consequently, large numbers of electrons and holes are often generated at locations with strong electric fields, particularly at the drain junction boundary with a large bias voltage. These carriers are accelerated by the strong electric field, colliding to produce more secondary carriers, which then recombine with inversion layer carriers in the channel to emit light. This process is more likely to occur in transistors with shorter gate lengths because the channel barrier is lowered due to the short channel effect, allowing secondary carriers a longer free path and increasing the probability of recombination. In image sensors, pixels are designed to have high sensitivity. The faint light emitted by peripheral circuits can easily be captured by the pixels, interfering with the image.

[0048] One existing solution for reducing the emission of transistors in signal processing circuits is to reduce the impact of the short channel effect by increasing the gate length or increasing the channel well implant concentration. However, increasing the gate length reduces the speed of the transistor and also increases the silicon area occupied by the transistor to a certain extent.

[0049] Another existing solution for reducing transistor luminescence in signal processing circuits involves reducing the source-drain voltage difference or increasing the gate voltage to more than half the source-drain voltage difference. However, increasing the well implant concentration leads to more severe gate-induced drain leakage (GIDL), which can, to some extent, enhance luminescence.

[0050] In an embodiment of the present invention, a buried channel doping region is formed, which has the same doping type as the lightly doped drain (LDD), has an overlapping area and a lower doping concentration, and has a boundary extending to the bottom of the gate. The buried channel doping region is longer than the drain region and covers the drain region. A triple ion implantation concentration gradient of "maximum drain doping concentration - relatively high doping concentration of the lightly doped drain region - relatively low doping concentration of the buried channel doping region - minimum channel well injection doping concentration" can be formed between the drain and the channel center, effectively expanding the drain junction range, significantly reducing the electric field strength at the drain boundary, and thereby reducing the number of secondary carriers at the drain boundary, reducing the probability of carrier radiation recombination, reducing carrier recombination luminescence, and improving the imaging quality of the image sensor.

[0051] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0052] Reference Figure 2 , Figure 2 1 is a flow chart of a method for forming a CMOS image sensor according to an embodiment of the present invention. The method for forming a CMOS image sensor may include steps S21 to S26:

[0053] Step S21: providing a semiconductor substrate;

[0054] Step S22: forming a buried channel doping region in the semiconductor substrate;

[0055] Step S23: forming a gate on the surface of the semiconductor substrate;

[0056] Step S24: forming a lightly doped drain region, wherein the lightly doped drain region is located in the semiconductor substrate on both sides of the gate;

[0057] Step S25: forming a sidewall spacer on the sidewall surface of the gate to obtain a gate structure;

[0058] Step S26: forming a source region and a drain region, wherein the source region and the drain region are respectively located in the semiconductor substrate on both sides of the gate structure.

[0059] The following combination Figures 3 to 5 Each of the above steps is explained.

[0060] Figures 3 to 5 It is a schematic diagram of the device cross-sectional structure corresponding to each step in the method for forming the first CMOS image sensor in an embodiment of the present invention.

[0061] Reference Figure 3 , providing a semiconductor substrate 200, forming a buried channel doping region 230 in the semiconductor substrate 200, and forming a gate on the surface of the semiconductor substrate 200.

[0062] The gate may include a gate dielectric layer 221 and a gate layer 222 located on the surface of the gate dielectric layer 221 .

[0063] The material of the gate dielectric layer 221 may be silicon oxide, such as SiO 2 , and the material of the gate layer 222 may be polysilicon or other appropriate materials.

[0064] In a specific implementation, the semiconductor substrate 200 can be a silicon substrate, or the material of the semiconductor substrate 200 can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The semiconductor substrate 200 can also be a silicon substrate on an insulator surface or a germanium substrate on an insulator surface, or a substrate on which an epitaxy layer (Epi layer) is grown. In a non-limiting specific embodiment, the semiconductor substrate 200 can be a lightly doped semiconductor substrate, and the doping type is opposite to that of the drain region. Specifically, deep well doping (Deep Well Implant) can be achieved by performing ion implantation on the semiconductor substrate 200.

[0065] Reference Figure 4 , forming a lightly doped drain region 240, the lightly doped drain region 240 is located in the semiconductor substrate 200 on both sides of the gate, and forming a sidewall spacer 223 on the sidewall surface of the gate to obtain a gate structure 220.

[0066] It should be pointed out that in another specific implementation of the embodiment of the present invention, the side wall 223 may include two processes, the first process is an offset side wall formed before forming the lightly doped drain region 240, and the second process is a second layer outer side wall formed after forming the lightly doped drain region 240. Specifically, the offset side wall can be used to control the injection area of the lightly doped drain region 240, and the second layer outer side wall formed subsequently can control the injection area of the source region and the drain region.

[0067] In a specific implementation, the doping type of the buried channel doping region 230 is consistent with the doping type of the lightly doped drain region 240 .

[0068] Taking the CIS device type as an N-type metal-oxide-semiconductor (NMOS) device as an example, the doping type of the lightly doped drain region 240 is N-type, and the doping type of the buried channel doping region 230 is also N-type, and the doping ions can include, for example, P, As or Sb.

[0069] In a specific implementation, the doping concentration of the buried channel doping region 230 may be lower than the doping concentration of the lightly doped drain region 240 .

[0070] In an embodiment of the present invention, a buried channel doping region 230 having the same doping type as the lightly doped drain region 240 but a lower doping concentration is formed, so that an ion implantation concentration gradient of "lightly doped drain region with higher doping concentration - buried channel doping region with lower doping concentration" can be formed.

[0071] Reference Figure 5 , forming a source region 210 and a drain region 211 , wherein the source region 210 and the drain region 211 are respectively located in the semiconductor substrate 200 on both sides of the gate structure 220 .

[0072] Furthermore, the buried channel doped region 230 includes a first doped region located in the semiconductor substrate on one side of the drain region 211 .

[0073] That is, Figure 5 In the device shown, the buried channel doped region (first doped region) 230 is formed only on a single side of the gate structure 220 .

[0074] In a specific implementation, the buried channel doping region (first doping region) 230 has an overlapping area with the lightly doped drain region 240 on one side of the drain region 211, and the boundary of the buried channel doping region (first doping region) 230 extends to the bottom of the gate 222. In the extension direction parallel to the device channel, the buried channel doping region (first doping region) 230 is larger than the drain region 211 and covers the drain region 211.

[0075] Furthermore, the ion implantation depth for forming the buried channel doping region (first doping region) 230 is greater than or equal to the ion implantation depth for forming the lightly doped drain region 240 .

[0076] In an embodiment of the present invention, since the doping concentration of the drain region 211 is greater than the doping concentration of the lightly doped drain region 240, and the doping concentration of the lightly doped drain region 240 is greater than the doping concentration of the buried channel doping region (first doping region) 230, an ion injection concentration gradient of "the drain region 211 has the highest doping concentration - the lightly doped drain region 240 has a relatively high doping concentration - the buried channel doping region (first doping region) 230 has a relatively low doping concentration" can be formed.

[0077] In the extending direction parallel to the device channel, the buried channel doping region (first doping region) 230 is larger than the drain region 211 , thereby reducing the electric field strength of the junction region outside the drain region 211 .

[0078] Furthermore, in a direction parallel to the surface of the semiconductor substrate 200 and perpendicular to the extension direction of the device channel, the buried channel doping region (first doping region) 230 may be larger than the drain region 211 and cover the drain region 211 .

[0079] As a non-limiting example, taking a CIS with a gate 222 having a length of 0.4 μm as an example, the single side length of the buried channel doping region (first doping region) 230 may be 40 nm to 80 nm longer than the single side length of the drain region 211 .

[0080] That is, Figure 5 In the embodiment, the widths of d1 and d2 may be 20 nm to 40 nm, for example, 30 nm.

[0081] The length of the gate 222 may be determined according to the critical dimension (CD) of the CIS device. The CD refers to the pattern processing accuracy used to evaluate and control the process in the integrated circuit photomask manufacturing and photolithography process.

[0082] Furthermore, the ion implantation depth for forming the buried channel doping region (first doping region) 230 may be greater than or equal to the ion implantation depth for forming the lightly doped drain region 240 .

[0083] As a non-limiting example, taking a CIS with a gate 222 length of 0.4 μm as an example, the injection depth of the lightly doped drain region 240 can be 0.06 μm, and the ion injection depth of the buried channel doping region (first doping region) 230 can be 0.06 μm or greater than 0.06 μm.

[0084] Furthermore, parameters of the process for forming the buried channel doping region (first doping region) 230 may be selected from one or more of the following:

[0085] The implanted ions include phosphorus ions;

[0086] The implantation energy is 10KeV to 50KeV;

[0087] The injection dose is 1E12atom / cm 2 to 5E12 atoms / cm 2 .

[0088] In a non-limiting embodiment, parameters of the process for forming the lightly doped drain region 240 may be selected from one or more of the following:

[0089] The implanted ions include phosphorus ions;

[0090] The injection energy is less than or equal to 30 KeV, and the injection energy of the buried channel doping region (first doping region) 230 is greater than or equal to the injection energy of the lightly doped drain region 240;

[0091] The injection dose is 1E13 atom / cm 2 to 1E14 atoms / cm 2 .

[0092] In an embodiment of the present invention, the ion implantation depth for forming the buried channel doping region (first doping region) 230 is greater than or equal to the ion implantation depth for forming the lightly doped drain region 240, so that the buried channel doping region (first doping region) 230 surrounds the lightly doped drain region 240 in depth, and a triple ion implantation concentration gradient can also be formed in a direction perpendicular to the surface of the semiconductor substrate 200, thereby further reducing carrier recombination luminescence and improving the imaging quality of the image sensor.

[0093] Furthermore, the length of the portion of the buried channel doping region (first doping region) 230 extending below the gate 222 does not exceed a first preset proportional length of the gate 222; wherein the direction of the length is consistent with the extension direction of the device channel.

[0094] It should be pointed out that when only single-sided buried channel doping is set, the designed injection area can be increased compared to double-sided buried channel doping. However, since the light-emitting devices are mostly short-channel devices, a longer buried channel injection will further deteriorate the shutdown characteristics of the transistor. Therefore, the injection area of the buried channel doping region (first doping region) 230 cannot be increased indefinitely.

[0095] Furthermore, the first preset ratio can be determined based on the length of the gate 222 and the device turn-on voltage of the CMOS image sensor; wherein, the longer the length of the gate 222 is, the smaller the first preset ratio used to calculate the first preset ratio length is; and the higher the device turn-on voltage is, the larger the first preset ratio length of the gate 222 is.

[0096] It should be noted that, in a specific implementation, the larger the length of the gate 222, the smaller the first preset ratio can be, so that the first preset ratio length remains unchanged; or, the larger the length of the gate 222, the first preset ratio can remain unchanged, so that the first preset ratio length increases.

[0097] Furthermore, the first preset ratio used to calculate the first preset ratio length may be selected from 1 / 6 to 1 / 3.

[0098] It should be noted that the first preset ratio is used to indicate the distance between the buried channel doping region (first doping region) 230 and the lightly doped drain region 240 , and should not be too large or too small.

[0099] Specifically, the distance between the buried channel doping region (first doping region) 230 and the lightly doped drain region 240 should be greater than or equal to the first preset distance (such as 50nm), which can significantly reduce the electric field effect; the distance between the buried channel doping region (first doping region) 230 and the lightly doped drain region 240 should be less than the second preset distance (such as 1 / 3 of the gate length), which can avoid the short channel effect affecting the transistor turn-on voltage.

[0100] As a non-limiting example, taking a CIS in which the length of the gate 222 is 0.4 μm, the first preset ratio can be 1 / 6 to 1 / 3. After calculation, 1 / 6×0.4 μm=0.067 μm, 1 / 3×0.4 μm=0.13 μm, the first preset ratio length of the gate 222 can be 0.067 μm to 0.13 μm.

[0101] In an embodiment of the present invention, the length of the portion of the buried channel doping region (first doping region) 230 extending below the gate 222 does not exceed a first preset proportional length of the gate 222, thereby avoiding shortening the effective channel length of the transistor and avoiding adverse effects on the power consumption and switching ratio of the device.

[0102] Specifically, an excessively long buried channel doping region (first doping region) 230 will cause the effective channel length of the CIS to be too short, thereby amplifying the shutdown current of the CIS, increasing the power consumption of the CIS and reducing the switching ratio; an excessively short buried channel doping region (first doping region) 230 will cause the effective channel length of the CIS to be too long, causing the turn-on voltage of the CIS to be significantly reduced, which may cause problems with circuit function.

[0103] In an embodiment of the present invention, a buried channel doping region (first doping region) 230 is formed on one side of the drain region 211, which has the same doping type as the lightly doped drain region 240, has an overlapping area and a lower doping concentration, and has a boundary extending to the bottom of the gate 222. The buried channel doping region (first doping region) 230 is longer than the drain region 211 and covers the drain region 211. A triple ion implantation concentration gradient of "maximum doping concentration of drain region 211 - relatively high doping concentration of lightly doped drain region 240 - relatively low doping concentration of buried channel doping region (first doping region) 230 - minimum channel well injection doping concentration" can be formed between the drain and the channel center, effectively expanding the drain junction range, significantly reducing the electric field strength at the drain boundary, thereby reducing the number of secondary carriers at the drain boundary, reducing the probability of carrier radiation recombination, reducing carrier recombination luminescence, and improving the imaging quality of the image sensor.

[0104] Reference Figure 6 , Figure 6 FIG2 is a schematic diagram of a cross-sectional structure of a second CMOS image sensor according to an embodiment of the present invention. The following describes the parts that are different from the first CMOS image sensor.

[0105] In the second CMOS image sensor, the buried channel doped region includes a first doped region 330 located in the semiconductor substrate 200 on one side of the drain region 211 , and also includes a second doped region 331 located in the semiconductor substrate 200 on one side of the source region 210 .

[0106] The second doped region 331 has an overlapping area with the lightly doped drain region 240 on one side of the source region 210, and the boundary of the second doped region 331 extends to the bottom of the gate 222; in the extension direction parallel to the device channel, the second doped region 331 is larger than the source region 210 and covers the source region 210.

[0107] Furthermore, the second doping region 331 and the first doping region 330 may be formed by using the same ion implantation process.

[0108] Furthermore, in a direction parallel to the surface of the semiconductor substrate and perpendicular to the extension direction of the device channel, the second doped region 331 may be larger than the source region 210 and cover the source region 210 .

[0109] In the embodiment of the present invention, the specific formation process of the second doping region 331 can refer to the formation steps and processes of the first doping region 330 mentioned above, and will not be repeated here.

[0110] Furthermore, the length D2 of the portion of the first doped region 331 extending below the gate 222 does not exceed the second preset proportional length of the gate 222, and the length D3 of the portion of the second doped region 330 extending below the gate 222 does not exceed the third preset proportional length of the gate 222; wherein the direction of the length is consistent with the extension direction of the device channel.

[0111] In an embodiment of the present invention, the length of the portion of the first doped region 330 extending below the gate 222 does not exceed the second preset proportional length of the gate 222, and the length of the portion of the second doped region 331 extending below the gate 222 does not exceed the third preset proportional length of the gate 222, thereby avoiding shortening the effective channel length of the transistor and avoiding adverse effects on the power consumption and switching ratio of the device.

[0112] Specifically, excessively long first and second doped regions 330 and 331 shorten the effective channel length of the CIS, thereby amplifying the CIS's off-current, increasing CIS power consumption, and reducing the on-off ratio. Furthermore, excessively long first and second doped regions 330 and 331 shorten the effective channel length of the CIS, significantly reducing the CIS's turn-on voltage and potentially causing circuit functionality issues. Excessively short first and second doped regions 330 and 331 lead to large concentration gradients outside the source and drain regions, resulting in insignificant electric field reduction and, consequently, inability to reduce luminous intensity.

[0113] Furthermore, the second preset proportional length is determined based on the length of the gate 222 and the device turn-on voltage of the CMOS image sensor; wherein, the larger the length of the gate 222, the smaller the second preset proportional length used to calculate the second preset proportional length or remains unchanged, and the smaller the third preset proportional length used to calculate the third preset proportional length or remains unchanged; the higher the device turn-on voltage, the larger the second preset proportional length of the gate 222, and the larger the third preset proportional length of the gate.

[0114] Furthermore, the second preset ratio used to calculate the second preset ratio length may be selected from 1 / 6 to 1 / 3, and the third preset ratio used to calculate the third preset ratio length may be selected from 1 / 6 to 1 / 3.

[0115] As a non-limiting example, taking the CIS in which the length of the gate 222 is 0.4μm as an example, the second preset ratio can be 1 / 6 to 1 / 3. After calculation, 1 / 6×0.4μm=0.067μm, 1 / 3×0.4μm=0.13μm, the second preset ratio length of the gate 222 can be 0.067μm to 0.13μm. Similarly, the third preset ratio length of the gate 222 can also be 0.067μm to 0.13μm.

[0116] Furthermore, the second preset ratio and the third preset ratio may be equal, which is beneficial to improving the morphological symmetry and performance stability of the device.

[0117] For more details about the second preset ratio and the third preset ratio, please refer to the above description about the first preset ratio, which will not be repeated here.

[0118] In the embodiment of the present invention, a first doping region 330 and a second doping region 331 are formed on both sides of the source region 210 and the drain region 211, which have the same doping type as the lightly doped drain region 240, have an overlapping area and a lower doping concentration, and have a boundary extending to the bottom of the gate 222. The first doping region 330 is longer than the drain region 211 and covers the drain region 211, and the second doping region 331 is longer than the source region 210 and covers the source region 210. A triple ion implantation concentration gradient of "maximum doping concentration of the source region 210 and the drain region 211 - relatively high doping concentration of the lightly doped drain region 240 - relatively low doping concentration of the first doping region 330 and the second doping region 331 - minimum channel well injection doping concentration" can be formed between the drain and the channel center, effectively expanding the drain junction range, significantly reducing the electric field strength at the drain boundary, thereby reducing the number of secondary carriers at the drain boundary, reducing the probability of carrier radiation recombination, reducing carrier recombination luminescence, and improving the imaging quality of the image sensor.

[0119] Reference Figure 7 , Figure 7 4 is a schematic diagram of a mapping pattern of radiation power and threshold voltage based on different electric field buffer zone widths in an embodiment of the present invention.

[0120] like Figure 7 The simulation data shown shows that when the electric field buffer zone is increased by 50nm, the device's luminous intensity decreases by 50% compared to the unoptimized state. Furthermore, the luminous power is further halved for each 50nm increase in the electric field buffer zone width. Therefore, the solution of the present invention can effectively reduce transistor luminous intensity without adding any process steps or changing the original transistor design.

[0121] Specifically, when the implantation range of the buried channel doping region is expanded, the luminous intensity decreases as the implantation range of the buried channel is expanded, and the threshold voltage of the device decreases faster as the implantation range of the buried channel is expanded. Figure 7 As shown, adding a large buried-channel injection electric field buffer zone to the device channel significantly reduces the effective gate length and significantly changes the transistor's threshold voltage. This reduction rate accelerates as the width of the electric field buffer zone increases. Therefore, to ensure proper circuit operation, it is necessary to balance luminous intensity and device performance deviation within a relatively appropriate range.

[0122] On the other hand, for the same buried trench implant range, changing the implant dose will also affect the effectiveness of the scheme.

[0123] Reference Figure 8 , Figure 8 3 is a schematic diagram of a mapping pattern of radiation power and threshold voltage based on different buried channel doses in an embodiment of the present invention.

[0124] like Figure 8 The simulation data shown shows that, under the condition of a fixed electric field buffer width, increasing the implant dose will rapidly reduce the transistor's luminescence intensity, but it will also reduce the transistor's threshold voltage. Therefore, it is necessary to select an appropriate buried channel implant width and implant concentration based on the actual operating state of the circuit.

[0125] Reference Figure 9 , Figure 9 This is a schematic diagram of a mapping pattern of threshold voltage and radiation power based on buffer length and channel length in an embodiment of the present invention.

[0126] like Figure 9 The simulation data shown in the figure increases the gate length and the buried channel injection range at the same time. At this time, the transistor threshold voltage does not change significantly, but the luminescence level is reduced by an order of magnitude due to the significant expansion of the drain junction area.

[0127] It can be seen from the above that the specific implementation methods in the embodiments of the present invention can be used in combination with other solutions for reducing luminescence.

[0128] In an embodiment of the present invention, a CMOS image sensor is further provided. Figure 6As shown, it includes: a semiconductor substrate 200; a buried channel doped region, located in the semiconductor substrate 200; a gate structure 220, including a gate and a sidewall 223 located on the sidewall surface of the gate, located on the surface of the semiconductor substrate 200; a lightly doped drain region 240, located in the semiconductor substrate 200 on both sides of the gate; a source region 210 and a drain region 211, respectively located in the semiconductor substrate 200 on both sides of the gate structure 220; wherein the doping type of the buried channel doped region is the same as the doping type of the lightly doped drain region 240 The buried channel doping region is consistent with the doping concentration of the lightly doped drain region 240, and the doping concentration of the buried channel doping region is less than the doping concentration of the lightly doped drain region 240; the buried channel doping region includes a first doping region 330 located in the semiconductor substrate 200 on one side of the drain region 211, the first doping region 330 and the lightly doped drain region 240 on one side of the drain region 211 have an overlapping area, and the boundary of the first doping region 330 extends to below the gate 222; in the extension direction parallel to the device channel, the first doping region 330 is larger than the drain region 211 and covers the drain region 211.

[0129] Furthermore, the ion implantation depth for forming the first doped region 330 is greater than or equal to the ion implantation depth for forming the lightly doped drain region 240 .

[0130] Furthermore, the length of the portion of the first doped region 330 extending below the gate 222 does not exceed a first preset proportional length of the gate 222 ; wherein the direction of the length is consistent with the extension direction of the device channel.

[0131] Furthermore, the first preset ratio is determined based on the length of the gate 222 and the device turn-on voltage of the CMOS image sensor; wherein, the longer the length of the gate 222 is, the smaller the first preset ratio used to calculate the first preset ratio length is or remains unchanged; and the higher the device turn-on voltage is, the longer the first preset ratio length of the gate 222 is.

[0132] Furthermore, the buried channel doped region also includes a second doped region 331 located in the semiconductor substrate on one side of the source region, the second doped region 331 has an overlapping area with the lightly doped drain region 240 on one side of the source region 210, and the boundary of the second doped region 331 extends to the bottom of the gate 222; wherein, in the extension direction parallel to the device channel, the second doped region 331 is larger than the source region 210 and covers the source region 210.

[0133] Furthermore, the second doping region 331 and the first doping region 330 are formed by the same ion implantation process.

[0134] Furthermore, the length of the portion of the first doped region 330 extending below the gate 222 does not exceed the second preset proportional length of the gate 222, and the length of the portion of the second doped region 331 extending below the gate 222 does not exceed the third preset proportional length of the gate 222; wherein the direction of the length is consistent with the extension direction of the device channel.

[0135] Furthermore, the second preset ratio is determined based on the length of the gate 222 and the device turn-on voltage of the CMOS image sensor; wherein, the greater the length of the gate 222, the smaller the second preset ratio used to calculate the second preset ratio length is or remains unchanged, and the smaller the third preset ratio used to calculate the third preset ratio length is or remains unchanged; and the higher the device turn-on voltage, the greater the second preset ratio length of the gate 222, and the greater the third preset ratio length of the gate.

[0136] Regarding the principle, specific implementation and beneficial effects of the CMOS image sensor, please refer to the above description of the method for forming the CMOS image sensor, which will not be repeated here.

[0137] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a CMOS image sensor, characterized in that: include: providing a semiconductor substrate; forming a buried channel doped region in the semiconductor substrate; forming a gate on a surface of the semiconductor substrate; forming a lightly doped drain region, wherein the lightly doped drain region is located in the semiconductor substrate on both sides of the gate; forming sidewalls on the sidewall surfaces of the gate to obtain a gate structure; forming a source region and a drain region, wherein the source region and the drain region are respectively located in the semiconductor substrate on both sides of the gate structure; The doping type of the buried channel doping region is consistent with the doping type of the lightly doped drain region, and the doping concentration of the buried channel doping region is less than the doping concentration of the lightly doped drain region; The buried channel doped region includes a first doped region located in the semiconductor substrate on one side of the drain region, the first doped region and a lightly doped drain region on one side of the drain region having an overlapping area, and a boundary of the first doped region extends below the gate; In an extension direction parallel to the device channel, the first doped region is larger than the drain region and covers the drain region.

2. The method for forming a CMOS image sensor according to claim 1, wherein: The ion implantation depth for forming the first doped region is greater than or equal to the ion implantation depth for forming the lightly doped drain region.

3. The method for forming a CMOS image sensor according to claim 1, wherein: The length of the portion of the first doped region extending below the gate does not exceed a first preset proportional length of the gate; The direction of the length is consistent with the extension direction of the device channel.

4. The method for forming a CMOS image sensor according to claim 3, wherein: The first preset ratio for calculating the first preset ratio length is selected from 1 / 6 to 1 / 3.

5. The method for forming a CMOS image sensor according to claim 3, wherein: The first preset ratio is determined according to the length of the gate and the device turn-on voltage of the CMOS image sensor; The longer the length of the gate is, the smaller the first preset ratio used to calculate the first preset ratio length is or remains unchanged; The higher the device turn-on voltage is, the longer the first preset proportional length of the gate is.

6. The method for forming a CMOS image sensor according to claim 1, wherein: In a direction parallel to the surface of the semiconductor substrate and perpendicular to the extension direction of the device channel, the first doped region is larger than the drain region and covers the drain region.

7. The method for forming a CMOS image sensor according to claim 1, wherein: The parameters of the buried channel doping region formation process are selected from one or more of the following: The implanted ions include phosphorus ions; The implantation energy is 10KeV to 50KeV; The injection dose is 1E12atom / cm 2 to 5E12atom / cm 2 .

8. The method for forming a CMOS image sensor according to any one of claims 1 to 7, wherein: The buried channel doped region further includes a second doped region located in the semiconductor substrate on one side of the source region, the second doped region and the lightly doped drain region on one side of the source region having an overlapping area, and a boundary of the second doped region extends below the gate; Wherein, in an extension direction parallel to the device channel, the second doped region is larger than the source region and covers the source region.

9. The method for forming a CMOS image sensor according to claim 8, wherein: The second doping region and the first doping region are formed by using the same ion implantation process.

10. The method for forming a CMOS image sensor according to claim 8, wherein: The length of the portion of the first doped region extending below the gate does not exceed a second preset proportional length of the gate, and the length of the portion of the second doped region extending below the gate does not exceed a third preset proportional length of the gate; The direction of the length is consistent with the extension direction of the device channel.

11. The method for forming a CMOS image sensor according to claim 10, wherein: The second preset ratio for calculating the second preset ratio length is selected from 1 / 6 to 1 / 3, and the third preset ratio for calculating the third preset ratio length is selected from 1 / 6 to 1 / 3.

12. The method for forming a CMOS image sensor according to claim 10, wherein: The second preset ratio is equal to the third preset ratio.

13. The method for forming a CMOS image sensor according to claim 10, wherein: The second preset proportional length is determined according to the length of the gate and the device turn-on voltage of the CMOS image sensor; The longer the length of the gate is, the smaller the second preset ratio used to calculate the second preset ratio length is or remains unchanged, and the smaller the third preset ratio used to calculate the third preset ratio length is or remains unchanged; The higher the device turn-on voltage is, the longer the second preset proportional length of the gate is, and the longer the third preset proportional length of the gate is.

14. The method for forming a CMOS image sensor according to claim 8, wherein: In a direction parallel to the surface of the semiconductor substrate and perpendicular to the extension direction of the device channel, the second doped region is larger than the source region and covers the source region.

15. A CMOS image sensor, characterized in that: include: semiconductor substrates; a buried channel doped region, located in the semiconductor substrate; A gate structure, comprising a gate and a sidewall located on a sidewall surface of the gate, and located on a surface of the semiconductor substrate; a lightly doped drain region located in the semiconductor substrate on both sides of the gate; a source region and a drain region, respectively located in the semiconductor substrate on both sides of the gate structure; The doping type of the buried channel doping region is consistent with the doping type of the lightly doped drain region, and the doping concentration of the buried channel doping region is less than the doping concentration of the lightly doped drain region; The buried channel doped region includes a first doped region located in the semiconductor substrate on one side of the drain region, the first doped region and a lightly doped drain region on one side of the drain region having an overlapping area, and a boundary of the first doped region extends below the gate; In an extension direction parallel to the device channel, the first doped region is larger than the drain region and covers the drain region.

16. The CMOS image sensor according to claim 15, wherein: The ion implantation depth for forming the first doped region is greater than or equal to the ion implantation depth for forming the lightly doped drain region.

17. The CMOS image sensor according to claim 15, wherein: The length of the portion of the first doped region extending below the gate does not exceed a first preset proportional length of the gate; The direction of the length is consistent with the extension direction of the device channel.

18. The CMOS image sensor according to claim 17, wherein: The first preset ratio is determined according to the length of the gate and the device turn-on voltage of the CMOS image sensor; The longer the length of the gate is, the smaller the first preset ratio used to calculate the first preset ratio length is or remains unchanged; The higher the device turn-on voltage is, the longer the first preset proportional length of the gate is.

19. The CMOS image sensor according to any one of claims 15 to 18, wherein: The buried channel doped region further includes a second doped region located in the semiconductor substrate on one side of the source region, the second doped region and the lightly doped drain region on one side of the source region having an overlapping area, and a boundary of the second doped region extends below the gate; Wherein, in an extension direction parallel to the device channel, the second doped region is larger than the source region and covers the source region.

20. The CMOS image sensor according to claim 19, wherein: The second doping region and the first doping region are formed by using the same ion implantation process.

21. The CMOS image sensor according to claim 19, wherein: The length of the portion of the first doped region extending below the gate does not exceed a second preset proportional length of the gate, and the length of the portion of the second doped region extending below the gate does not exceed a third preset proportional length of the gate; The direction of the length is consistent with the extension direction of the device channel.

22. The CMOS image sensor according to claim 21, wherein: The second preset ratio is determined according to the length of the gate and the device turn-on voltage of the CMOS image sensor; The longer the length of the gate is, the smaller the second preset ratio used to calculate the second preset ratio length is or remains unchanged, and the smaller the third preset ratio used to calculate the third preset ratio length is or remains unchanged; The higher the device turn-on voltage is, the longer the second preset proportional length of the gate is, and the longer the third preset proportional length of the gate is.

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